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The pod assembly consists of two sub-assemblies. The universal Port Replacement Unit ( is the larger board that carries the small Processor Module ( ) daughterboard. has three headers on the bottom that carry the signals to the target. The also has a 50-pin header J1 that connects through the ribbon cable to the emulator board.
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Note: Taking power from the target system is not recommended. Note: Both pins of the controller are shorted together. USB Power Select (USL): V Source Select This jumper selects how to power the V pin of the controller. When the jumper top is across pins 1 and 2, V is connected to the V of the emulator.
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• Watchdog timer • Oscillator watchdog • Timer0 • Timer1 • When the jumper top is on, the mode is selected. In this case, only some of the internal BREAK peripherals are stopped. This includes the following controller peripherals. • Interrupts •...
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JP7 (External Code Enable) This jumper enables access to the external code if the single-chip mode is emulated and part of the code is mapped into the target code memory. The external code is enabled if the jumper top is out. Reset Button When pressed, this switch resets the pod (including the controller).
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Emulation LED The Emulation (green ) turns on whenever the user program is running, and turns off whenever the user program is stopped (emulation break). The user code can be fetched from on the emulator board or from code memory on the target (usually PROM Monitor LED The Monitor...
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default state of single-chip mode when the target does not force this pin. This difference must be taken into account if the target pin is tied to a pull-down resistor. A sufficiently low pull- down (1.5K or lower) is required to overcome the 22K pull-up resistor on the pod. •...
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Port0 and Port2 Pins—The pod emulates these 16 port pins, used as the address/data bus and as port pins. These pins have slightly different characteristics from the Port0 and Port2 pins of the controller. These pins sink up to 12 mA and source up to 4 mA, while main- taining valid output logic levels.
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