Analog Devices dBCOOL ADT7463 Instruction Manual

Remote thermal controller and voltage monitor

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FEATURES

Monitors up to 5 Supply Voltages

Controls and Monitors up to 4 Fan Speeds

1 On-Chip and 2 Remote Temperature Sensors

Monitors up to 6 Processor VID Bits

Dynamic T

Control Mode Optimizes System

MIN

Acoustics Intelligently

Automatic Fan Speed Control Mode Controls System

Cooling Based on Measured Temperature

Enhanced Acoustic Mode Dramatically Reduces User

Perception of Changing Fan Speeds

Thermal Protection Feature via THERM Output

Monitors Performance Impact of Intel

Processor Thermal Control Circuit via THERM Input

2-Wire and 3-Wire Fan Speed Measurement

Limit Comparison of All Monitored Values

Meets SMBus 2.0 Electrical Specifications

(Fully SMBus 1.1 Compliant)

APPLICATIONS

Low Acoustic Noise PCs

Networking and Telecommunications Equipment

www.BDTIC.com/ADI

*Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

Pentium

FUNCTIONAL BLOCK DIAGRAM

VID5

VID4

VID3

VID2

VID1

VID0

PWM1

PWM

REGISTERS

ENHANCEMENT

PWM2

AND

CONTROLLERS

PWM3

TACH1

TACH2

TACH3

TACH4

PERFORMANCE

MONITORING

THERM

PROTECTION

TO ADT7463

D1+

D1–

D2+

D2–

CONDITIONING

+5V

+12V

MULTIPLEXER

+2.5V

CCP

BAND GAP

TEMP. SENSOR

dB COOL

Controller and Voltage Monitor

GENERAL DESCRIPTION

The ADT7463 dBCOOL controller is a complete systems

monitor and multiple PWM fan controller for noise-sensitive

applications requiring active system cooling. It can monitor

12 V, 5 V, and 2.5 V CPU supply voltages, plus its own supply

voltage. It can monitor the temperature of up to two remote

sensor diodes, plus its own internal temperature. It can measure

and control the speed of up to four fans so that they operate at the

lowest possible speed for minimum acoustic noise. The automatic

fan speed control loop optimizes fan speed for a given temperature.

A unique dynamic T

thermals/acoustics to be intelligently managed. The effectiveness

of the system's thermal solution can be monitored using the

THERM input. The ADT7463 also provides critical thermal

protection to the system using the bidirectional THERM pin

as an output to prevent system or component overheating.

ADDR

ADDR EN

SELECT

SCL SDA

VID

SMBUS

SERIAL BUS

ADDRESS

INTERFACE

SELECTION

AUTOMATIC

ACOUSTIC

FAN SPEED

CONTROL

DYNAMIC

MIN

CONTROL

FAN SPEED

COUNTER

THERMAL

ADT7463

10-BIT

INPUT

ADC

SIGNAL

AND

ANALOG

BAND GAP

REFERENCE

GND

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

Remote Thermal

™

ADT7463

control mode enables the system

MIN

SMBALERT

ADDRESS

POINTER

PWM

CONFIGURATION

REGISTERS

INTERRUPT

MASKING

INTERRUPT

STATUS

REGISTERS

LIMIT

COMPARATORS

VALUE AND

LIMIT

REGISTERS

www.analog.com

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Summary of Contents for Analog Devices dBCOOL ADT7463

Page 1 *Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O.
Page 2 1, 2, 3, 4 ADT7463–SPECIFICATIONS to T to V , unless otherwise noted.) Parameter Unit Test Conditions/Comments POWER SUPPLY Supply Voltage Supply Current, I Interface Inactive, ADC Active µA Standby Mode TEMPERATURE-TO-DIGITAL CONVERTER ± 0.5 ± 1.5 Local Sensor Accuracy 70 C ±...
Page 3 ADT7463 Parameter Unit Test Conditions/Comment DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, V Maximum Input Voltage Input Low Voltage, V +0.8 –0.3 Minimum Input Voltage Hysteresis V p-p DIGITAL INPUT LOGIC LEVELS (THERM) AGTL+ Input High Voltage, V 0.75 Input Low Voltage, V DIGITAL INPUT CURRENT...
Page 4: Absolute Maximum Ratings
ADT7463 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION Positive Supply Voltage (V ) ..... 6.5 V Voltage on +12V Pin ......20 V PWM1/XTO Voltage on Any Other Input or Output Pin .
Page 5 ADT7463 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus. Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up. Ground Pin for the ADT7463. Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. V is also monitored through this pin.
Page 6: Functional Description
ADT7463 FUNCTIONAL DESCRIPTION INTERNAL REGISTERS OF THE ADT7463 General Description A brief description of the ADT7463’s principal internal registers The ADT7463 is a complete systems monitor and multiple fan is given below. More detailed information on the function of controller for any system requiring monitoring and cooling. The each register is given in Tables IV to XLII.
Page 7 Typical Performance Characteristics–ADT7463 –3 REMOTE TEMPERATURE ERROR ( C) HIGH LIMIT –6 –9 DXP TO GND –12 +3 SIGMA –15 –18 –5 –3 SIGMA –21 DXP TO V (3.3V) –1 –24 –10 –27 LOW LIMIT –2 –30 –15 –33 –36 –3 –20 10.0...
Page 8 ADT7463 ADT7463 FRONT CHASSIS TACH2 PWM1 TACH1 PWM3 REAR 5(VRM9)/6(VRM10) CHASSIS TACH3 VID[0:4]/VID[0:5] D2– THERM PROCHOT AMBIENT TEMPERATURE D1– 3.3VSB 12V/VID5 COMP SMBALERT ADP316x CURRENT CONTROLLER CORE Figure 2. Recommended Implementation • VRM temperature uses local temperature sensor. RECOMMENDED IMPLEMENTATION www.BDTIC.com/ADI Configuring the ADT7463 as in Figure 2 allows the systems •...
Page 9: Serial Bus Interface
ADT7463 SERIAL BUS INTERFACE The ability to make hardwired changes to the SMBus slave Control of the ADT7463 is carried out using the serial system address allows the user to avoid conflicts with other devices sharing management bus (SMBus). The ADT7463 is connected to this the same serial bus, for example, if more than one ADT7463 is bus as a slave device, under the control of a master controller.
Page 10 ADT7463 2. Data is sent over the serial bus in sequences of nine clock in one operation because the type of operation is determined at pulses, eight bits of data followed by an Acknowledge Bit the beginning and cannot subsequently be changed without from the slave device.
Page 11 ADT7463 ACK. BY START BY ACK. BY STOP BY ADT7463 MASTER ADT7463 MASTER FRAME 1 FRAME 2 SERIAL BUS ADDRESS ADDRESS POINTER REGISTER BYTE BYTE Figure 8. Writing to the Address Pointer Register Only ACK. BY START BY NO ACK. BY STOP BY ADT7463 MASTER...
Page 12: Smbus Timeout
ADT7463 ADT7463 WRITE OPERATIONS ADT7463 READ OPERATIONS The SMBus specification defines several protocols for different The ADT7463 uses the following SMBus read protocols. types of read and write operations. The ones used in the ADT7463 Receive Byte are discussed below. The following abbreviations are used in the This is useful when repeatedly reading a single register.
Page 13 ADT7463 VOLTAGE MEASUREMENT INPUTS VOLTAGE MEASUREMENT LIMIT REGISTERS The ADT7463 has four external voltage measurement channels. Associated with each voltage measurement channel are high and It can also measure its own supply voltage, V low limit registers. Exceeding the programmed high or low limit causes the appropriate status bit to be set.
Page 14 ADT7463 Table II. 10-Bit A/D Output Code vs. V Input Voltage A/D Output +12V (3.3V +2.5V Decimal Binary (10 Bits) <0.0156 <0.0065 <0.0042 <0.0032 <0.00293 00000000 00 0.0156–0.0312 0.0065–0.0130 0.0042–0.0085 0.0032–0.0065 0.0293–0.0058 00000000 01 0.0312–0.0469 0.0130–0.0195 0.0085–0.0128 0.0065–0.0097 0.0058–0.0087 00000000 10 0.0469–0.0625 0.0195–0.0260 0.0128–0.0171...
Page 15 ADT7463 logic states on the VID inputs are different than they were 11 µs VID CODE MONITORING The ADT7463 has five dedicated voltage ID (VID code) inputs. previously. The change of VID code can be used to generate an SMBALERT interrupt. If an SMBALERT interrupt is These are digital inputs that can be read back through the VID register (Reg.
Page 16: Temperature Measurement System
ADT7463 TEMPERATURE MEASUREMENT SYSTEM value of V varies from device to device and individual calibra- Local Temperature Measurement tion is required to null this out, so the technique is unsuitable The ADT7463 contains an on-chip band gap temperature sensor for mass production. The technique used in the ADT7463 is to whose output is digitized by the on-chip 10-bit ADC.
Page 17 ADT7463 If a discrete transistor is used, the collector will not be grounded and should be linked to the base. If a PNP transistor is used, the ADT7463 base is connected to the D– input and the emitter to the D+ 2N3904 input.
Page 18 ADT7463 Temperature Measurement Registers Single-Channel ADC Conversions Reg. 0x25 Remote 1 Temperature = 0x80 Default Setting Bit 6 of Configuration Register 2 (Reg. 0x73) places the ADT7463 into single-channel ADC conversion mode. In this Reg. 0x26 Local Temperature = 0x80 Default mode, the ADT7463 can be made to read a single temperature Reg.
Page 19 ADT7463 LIMITS, STATUS REGISTERS, AND INTERRUPTS Fan Limit Registers Reg. 0x54 TACH1 Minimum Low Byte = 0xFF Default Limit Values Associated with each measurement channel on the ADT7463 Reg. 0x55 TACH1 Minimum High Byte = 0xFF Default are high and low limits. These can form the basis of system Reg.
Page 20 ADT7463 Analog Monitoring Cycle Time The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (Reg. 0x40). The ADC measures each analog input in turn and as each measurement is completed, the result is automatically stored in the appropriate value register.
Page 21 ADT7463 Read/Write HIGH LIMIT (Click 10000000 Digits) 2.5V TEMPERATURE OOL = 1 DENOTES A PARAMETER MONITORED THROUGH STATUS REG 2 CLEARED ON READ IS OUT-OF-LIMIT (TEMP BELOW LIMIT) “STICKY” Figure 21. Status Register 1 STATUS TEMP BACK IN LIMIT Status Register 1 (Reg. 0x41) (STATUS BIT STAYS SET) SMBALERT Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and...
Page 22 ADT7463 To Assign THERM Functionality to a Pin Masking Interrupt Sources Pin 14 or Pin 20 can be configured as the THERM pin on the Interrupt Mask Registers 1 and 2 are located at Addresses 0x74 and 0x75. These allow individual interrupt sources to be ADT7463.
Page 23 ADT7463 Figure 26 illustrates how the THERM timer behaves as the THERM TIMER The ADT7463 has an internal timer to measure THERM asser- THERM input is asserted and negated. Bit 0 gets set on the first tion time. For example, the THERM input may be connected THERM assertion detected.
Page 24 ADT7463 2.914s 2.914s 1.457s 1.457s 728.32ms 728.32ms THERM LIMIT THERM 364.16ms 364.16ms (REG. 0x7A) TIMER 182.08ms 182.08ms (REG. 0x79) 91.04ms 91.04ms 45.52ms 45.52ms 22.76ms 22.76ms THERM 7 6 5 4 3 2 1 0 THERM TIMER CLEARED ON READ COMPARATOR F4P BIT (BIT 5) SMBALERT STATUS REGISTER 2...
Page 25 ADT7463 Configuring the ADT7463 THERM Pin as an Output pull-up on the gate is tied to 5 V. The MOSFET should also have In addition to the ADT7463 being able to monitor THERM as a low on resistance to ensure that there is not significant voltage an input, the ADT7463 can optionally drive THERM low as an drop across the FET.
Page 26 ADT7463 Driving Two Fans from PWM3 Driving up to Three Fans from PWM2 Note that the ADT7463 has four TACH inputs available for fan TACH measurements for fans are synchronized to particular speed measurement, but only three PWM drive outputs. If a PWM channels, e.g., TACH1 is synchronized to PWM1.
Page 27 ADT7463 Driving 2-Wire Fans LAYING OUT 2-WIRE AND 3-WIRE FANS Figure 33 shows how a 2-wire fan may be connected to the Figure 35 shows how to lay out a common circuit arrangement ADT7463. This circuit allows the speed of a 2-wire fan to be for 2-wire and 3-wire fans.
Page 28 ADT7463 measured by gating an on-chip 90 kHz oscillator into the input of a 16-bit counter for N periods of the fan TACH output (Figure 37), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the ADT7463 PULL-UP 4.7k...
Page 29 ADT7463 Fan TACH Limit Registers 00 = 1 Pulse per Revolution. The fan TACH limit registers are 16-bit values consisting of 01 = 2 Pulses per Revolution. two bytes. 10 = 3 Pulses per Revolution. Reg. 0x54 TACH1 Minimum Low Byte = 0xFF Default 11 = 4 Pulses per Revolution.
Page 30 ADT7463 PWM1 CONFIGURATION (REG. 0x5C) PWM1 FREQUENCY REGISTERS (REG. 0x5F to 0x61) <2:0> SPIN These bits control the start-up timeout for PWM1. <2:0> FREQ 000 = 11.0 Hz 001 = 14.7 Hz 000 = No Startup Timeout 010 = 22.1 Hz 001 = 100 ms 011 = 29.4 Hz 010 = 250 ms (default)
Page 31: Power-On Default
ADT7463 By reading the PWMx current duty cycle registers, users can Note that since other voltages can drop or be turned off during keep track of the current duty cycle on each PWM output, even a low power state, these voltage channels set status bits or generate SMBALERTs.
Page 32 ADT7463 Table IV. ADT7463 Registers Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable? 0x20 2.5 V Reading 0x00 0x21 Reading 0x00 0x22 Reading 0x00 0x23 5 V Reading 0x00 0x24 12 V Reading...
Page 33 ADT7463 Table IV. ADT7463 Registers (continued) Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable? 0x5C R/W PWM1 Configuration Register BHVR BHVR BHVR SLOW SPIN SPIN SPIN 0x62 0x5D R/W PWM2 Configuration Register BHVR...
Page 34 ADT7463 Table V. Voltage Reading Registers (Power-On Default = 0x00) Register Address Description 0x20 Read-Only 2.5 V Reading (8 MSBs of reading) 0x21 Read-Only Reading: holds processor core voltage measurement (8 MSBs of reading) 0x22 Read-Only Reading: measures V through the V pin (8 MSBs of reading) 0x23 Read-Only...
Page 35 ADT7463 Table VIII. Current PWM Duty Cycle Registers (Power-On Default = 0xFF) Register Address Description 0x30 Read/Write PWM1 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF) 0x31 Read/Write PWM2 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF) 0x32 Read/Write PWM3 Current Duty Cycle (0% to 100% Duty Cycle = 0x00 to 0xFF)
Page 36 ADT7463 Table X. Register 0x36 – Dynamic T Control Register 1 (Power-On Default = 0x00) Name Description <0> CYR2 Read/Write MSB of 3-Bit Remote 2 Cycle Value. The other two bits of the code reside in Dynamic T Control Register 2 (Reg. 0x37). These three bits define the delay time between making sub- sequent T adjustments in the control loop, in terms of number of monitoring cycles.
Page 37 ADT7463 Table XI. Register 0x37 – Dynamic T Control Register 2 (Power-On Default = 0x00) Name R/W* Description <2:0> CYR1 Read/Write 3-Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent T adjustments in the control loop for the Remote 1 channel, in terms of number of monitoring cycles.
Page 38 ADT7463 Table XII. Register 0x40 – Configuration Register 1 (Power-On Default = 0x00) Name Description <0> STRT Read/Write Logic 1 enables monitoring and PWM control outputs based on the limit settings pro- grammed. Logic 0 disables monitoring and PWM control based on the default power-up limit settings.
Page 39 ADT7463 Table XIV. Register 0x42 – Interrupt Status Register 2 (Power-On Default = 0x00) Name Description <0> 12V/VC Read-Only A one indicates the 12 V high or low limit has been exceeded. This bit gets cleared on a read of the status register only if the error condition has subsided. If Pin 21 is configured as VID5, this bit is the VID change bit.
Page 40 ADT7463 Table XVII. Temperature Limit Registers Register Address Description Power-On Default 0x4E Read/Write Remote 1 Temp Low Limit 0x81 0x4F Read/Write Remote 1 Temp High Limit 0x7F 0x50 Read/Write Local Temp Low Limit 0x81 0x51 Read/Write Local Temp High Limit 0x7F 0x52 Read/Write...
Page 41 ADT7463 Table XIX. PWM Configuration Registers Register Address R/W* Description Power-On Default 0x5C Read/Write PWM1 Configuration 0x62 0x5D Read/Write PWM2 Configuration 0x62 0x5E Read/Write PWM3 Configuration 0x62 Name Description <2:0> SPIN Read/Write These bits control the startup timeout for PWMx. The PWM output stays high until two valid TACH rising edges are seen from the fan.
Page 42 ADT7463 Table XX. TEMP T /PWM Frequency Registers RANGE Register Address R/W* Description Power-On Default 0x5F Read/Write Remote 1 T /PWM 1 Frequency 0xC4 RANGE 0x60 Read/Write Local Temp T /PWM 2 Frequency 0xC4 RANGE 0x61 Read/Write Remote 2 T /PWM 3 Frequency 0xC4 RANGE...
Page 43 ADT7463 Table XXI. Register 0x62 – Enhance Acoustics Reg 1 (Power-On Default = 0x00) Name R/W* Description <2:0> ACOU Read/Write These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jump- ing instantaneously to its newly calculated speed, PWM1 ramps gracefully at the rate determined by these bits.
Page 44 ADT7463 Table XXII. Register 0x63 – Enhance Acoustics Reg 2 (Power-On Default = 0x00) Name R/W* Description <2:0> ACOU3 Read/Write These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jump- ing instantaneously to its newly calculated speed, PWM3 ramps gracefully at the rate determined by these bits.
Page 45 ADT7463 Table XXIII. PWM Min Duty Cycle Registers Register Address R/W* Description Power-On Default 0x64 Read/Write PWM1 Min Duty Cycle 0x80 (50% duty cycle) 0x65 Read/Write PWM2 Min Duty Cycle 0x80 (50% duty cycle) 0x66 Read/Write PWM3 Min Duty Cycle 0x80 (50% duty cycle) Name Read/Write...
Page 46 ADT7463 Table XXVII. XOR Tree Test Enable Register Address R/W* Description Power-On Default 0x6F Read/Write XOR Tree Test Enable Register 0x00 <0> If the XEN bit is set to 1, the device enters the XOR Tree Test Mode. Clearing the bit removes the device from the XOR Test Mode.
Page 47 ADT7463 Table XXXI. Register 0x73 – Configuration Register 2 (Power-On Default = 0x00) Name R/W* Description AIN1 Read/Write AIN1 = 0, Speed of 3-wire fans measured using the TACH output from the fan. AIN1 = 1, Pin 11 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor.
Page 48 ADT7463 Table XXXII. Register 0x74 – Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00) Name Description A one masks SMBALERT for out-of-limit conditions on the 2.5 V channel. 2.5V Read/Write A one masks SMBALERT for out-of-limit conditions on the V Read/Write channel.
Page 49 ADT7463 Table XXXVI. Register 0x78 – Configuration Register 3 (Power-On Default = 0x00) Name R/W* Description ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt <0> ALERT Read/Write output to indicate out-of-limit error conditions. THERM THERM Enable = 1 enables THERM monitoring functionality on the pin <1>...
Page 50 ADT7463 Table XXXIX. Register 0x7B – Fan Pulses per Revolution Register (Power-On Default = 0x55) Name Description <1:0> FAN1 Read/Write Sets number of pulses to be counted when measuring FAN 1 speed. Can be used to determine fan’s pulses per revolution for unknown fan type. Pulses Counted 00 = 1 01 = 2 (Default)
Page 51: Outline Dimensions
ADT7463 OUTLINE DIMENSIONS 24-Lead Shrink Small Outline Package [QSOP] (RQ-24) Dimensions shown in inches 0.341 0.154 0.236 PIN 1 0.065 0.069 0.049 0.053 0.010 0.025 0.012 SEATING 0.050 0.004 0.010 PLANE 0.008 0.016 0.006 COPLANARITY 0.004 COMPLIANT TO JEDEC STANDARDS MO-137AE www.BDTIC.com/ADI REV.
Page 52 ADT7463 Revision History Location Page 10/04—Data Sheet Changed from REV. B to REV. C. Updated ORDERING GUIDE ................4 Change to Table IV .

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Summary of Contents for Analog Devices dBCOOL ADT7463

Page 4: Absolute Maximum Ratings

Page 6: Functional Description

Page 9: Serial Bus Interface

Page 12: Smbus Timeout

Page 16: Temperature Measurement System

Page 31: Power-On Default

Page 51: Outline Dimensions

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