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IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-13
Q301 : CS42518 (8-ch Codec with S/PDIF Receiver)-2/4
PIN CONFIGURATION
CX_SDIN1
CX_SCLK
CX_LRCK
DGND
VLC
SCL/CCLK
SDA/CDOUT
AD1/CDIN
AD0/CS
INT
RST
AINR-
AINR+
AINL+
AINL-
TERMINAL DESCRIPTION(1/3)
Pin Name
#
CX_SDIN1
1
Codec Serial Audio Data Input (Input) - Input for two's complement serial audio data.
CX_SDIN2
64
CX_SDIN3
63
CX_SDIN4
62
CX_SCLK
2
CODEC Serial Clock (Input/Output) - Serial clock for the CODEC serial audio interface
CX_LRCK
3
CODEC Left Right Clock (Input/ Output) - Determines which channel, Left or Right, is currently active on
the CODEC serial audio data line.
VD
4
Digital Power (Input) - Positive power supply for the digital section.
51
DGND
5
Digital Ground (Input) - Ground reference. Should be connected to digital ground.
52
VLC
6
Control Port Power (Input) - Determines the required signal level for the control port.
SCL/CCLK
7
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I2C mode as shown in the Typical Connection Diagram.
SDA/CDOUT
8
Serial Control Data (Input/Output) - SDA is a data I/O line in IC mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.
AD1/CDIN
Address Bit 1 (I2C)/Serial Control Data (SPI) (Input) - AD1 a chip address pin in I2C mode; CDIN is
9
the input data line for control port interface in SPI mode.
1
2
3
VD
4
5
6
7
8
CS42518
9
10
11
12
13
14
15
16
Pin Description
TX-SR504/504E/8450
48
RXP1/GP01
47
RXP1/GP01
46
RXP1/GP01
45
RXP1/GP01
44
RXP1/GP01
43
RXP1/GP01
42
RXP1/GP01
41
VARX
40
AGND
39
LPFLT
38
MUTEC
37
AOUTA1-
36
AOUTA1+
35
AOUTB1+
34
AOUTB1-
33
AOUTA2-
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