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SGS ATES Z80 Instruction Set

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Summary of Contents for SGS ATES Z80

  • Page 2 Z80 CPU is not intended exclusively as an application support device itself but forms second part of the instruction manual SGS-ATES CLZ80 microcomputer, which is based on the Z80 microprocessor. paragraphs therefore numbered accordingly.
  • Page 3 [;07£: Execution time (E.T.) for each instruction given in nicroseconds for an assuoed clock. Total HllZ P.lachine cycles (H) are indicated I/ith total clock periods (T States). Also indicated the nuober States for each M cycle. For exanple: indicates that instruction consists of 2 nachine...
  • Page 4 Z 80 INSTRUCTION TABLE OF CONTENTS SECTION PAGE 8 BIT LOAD GROUP. 16 BIT LOAD GROUP. EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP 8 BIT ARITHMETIC AND LOGICAL GROUP GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS. 16 BIT ARITHMETIC GROUP ROTATE AND SHIFT GROUP SET,...
  • Page 6 <:Juanlurn c!cc 391262 SoJt Jr.ml.~ tOl.
  • Page 7 The contents of any register are loaded into other register r. Note: r,r' identifies any of the registers A, B, C, D, E, or L, assembled as follows in the object code: COOl DOlO If the register contains the number 8AH, register contains...
  • Page 8 a:o~r~< < "1 I,,: in::: The eight-bit integer n is loaded into any register where r identifies register C, D, E, H or L, assembled as follows in the object code: Register 1 11...
  • Page 9 (HLJ The eight-bit contents of memory location (HL) loaded into register r, where r identifies register B, C, D, E, H or L, assembled as follo~ls in the object code: BODO COOl DOlO If register pair HL contains the number 7SA1H, memory address...
  • Page 10 (IX +dJ > < < < < Ia:<-~r~«ol >: : operand (IX+d) (the contents Index Register IX summed with displacement integer d) is loaded into register r, where identifies register B, C, D, E, H or L, assembled follows object code: Register If the...
  • Page 11 will cause calculation of the 25AFH 19H, which points to memory location 25C8H. If this address contains byte 39H, ins'truction will result register B also containing 39H.
  • Page 12 (IY+dJ < < < < < < o>~r~< < °1 :< : : •. The operand (IY+d) (the contents of the Index Register IY sUQQed with a displacement integer is loaded into register r, where r identifies register C, D, E, H or L, assembled as follows in the object...
  • Page 13 If the Index Register IY contains number 2SAFll, instruction will cause the calculation sum 2SAFll 19H, which points memory location 2SC8H. If this address contains byte 39H, instruction will result register B also containing 39H.
  • Page 14 CHLJ, 0 : 1 : 1 : 1 : 0 ~r The contents of register r are loaded into menory location specified by the contents of the register pair. symbol r identifies register A, B, C, D, E, or L, assembled as follows in the object code:...
  • Page 15 LD (IX + dJ, >: > : > > IO»>:o:~r~1 < : : •. I" : : contents of register r are loaded into the memory address specified by the contents of Index Register summed with d, a two's complement displacement integer.
  • Page 16 If the C register contains the byte lCH, Index Register IX contains 3100H, then instruction will perform the sum 3100H 6H and will load lCH into memory location 3106H.
  • Page 17 CIY + dJ, > > > > > > IO:«<o~r+-1 < : : •. 1< : : The contents of register r are loaded into memory address specified the sum of contents Index Register IY and d, a two's complenent displacenent integer.
  • Page 18 If the C register contains the byte 48H, Index Register.IY contains 2AIIH, then the instruction will perform the sum 2AIIH 4H, and will load into memory location 2A15.
  • Page 19 (HLJ, < < < < : 0 : "1 I .• Integer n is loaded into the memory address specified the contents of the HL register pair. will result in the memory location 4444H containing byte 281I.
  • Page 20 (IX +dJ, > > : > > > > > > > :< : : 1< : 1< : >1 In: : : The n operand is loaded into the memory address specified by the sum of the contents of the Index Register the two's...
  • Page 21 > < < < < < < > > > > < : : ;. 1< : : 1< : : : :- Integer n is loaded into the memory location specified by the contents of the Index Register sUDDed with displacement integer...
  • Page 22 (Be) The contents of the memory location specified by the contents of the BC register pair loaded into AccuJ:lulator. If the BC register pair contains the number 4747H, J:leJ:lory address 4747H contains the byte 1ZH, then instruc tion...
  • Page 23 (DE) contents of the memory location specified by the reg~ster pair DE are loaded into the Accumulator. If the DE register pair contains the number 30A2H memory address 30A2H contains the byte 22H, then instruction...
  • Page 24 LD A, (nn) 2.1.14 (nn) Operation: Format: Opcode Operands (nn) >: < < 0 : 0 : I'; : : : ;. 1< : The contents of the memory location specified operands nn are loaded into the Accumulator. first memory n operand is the low order byte...
  • Page 25 (Be), The contents of the Accumulator are loaded into memory location specified by the contents of the register pair If the Accumulator contains 7AH and the BG register pair contains 1212H instruction...
  • Page 26 (DE], contents of the Accuflulator are loaded into memory location specified by the DE register pair. If the contents of register pair DE are ll28H, Accuculator contains byte AOH, instruction...
  • Page 27 [nnJ, > > > :a :a 1< : In: : : :-1 >1 1< : The contents of the Accumulator are loaded into memory address specified by the operands first n operand in the assembled object code above is the order byte of nn,...
  • Page 28 LD A, > > : > > : > < > > 0 : 1 : 0 : 0 : 1 The contents of the Interrupt Vector Register I are loaded into the Accumulator. Set if I-Reg. is negative; reset otherwise Set if I-Reg.
  • Page 29 > > : > > : > > > > > > > The contents of llemory Refresh Register R are loaded into the Accumulator. Set if R-Reg. is negative; reset otherwise Set if R-Reg. is zero; reset otherwise Re se t P/V: Contains contents...
  • Page 30 > > > < < < > > > > :a :a The contents of the Accunulator are loaded into Interrupt Control Vector Register, If the Accumulator contains the number B1R, after instruction...
  • Page 31 > > > < < < > > > > > :a :a The contents of the Accumulator are loaded into Memory Refresh register If the Accumulator contains the number B4H, after instruction...
  • Page 33 I" : : : ;. I" : "1 two-byte integer nn is loaded into the dd register pair, where dd defines BC, DE, HL, or SP register pairs, assembled as follows in the object code: first n operand asseobled object code is the low order...
  • Page 34 < > > > > < >: > a: a a: a: a: a : : •. I .• : : •• I .• Integer nn is loaded into Index Register first n operand in the assembled object code above the low order byte.
  • Page 35 11:<1:1»:0>1 < I" "1 I In; I I : In; I I ,.1 Integer nn is loaded into Index Register first n operand in the assembled object code above the low order byte.
  • Page 36 (nn) a : a : I., : : : •. I., : "1 The contents of memory address are loaded into low order portion of register pair (register the contents of the next highest memory address nn+l are loaded into the high order portion...
  • Page 37 (nn) n: : 11 : 1 : 1 : 1 : 1 I" : : : ,. I .• The contents of address are loaded into the low order portion of register pair the contents the next highest memory address nn+l are loaded into...
  • Page 38 If Address 2130ll contains 65ll and address 2131H contains 78ll after the instruction...
  • Page 39 (nn) 11 : 1 : 1 : 1 : 1 : < : 0 : 1 : 0 : 1 : 0 : 1< : 1< : >1 The contents of the address are loaded into order portion of Index Register IX, and the contents...
  • Page 40 (nn] < < < < < < > > > : in: 1< : : ;. contents of address are loaded into order portion of Index Register IY, and the content the next highest cemory address nn+l are loaded the high order portion of IY.
  • Page 41 (nn], < < a: a: a: a: a: 1< : I" : The contents of the low order portion of register pair (register are loaded into memory address the contents of the high order portion (register are loaded into the next highest memory address...
  • Page 42 (nn], : 1 : 1 : 0: 1 : 1: 1°:1:«0:0:1:11 1< : "I order byte of register pair dd is loaded into memory address upper byte is loaded into memory address nn+1 • Register pair dd defines either BC, DE, HL, or SP, assembled as follows in the object...
  • Page 43 If register pair BG contains the number 4644H, instruc tion will result in 44H in memory location lOOOH, memory location lOOlH.
  • Page 44 (nnJ, 11: 1: 1 : 1: 1: < 1< : In: : : :- 1< : In! : : The low order byte in Index Register IX is loaded into memory address upper order byte is loaded into the next highest address nn+l...
  • Page 45 (nn), > < < < < 0: 0: 1 : : 0: 1: 1< : >1 The low order byte in Index Register IY is loaded into memory address the upper order byte is loaded into memory location nn+l first n operand assembled object...
  • Page 46 The contents of the register pair HL are loaded into Stack Pointer If the register pair contains 442EH, after instruction...
  • Page 47 > > > > < < < < < < < a: a: two byte contents of Index Register IX are loaded into the Stack Pointer If the contents of the Index Register IX are 98DAH, after the instruction...
  • Page 48 > > > > > > > > > > > :a :a two byte contents of Index Register IY are loaded into Stack Pointer Index Register IY contains integer A227U, after the instruction...
  • Page 49 PUSH The contents of the register pair qq are pushed into external memory LIFO (last-in, first-out) Stack. Stack Pointer (SP) register pair holds 16-bit address of the current "top" of the Stack. This instruction first decrements SP and loads the high order byte of register...
  • Page 50 PUSH > : > > : > > > > : > > contents of the Index Register IX are pushed into external memory LIFO (last-in, first-out) Stack. Stack Pointer (SP) register pair holds l6-bit address of the current "top" of the Stack.
  • Page 51 PUSH »»>:0>1 > : > > > 0 : 0 The contents of the Index Register IY are pushed into the external ~emory LIFO (last-in, first-out) Stack. Stack Pointer (SP) register. pair holds 16-bit address of the current "top" of the Stack.
  • Page 52 top two bytes of the external memory LIFO (last-in, first-out) Stack popped into register pair Stack Pointer (SP) register pair holds 16-bit address of the current "top" of the Stack. This instruction first loads into the low order portion qq, the byte at the memory location corresponding...
  • Page 53 If the Stack Pointer contains 1000H, memory location 1000H contains 55H, location 1001H contains 33H, instruction will result in register pair HL containing 3355H, Stack Pointer containing 1002H.
  • Page 54 > > > : > 11 : 1 : > > :0 :0 :0 :0 11 :1 top two bytes of the external memory LIFO (last-in, first-out) Stack popped into Index Register Stack Pointer (SP) register pair holds l6-bit address of the current "top"...
  • Page 55 1«««0:11 1«««0:11 bytes external memory LIFO (last-in, first-out) Stack are popped into Index Register Stack Pointer (SP) register pair holds 16-bit address of the current "top" Stack. This instruction first loads into the low order portion the byte at the memory location corresponding contents...
  • Page 57 two-byte contents of register pairs DE and HL exchanged. If the content of register pair DE is the number 2822H, the content of the register pair HL is number 499AH, after the instruction the content of register pair DE will be 499AH content of register...
  • Page 58 two-byte contents of the register pairs AF and AF' are exchanged. (Note: register pair consists registers A' and F'.) If the content of register pair AF is number 9900H, the content of register pair is number 5944H, after the instruction the contents of AF will be 5944H,...
  • Page 59 Each two-byte value in register pairs BC, DE, and HL exchanged with the two-byte value BC', DE', HL', respectively. If the contents of register pairs BC, DE, and HL are numbers 445AH, 3DA2H, 88590, respectively, contents of register pairs BC', DE', and HL' 0988H,...
  • Page 60 (SPJ, The low order byte contained in register pair exchanged with the contents of the memory address specified the contents of register pair (Stack Pointer), the high order byte of HL is exchanged with next highest memory address (SP+l). If the HL register pair contains 7012ll, the...
  • Page 61 CSPJ, > > > > < < > > < < < The low order byte in Index Register IX is exchanged with the contents of the memory address specified by the contents of register pair SP (Stack Pointer), high order byte of IX is exchanged...
  • Page 62 (SPJ, > > > > > > > > > > :a :a :a The low order byte in Index Register IY is exchanged with the contents of the memory address specified by the contents of register pair SP (Stack Pointer), high order...
  • Page 63 > > > : < < < >: 0: 0: 0: 0: 0 A byte of data is transferred from memory location addressed by the contents of the HL register pair to the memory location addressed the contents of the DE register pair.
  • Page 64 If the HL register pair contains llllH, memory location BSH, llllH contains contains the byte DE register pair contains 2222H, the memory location 2222H contains 66ll, byte the BC register pair contains 7H, then instruc tion will result in the following contents in register pairs...
  • Page 65 LDIR >: > 0> >: 0> >: 0> 0: 0: 0: This two byte instruction transfers a byte data fro~ memory location addressed. by the contents the HL register pair to the memory location addressed by the DE register pair. Then both these...
  • Page 66 af.fected affected Re se t P/V: Re se II : Reset affected If the HL register pair contains llllll, the DE register pair contains 2222H, BC register pair contains 0003H, and memory locations have these contents: (llllH) (2222ll) (1112H) 36ll (2223H) (l113H) (2224H)
  • Page 67 > >: >: > >: : 0: This two byte instruction transfers a byte data from memory location eidressed by the contents of the register pair to the memory location addressed by the contents of the DE register pair. Then both of these register...
  • Page 68 If the HL register pair contains IIIIH, memory location IIIIH contains the byte 88H, the DE register pair contains 2222H, memory location 2222H contains byte 66H, the BC register pair contains 7H, then in s tr uc t io n will result in the...
  • Page 69 LDDR < < < > > > > > > ~ ;a :a :a ;a This two byte instruction transfers byte data fro~ memory location addressed contents the HL register pair to the me~ory location addressed by the contents of the DE register pair.
  • Page 70 If the HL register pair contains 1114H, the DE register pair contains 2225H, BC register pair contains 0003H, and memory locations have these contents: (2225Il) C5Il (l114H) (l113H) (2224H) (l112H) (2223H) the contents of register pairs and memory locations will llllH 2222H OOOOH...
  • Page 71 1«<0»»1 > < < a: a: a: contents of the memory location addressed register pair is compared with contents of the Accumulator. In case of a true compare, a condition is set. Then HL is incremented the Byte Counter (register pair is decremented.
  • Page 72 the Byte Counter will contain OOOOH, the HL register pair will contain 1112H, Z flag in the F register will be set, the P/V flag in the F register will reset. There will be no effect on the contents of the Accumulator or address llllH.
  • Page 73 CPIR > > : > > : > < < > < a: a: The contents of the memory location addressed the HL register pair is compared with contents of the Accumulator. In case of a true compare, a condition set.
  • Page 74 Set if result is negative; reset otherwise L) ; reset otherwise ifthere is a bar row otherwise. BC-1,lO; reset otherwise affected the ilL register pair contains 1111il, the Accumulator contains F3il, the Byte Counter contains On07H, memory locations have these contents: (111111) 52il...
  • Page 75 > < > > < < > > > < :a :a contents of the memory location addressed by the ilL register pair is compared with the contents Accumulator. In case of a true compare, a condition is set. The ilL and the Byte Counter (register...
  • Page 76 Byte Counter will contain OOOOH, HL register pair will contain IIIOH, Z flag in the F register will be set, the P/V flag in the F register will reset. There will be no effect the contents of the Accumulator or address IIIIH.
  • Page 77 CPDR > < < < < < < > > > > :a :a The contents of the oemory location addressed by the HL register pair is compared with the contents Accuoulator. case of a true compare, a condition is set. The ilL and BC (Byte Counter)
  • Page 78 Set if result is negative; reset otherwise Set if (IlL); reset otherwise ifthere a borrow and reset otherwise. Set if BC-l;<O; reset otherwise Se t affected If the HL register pair contains 1118H, the Accumulator contains F3H, Byte Counter contains 0007H, memory locations...
  • Page 81 The contents of register r are added to the contents the Accumulator, the result is stored in the Accumulator. symbol r identifies registers A,B,C,D,E,H or L assembled as follows in the object code: Register Set if result is negative; reset otherwise Set if result is zero;...
  • Page 82 If the contents of the Accumulator are 44H, contents of register Care IlH, after the execution...
  • Page 83 > > < < :a :a I" : integer n is added to the contents of the Accumulator and the results stored in the Accumulator. Set if result is negative; reset otherwise Set if result is zero; reset otherwise Set if carry from Bit 3;...
  • Page 84 CHLJ The byte at the memory address specified by the contents of the HL register pair is added to the contents of the Accumulator and the result is stored in the Accumulator. CYCLES: STATES: 7(4,3) 4 1lHZ E.T.: Condi tion Bits Affected: Set if result...
  • Page 85 CIX+dJ > : > > > > < < : a: a: 11 : :< : : I., : "1 The contents of the Index Register (register pair added to a displacement d to point to an address memory. The contents of this address is then...
  • Page 86 10050 is 220, after the execution ADD A,(IX+SH) the contents of the Accumulator will be 33H.
  • Page 87 CIY+dJ < < < < < < < > > :a :a 0 : 0 I., : >: : : •. The contents of the Index Register (register pair IY) is added to a displacement d to point to an address memory.
  • Page 89 2.4.6 + Cy Operation: <,- Format: Opcode Operands A, s s operand is any of r,n,(HL),(IX+d) or (IY+d) defined for the analogous instruction. These various possible opcode-operand combinations assembled as follows in the object code: ~r*:--I 11 : : 0 : 1 <...
  • Page 90 DOlO s operand, along with the Carry Flag ("C" in the register) is added to the contents of the Accumulator, the result is stored in the Accumulator. INSTRUCTION CYCLES T STATES 4 HHZ E.T. ADC A,r 1.00 7(4,3) A, (HL) 7(4,3) A, (IX+d) 19(4,4,3,5,3)
  • Page 91 s operand of r,n,(HL),(IX+d) (IY+d) defined for the analogous instruction. These various possible opcode-operand combinations assembled as follows object code: > < :a ~ < < < < < 1< : < < << a: a: 11 : 1 : 1 : 1 : : 1 : <...
  • Page 92 Register s operand is subtracted from the contents Accumulator, the result is stored in the Accumulator. INSTRUCTION CYCLES STATES E.T. SUB r 7(4,3) (ilL) 7(4,3) (IX+d) 19(4,4,3,5,3) 4.75 (IY+d) 19(4,4,3,5,3) 4.75 Condition Bits Affected: Set if result negative; reset otherwise Set if result zero;...
  • Page 93 2.4.8 <- Operation: Format: Opcode Operands s operand is any of r,n,(HL) ,(IX+d) (IY+d) defined for the analogous instructions. These various possible opcode-operand combinations assembled as follows in the object code: 11:a:a»~r~1 :<0:««0 1< : >1 »»>1 > > > > 1>...
  • Page 94 DOlO s operand, along \'liththe Carry Flag ("C" register) is subtracted from the contents of the Accumulator, the result is stored in the Accumulator. INSTRUCTION CYCLES STATES E.T. SBC A, r SBC A,n 7(4,3) SBC A, (HL) 7(4,3) SBC A, (IX+d) 19(4,4,3,5,3) 4.75 SBC A,(IY+d)
  • Page 95 s operand is any of r,n, (HL), (IX+d) or (IY+d), defined for the analogous instructions. These various possible opcode-operand combinations assembled as follows in the object code: 1:a>:a:a~r~ > : > > > :a :a .• : In: : : •• <...
  • Page 96 DOlO A logical operation, by bit, is performed between the byte specified by the s operand and the byte contained in the Accumulator; the result is stored the Accumulator. CYCLES T STATES 4 11HZ E.T. INSTRUCTION AND n 7(4,3) (HL) 7(4,3) (IX+d) 19(4,4,3,5,3)
  • Page 97 s operand is any r,n,(HL),(IX+d) (IY+d), defined for the analogous instructions. These various possible opcode-operand conbinations assembled follows object code: > > :o~r~1 <0 > > > : > > : ., : in: : : •. < < < <...
  • Page 98 DOlO A logical OR operation, bit by bit, is performed between byte specified by the s operand the byte contained in the Accumulator; result is stored the Accumulator. INSTRUCTION CYCLES T STATES E.T. OR r OR n 7(4,3) (HL) 7(4,3) (IX+d) 19(4,4,3,5,3) 4.75...
  • Page 99 s operand of r,n, (HL),(IX+d) or (IY+d), defined for the analogous instructions. These various possible opcode-operand combinations assembled follows the object code: < < l~r~1 < < < < < < 1< : >1 < < < < < > > > >...
  • Page 100 DOlO A logical exclusive-OR operation, bit by bit, performed between the byte specified by the s operand the byte contained in the Accumulator; the result stored in the Accumulator. INSTRUCTION M CYCLES T STATES E.T. XOR r XOR n 7(4,3) (HL) 7(4,3) (IX+d)
  • Page 101 s operand is any of r,n,(HL),(IX+d) or (IY+d), defined for the analogous instructions. These various possible opcode-operand combinations assembled as follows in the object code: <o:«<~r~1 < < < < < < < .; : In: > > > > > :a I >...
  • Page 102 Register The contents of the s operand are co~pared with contents of the Accumulator. If there is a true co~pare, a flag is set. IHSTRUCTION CYCLES T STATES 4 MHZ E.T. CP r CP n 7(4,3) (HL) 7(4,3) (IX+d) 19(4,4,3,5,3) 4.75 (IY+d) 19(4,4,3,5,3)
  • Page 103 Register r is incremented. r identifies any of the registers A,B, C,D,E,H or L, assembled as follows obj ect code. Register CYCLES: T STATES: E.T.: Condition Bits Affected: Set if result is negative; reset otherwise if result is zero; reset otherwise Set if carry from...
  • Page 104 If the contents of register Dare 280, after execution...
  • Page 105 (HLJ The byte contained in the address specified by the contents of the HL register pair is incremented. Set if result is negative; reset otherwise Set if result is zero; reset otherwise Set if carry from 3; reset otherwise Set if (HL) was 7FH before operation;...
  • Page 106 CIX+dJ < > > > : > 1 : 0 < < < a: a: \., : :< : : •. The contents of the Index Register IX (register pair added to a two's complement displacement integer to point to an address in memory.
  • Page 107 the contents of the Index Register.pair IX are 2020H, the Demory location 2030H contains byte 348, after the execution...
  • Page 108 CIY+dJ > : > > > > > < < < a: a: :< : : I., : "1 The contents of the Index Register (register pair are added to a two's cOQplement displacement integer to point to an address in memory.
  • Page 109 If the contents of the Index Register pair IY are 2020H, the memory location 2030H contain byte 34H, after the execution...
  • Page 110 m operand of r, (HL) ,(IX+d) or (IY+d), defined the analogous INC instructions. These various possible opcode-operand combinations assembled as follows in the object code: :a~r~< 0 :1 :1 :0 :1 :0 :1 1>:0»»> 0:0»»» .; : >: : : •. »»>:0>...
  • Page 111 Register INSTRUCTION CYCLES T STATES 4 MHZ E.T. DEC r (HL) 11(4,4,3) (IX+d) 23(4,4,3,5,4,3)" 5.75 (IY+d) 23(4,4,3,5,4,3) 5.75 Condition Bits Affected: Set if result is negative; reset otherwise Set if result zero; reset otherwise ifthere is a borrow othe rwise. Set if m was 80H before operation;...
  • Page 113 This instruction conditionally adjusts the Accumulator for BCD addition subtraction operations. addition (ADD, ADC, INC) or subtraction (SUB, SBC,DEC,NEG), following table indicates operation performed: VALUE VALUE NUHBER ADDED BEFORE UPPER BEFORE LOWER AFTER OPERATION DIGIT DIGIT BYTE (bit (b it 7-4) 3-0)
  • Page 114 if most significant of Ace. is 1 after operation; reset otherwise if Ace. is zero after operation; reset otherwise See instruction P/V: Set if Ace. is even parity after operation; reset otherwise Not affected See instruction an addition operation is performed between 15 (BCD) and 27 (BCD),...
  • Page 115 Contents Accumulator (register A) are inverted (l's complement). Condition Bits Affected: No t affected affected Se t P/V: Not affected No t affected Example: If the contents of the Accumulator 1011 0100, after execution...
  • Page 116 > > > < < < > > :a :a :a :a :a Contents of the Accumulator are negated (two complement). This is the same as subtracting contents of the Accumulator from zero. Note that left unchanged. Set if result is negative;...
  • Page 117 Example: the contents of the Accumulator...
  • Page 118 affected affected Previous carry will be copied P/V: affected Reset Set if CY was 0 before operation; reset otherwise...
  • Page 119 affected affected Rese P/V: affected Re se t...
  • Page 120 Operation: Format: Opcode Description: CPU perforos no operation during this machine cycle. M CYCLES: T STATES: Condition Bits Affected:...
  • Page 121 HALT The HALT instruction suspends CPU operation until subsequent interrupt or reset is received. While halt state, the processor will execute NOP's maintain memory refresh logic.
  • Page 122 DI disables the maskable interrupt by resetting interrupt enable flip-flops(IFFl IFF2). Note that this instruction disables the maskable interrupt during its execution. the maskable interrupt is disabled until it is subsequently re-enabled by an EI instruction. will not respond to an Interrupt Request (INT) signal.
  • Page 123 EI enables the maskable interrupt setting interrupt enable flip-flops(IFFl IFF2). Note that this instruction disables the maskable interrupt during its execution. the maskable interrupt is enabled. CPU will respond to an Interrupt Request (INT) signal.
  • Page 124 < < < > > > :0 :0 :1 :1 1M 0 instruction sets interrupt mode this mode the interrupting device insert instruction on the data and allow the CPU to execute...
  • Page 125 > > > > : > < > : > > instruction sets interrupt mode this mode the processor will respond to an interrupt executing a restart location 0038H.
  • Page 126 > > > 11 : 1 : > > : > > > 1M 2 instruction sets interrupt mode This mode allows indirect call to any location in memory. With this mode the CPU forms a 16-bit memory address. upper eight bits the contents...
  • Page 129 The contents of register pair ss (any of register BC,DE,HL or SP) are added to the contents regi: pair ilL and the result is stored in ilL. Operand specified as follows in the assembled object code Register Pair affected affected Set if carry 11;...
  • Page 130 If register pair HL contains the integer 42428 IlllH, register pair DE contains after the execution...
  • Page 131 HL., 2.6.2 HL<-HL+ss+CY Operation: Format: Opcode Operands HL,ss > > > < < < ° 1«««<01 contents of register pair ss (any of register pairs BC,DE,HL or SP) are added with Carry Flag flag the F register) to the contents of register pair the result...
  • Page 132 If the register pair BC contains 2222H, register pair contains 5437H the Carry Flas is set, after execution...
  • Page 133 2.6.3 HL<-HL-ss-CY Operation: Format: Opcode Operands IlL,ss > > : > : a : a : 1 : s : s : contents of the register pair ss (any of register pairs BC,DE,IlL or SP) and the Carry Flag (C flag F register) are subtracted from...
  • Page 134 If the contents of the HL register pair are 9999H, contents of registeT pair DE are 11118, Carry Flag is set, after the execution...
  • Page 135 > > > : > 11 : 1 : 0 : 0 : p : p : 1 : 0 : 0 : 1 The contents of register pair pp (any of register pairs BC.DE.IX or SP) are added to the contents of the Index Register...
  • Page 136 If the contents Index Register IX are 333H contents of register pair 5555H, after execution...
  • Page 137 > > > > > : > : 0 : r : r : 1 :0 :0 : 1 contents of register pair (any of register pairs BC,DE,IY or SP) are added to the contents Index Register IY, and the result is stored in IY.
  • Page 138 If the contents of Index Register IY are 333H contents of register pair SSSH, after execution...
  • Page 139 contents of register pair (any of register pairs BC, DE,HL or SP) are increnented. Operand ss is specified as follows in the assembled object code. i\egister Pair CYCLES: T STATES: E. T. Condi tion Bits Affected: None If the register pair contains 1000H,...
  • Page 140 > > > > : > > > > :a :a :a If the Index Register IX contains the integer 3300H after the execution...
  • Page 141 > > : < < < 0: 1 > > > :a :a :a If the contents of the Index Register are 2977H, after the execution...
  • Page 142 contents of register pair (any of the register pairs BC,DE,HL or SP) are decremented. Operand specified as follows in the assembled object code. Pair CYCLES: T STATES: HIlZ E. Condition Bits Affected: None If register pair HL contains 1001Il, after execution...
  • Page 143 : 1 : 0 : 1 : 1 : 1 : 0 : 1 > : 0 : 0 : 1 : 0 : 1 : 0 If the contents of Index Register IX are 2006ll, after the execution...
  • Page 144 > < < < < < 1 : 0 > > > > If the contents of the Index Register IY are 7649H, after the execution...
  • Page 147 RLCA contents of the Accumulator (register A) are rotated left: the content of bit 0 is moved to bit 1; the previous content of bit 1 is moved to bit 2; this pattern continued throughout the register. content 7 is copied into the Carry Flag...
  • Page 148 Example: If the contents of the Accumulator...
  • Page 149 lEJBJ contents of the Accumulator (register A) are rotated left: the content of bit 0 is copied into previous content of bit 1 is copied into bit 2; this pattern is continued throughout the register. content of bit 7 is copied into the Carry Flag...
  • Page 150 If the contents of the Accumulator the Carry Flag the contents of the Accumulator the Carry Flag will...
  • Page 151 RRCA The contents of the Accumulator (register A) is rotated right: the content of bit 7 is copied into bit 6; the previous content of bit 6 is copied into bit 5; this pattern is continued throughout the register. content of bit 0 is copied into...
  • Page 152 the contents of the Accumulator the Carry Flag will...
  • Page 153 The contents of the Accumulator (register A) are rotated right: the content of bit 7 is copied into bit 6; the previous content of bit 6 is copied into bit 5; this pattern is continued throughout the register. content of bit 0 is copied into Carry...
  • Page 154 If the contents of the Accumulator the Carry Flag the contents of the Accumulator and the Carry Flag will...
  • Page 155 WE]J < < > > > :o~r+-I 10:0:0:0 eight-bit contents of register r are rotated left: the content of bit 0 is copied into bit 1; the previous content of bit 1 is copied into 2; this pattern continued throughout the register.
  • Page 156 Set if result is negative; reset othervlise Set if result is zero; reset otherwise Re se P/V: Set if parity even; reset otherwise Re se t Data from 7 of source register...
  • Page 157 CHLJ crLB (HL) < < > > > > > : 0 : 0 : 0 contents of the ~e~ory address specified by the contents of register pair HL are rotated left: content of bit 0 is copied into bit 1;...
  • Page 158 If the contents of the ilL register pair 2828H, the contents of memory location 2828H the contents of memory location 2828il and Carry Flag will...
  • Page 159 CIX+dJ 2.7.7 WE}J Operation: (IX+d) Format: Opcode Operands (IX+d) > > > : 11 : > : > > 11 : 1 : I" : : : •. > : 0 : 0 : 0 : 0 : 0 1 : 0 contents of the memory...
  • Page 160 If the contents of the Index Register IX are 1000H, the contents of memory location 1022" are the contents of menory location 1002H and the Carry Flag v,ill be...
  • Page 161 CIY+dJ 2.7.8 L¥E]J Operation: (IY+d) Format: Operands Opcode ----- (IY+d) < 11 : 1 : 1 : 1 : 1 : > > : 1 : < : : I' ; : : "I > > : contents of the memory address specified...
  • Page 162 lOOOH, If the contents of the Index Register IY are the contents of memory location l002H the contents of memory location l002H the Carry Flag ,,'illbe...
  • Page 163 l§]~7-oIJ The m operand is any of r,(HL), (IX+d) or (IY+d), defined for the analogous instructions. These various possible opcode-operand combinations specified as follows in the assembled object code: > > 1 : 1 : 0 : 0 : 1 : 0 <...
  • Page 164 > > > > > > < < > > > :< : : 1< : > > > *r identifies registers B,C,D,E,H,L or A specified follows in the assembled object code above: DOlO The contents of the m operand are rotated left: content...
  • Page 165 Set if result is negative; reset otherwise Set if result is zero; reset otherwise ·Rese t P/V: Set if parity even; reset otherwise Re se Data from 7 of source register...
  • Page 166 The m operand of r, (HL), (IX+d) or (IY+d), defined for the analogous instructions. These various possible opcode-operand combinations specified as follows in the assembled object code: >: > : > > :-+r~ 0: 0: 0: 0: 1 > : >...
  • Page 167 > : > < < < < > : > : > > :< 1< : >1 > > > : 0 : 0 : 0 : identifies registers B,C,D,E,H,L or A specified follows the assembled object code above: contents of operand m are rotated right:...
  • Page 168 Set if result is negative; reset otherwise if result is zero; reset otherwise Re se t P/V: Set if parity even; reset otherwise Re se t Data from 0 of source register...
  • Page 169 2.7.11 LI7-0~§J Operation: Format: Operand Opcode The m operand any of r, (HL), (IX+d), (IY+d), defined for the analogous instructions. These various possible opcode-operand combinations specified as follows in the assembled object code: 1 : 1 : : 1 : 1 CB <...
  • Page 170 1°:0:°»>:<0 < 0»»: 1< :< : : •. 1< : ° : ° : 1: 1: 1 : 1 : 0 *r identifies registers B,C,D,E,H,L or A specified follows in the assembled object code above: The contents of operand m are rotated right: contents of bit...
  • Page 171 Set if result is negative; reset otherwise Set if result is zero; reset otherwise 'Re se t P/V: Set if parity is even; reset otherwise Re se t Data from 0 of source register If the contents of the HL register pair are 4343H, the contents...
  • Page 172 ~7-01 __0 operand of r, (HL), (IX+d) (IY+d), defined for the analogous instructions. These various possible opcode-operand conbinations specified as follows assembled object code: > 0> > >~r~ 1: 1: 1: 1 1 : 1 : I»»»: 0 :0 1 : 1 d: : : :.
  • Page 173 > > > > > < > >> > :< : : 1< > >> identifies registers B,C,D,E,H,L or A specified follows in the assembled object code field above: DOlO arithmetic shift left is performed on the contents operand m: bit 0 is reset, previous content...
  • Page 174 Affected: Condition Bits Se t if result is negative; reset otherwise Se t if result is zero; reset otherwise Re se t p/V: Se t if parity is even; otherwise reset Reset Data· from Example: If the contents of register...
  • Page 175 o~rc0 t.:J Operation: The m operand of r, (HL), (IX+d) (IY+d) defined the analogous instructions. These various possible opcode-operand combinations specified as follows in the assembled object code: > > > > :a :a < l~r~1 a: a: 1: 1: : 0: 1: 0: 1: 1 0: 0: 1: 0: 1: 1:...
  • Page 176 11: 1: 1: 1: 1:0: 11 11: 1:0:0: 1:0: :< 1< : 1:0: 1: 1:01 Ia:a: *r means registers B,C,D,E,H,L A specified as follows -in the assembled object code field above: Register An arithmetic shift right ·is performed on the contents of operand m: the content...
  • Page 177 Set if result is negative; reset otherwise Set if result is zero; reset otherwise Re se t p/v: Set if parity is even; reset otherwise Re se t Data fro~ 0 of source register lOOOH, contents of the Index Register the contents of me~ory location...
  • Page 178 The operand m is any of r, (HL), (IX+d) or (IY+d), defined for the analogous instructions. These various possible opcode-operand combinations specified as ~ollows in the assembled object code: > : > : > > 0: 0 1: 1: 1-~r~1 10: 0: <...
  • Page 179 > < < < < < < < < < 1: 0: 0: < : : :. I' ; : : < < < < < a; a: identifies registers B,C,D,E,H,L or A specified follows assembled object code fields above: 000.
  • Page 180 Set if result is negative; reset otherwise Set if result is zero; reset otherwise Re se t P/V: Set if parity is even; reset otherwise Re se t Data from 0 of source register...
  • Page 181 > > > < < < >: > > > 0: 1 contents of the low order four bits (bits 3,2,1 the Demory location (IlL) are copied into high order four bits (7,6,5 4) of that saDe memory location; previous contents of those high...
  • Page 182 If the contents of the HL register pair are SOOOH, the contents of the Accumu~ator and memory location SOOOH contents of the Accumulator and memory location SOOOH will...
  • Page 183 >> < < < 0> > >: > > > < contents of the low order four bits (bits 3,2,1 0) of memory location (ilL) copied into the low order four bits Accumulator (register the previous contents of the low order four bits...
  • Page 184 If the contents of the HL register pair SOOOH, the contents of the Accu~ulator and memory location SOOOH the contents of the Accumulator and menory location 5000H will...
  • Page 187 > > > > :a :a ~b~:-:r~1 After the execution of this instruction, Z flag F register will contain the cOQplenent of the indicated bit within the indicated register. Operands and r are specified as follows in the assenbled object code: Tested R~g_~~~e~...
  • Page 188 If bit in register B contains 0, after execution Z flag in the F register will contain 1, and in register B will remain O. Bit 0 in register B is least significant bit.
  • Page 189 CHLJ > > > : > 0 : 0 > 1>:a After the execution of this instruction, Z flag the F register will contain the co~plement of the indicated bit within the contents of the ilL register pair. Operand b is specified as follows in the assembled...
  • Page 190 HL register pair contains 4444H, and bit in the memory location 444H contains 1, after execution the Z flag in the F register will contain 0, and ° in memory location 44448 will still contain 1. (Bit memory location 4444H is the least significant bit.)
  • Page 191 (IX+dJ > : > : > > > : > : > : 0 : 0 :< : : I" : > ;-+b~ 1: After the execution of this instruction, Z flag the F register will contain the complement of the indicated bit within the contents...
  • Page 192 Unknown Set if specified 0; reset otherwise P/V: Unknown Re se t affected If the contents Index Register 2000H, 6 in memory location 2004H contains 1, after execution Z flag F register will contain 0, and bit memory location 2004H will still contain...
  • Page 193 b, (IY+dJ (IY+d)b Operation: > > > > : > 11 : 1 » :< : : ,. I .• ~b+-; 1 : 1 : After the execution of this instruction, flag the F register will contain the complement of the indicated bit within contents...
  • Page 194 Unknown Set if specified Bit is 0; reset otherwise P/V: Unknown affected If the contents of Index Register are 2000H, in memory location 2004H contains 1, after execution flag in the F register sill contain 0, and memory location 2004H will still contain...
  • Page 195 > > > : 11 : 1 : a : a 11:1~b~:~r+-1 Bit b (any bit, 7 through 0) in register r (any of registers B,C,D,E,H,L or A) is set. Operands band specified as follows in the assembled object code: Register CYCLES: T STATES:...
  • Page 196 CHLJ > : > > > a : a 11>~b~«~ Bit b (any bit, 7 through 0) in the memory location addressed by the contents of register pair HL is set. Operand b is specified as follows in the assembled object code: Tested...
  • Page 197 CIX+dJ > : > > > > > > : > > :< : : I" : ~b~«O > Bit b (any bit, 7 through 0) in the memory location addressed by the sum of the contents of the IX register pair (Index Register...
  • Page 198 the contents of Index Register 2000H, after execution 0 in memory location 2003H will (Bit memory location 2003H is the least significant bit.)
  • Page 199 CIY+dJ > > > > > > > < < a: a: ::<:: "I .• > 11:1~b+-71 Bit b (any bit, 7 through 0) in the memory location addressed by the sum of the contents of the register pair (Index Register IY) and the two's...
  • Page 200 If the contents of Index Register IY are 2000H, after the execution 0 in memory location 2003H will (Bit 0 in memory location 2003H is the least significant bit.)
  • Page 201 Operand b is any bit (7 through 0) of the contents the m operand,(any of r, (IX+d) or (IY+d))as (1iL), defined for the analogous SET instructions. These various possible opcode-operand combinations assembled as follows in the object code: 1 :°:°>:0» :~b7-:~r+- 1 >:°:0>:0>...
  • Page 202 Reset Register RES r 8(4,4) 15(4,4,4,3) 3.75 (HL) (IX+d) 23(4,4,3,5,4,3) 5.75 (IY+d) 23(4,4,3,5,4,3) 5.75 6 in register D will be reset. (Bit in register is the least significant bit.)
  • Page 205 > > < < :a :a >: : : •. I" : 1< : : : •• Note: The first operand in this assembled object code is the low order byte of a 2-byte address. Operand nn is loaded into register pair PC (Program...
  • Page 206 11 : 1 ~CC~ I., : In: : : •. :< : : 1< : >1 Note: first n operand in this assembled object code is the order byte of a 2-byte memory address. If condition cc is true, instruction loads operand nn into...
  • Page 207 If the Carry Flag (C flag in the F register) is set and the contents of address 1520 are 03H, after execution the Program Counter will contain 1520ll, and on the next machine cycle the CPU will fetch from address 1520H byte 03H.
  • Page 208 < < a: a: a: a: a: 1< : ~-2: : : >1 This instruction provides for unconditional branching other segments of a program. The value of the displacement e is added to the Program Counter (PC) the next instruction is fetched from the location...
  • Page 209 If C Operation: continue If C 1, PC PC + e < < a : a : I" : :e-2: : : •. This instruction provides for conditional branching other segments of a program depending on the results a test on the Carry Flag.
  • Page 210 resulting object code final PC value is shown below: 47C LABEL: 480 JR C, L.ABEL (2'5 complement-6)
  • Page 211 If C Operation: continue If C 0, PC > > : a: a: I'; : :e-2: : : •. This instruction provides for conditional branching other segments of a program depending on the results test on the Carry Flag. If the flag is equal '0',...
  • Page 212 The resulting object code and PC after the jump shown below: 480 LABEL:JR NC, LABEL PC after jump +---...
  • Page 213 IfZ=O. Operation: continue If Z > : > : I" : :e-2: : : •. This instruction provides for conditional branching other segments of a program depending the results test the Zero Flag. flag is equal to a '1', the value of the displacement is added...
  • Page 214 resulting object code final PC value is shown below: 300 JR Z, LPBEL LABEL:...
  • Page 215 If Z Operation: continue If Z 0, PC > : :e-2: : : •. This instruction provides for conditional branching other segments of a program depending results test on the Zero Flag. If the flag equal to a '0', the value of the displacement e is added...
  • Page 216 resulting object code and final PC value shown below: LABEL: JR NZ, LABEL...
  • Page 217 (HLJ The Program Counter (register pair is loaded with the contents of the HL register pair. The next instruction is fetched from the location designated the new contents of the PC. If the contents of the Program Counter 1000ll contents of the llL register pair 4800H,...
  • Page 218 (IX) < < >: > < < 11 : Program Counter (register pair is loaded with contents Register Pair (Index Register IX). The next instruction is fetched from location designated the new contents the PC. lOOOH, If the contents of the Program Counter the contents...
  • Page 219 (IYJ < > < < < < < > < < < > :a :a Program Counter (register pair is loaded with contents of the IY register pair (Index Register IY). next instruction fetched from location designated the new contents If the contents of the Program...
  • Page 220 D~NZ < a: a: a: a: a: a: 1< : ~-2: : : >1 This instruction is similar to the conditional jump instructions except that a register value is used determine branching. B register is decremented zero value remains, the value of the displacement e is added...
  • Page 221 (OUTBUF). moves bytes until finds a CR, until it has moved 80 bytes, whichever occurs first. B,80 ;Se t up counter HL,Inbuf ;Set up pointers DE,Outbuf )OP: A, (HL) ;Get next byte from buffer ;input (DE) ,A ;Store in output buffer ;Is it a CR? Z,DONE...
  • Page 223 CALL > < < < < a: a: I .• : >1 I .• Note: first of the two n operands in the assembled object code above is the least significant byte of a two-byte memory address. After pushing the current contents of the Program...
  • Page 224 If the contents of the Program Counter IA47H, contents of the Stack Pointer 3002H, and memory locations have the contents: IA47H IA48H IA49H then if an instruction fetch sequence begins, three-byte instruction CD352lH will be fetched to the CPU for execution.
  • Page 225 CALL IF cc TRUE: (SP-I) PC H (SP-2) - PC < ~:cc~< :< : : >1 I .• : I" : In: : : >1 Note: The first of the two n operands in the assembled object code above is the least significant byte of the...
  • Page 226 the push is executed. Condition cc is programmed as one of eight status which corresponds to condition bits the Flag Register (register These eight status defined in the table below, which also specifies corresponding cc bit fields in the assembled object code: Relevan t...
  • Page 227 After the execution of this instruction, the contents memory address 300lH will lAH, the contents address 3000H will be 4AH, contents of the Stack Pointer will be 3000H, the contents of the Program Counter will be 2l35H, pointing to the address of the first opcode...
  • Page 228 Control is returned to the original progran flow popping the previous contents of the Program Counter (PC) off the top of the external memory stack, where they were pushed by the CALL instruction. This accomplished by first loading the ~ow-order byte PC with the contents...
  • Page 229 If condition cc is true, control is returned to the original program flow by popping the previous contents of the Program Counter (PC) the top of the external memory stack, where they were pushed by the CALL instruction. This is accomplished by first loading low-order...
  • Page 230 If the flag in the F register is set, contents 3535H, the Program Counter contents Stack ZOOOH, ZOOOH Pointer contents of mecory location B5H, ZOOIH the contents memory location IBH, then after the execution ZOOZH contents of the Stack Pointer will IBB5H, contents...
  • Page 231 RETI > > > > > > > > : > > This instruction is used at the end of an interrupt service routine Restore the contents of the Program Counter (PC) (analogous to the RET instruction) 2. To signal an I/O device that the interrupt...
  • Page 232 B generates an interrupt is acknowledged. (The interrupt enable out, lEO, of B goes low, blocking lower priority devices from interrupting while B is being serviced). Then A generates an i~terrupt, suspending service of B. (The lEO of A goes 'low' indicating that...
  • Page 233 RETN 1«<0»»1 > > > :a :a :a Used at the end of a service routine for a non maskable interrupt, this instruction executes an unconditional return which functions identical to the RET instruction. That is, the previously stored contents of the Program Counter (PC)
  • Page 234 order-byte first, 006.6H will be loaded onto Program Counter. That address begins an interrupt service routine uhich ends with RETN instruction. Upon the execution of RETN, former Program Counter contents are popped the external memory stack, low-order first, resulting in a Stack Pointer contents again...
  • Page 235 The current Program Counter (PC) contents are pushed onto the external memory stack, and the page zero memory location given by operand p ~s loaded into the PC. Program execution then begins with the opcode in the address pointed to by PC. Th~ push is performed first...
  • Page 236 If the contents of the Program Counter l5B3R, after the execution the PC will contain DDl8R, as the address of the next opcode to be fetched.
  • Page 239 IN A, < < > > > > I : •• operand n is placed on the bottom half (AD through of the address to select I/O device at one 256 possible ports, The contents of the Accumulator also appear on the top half (A8 through A15)
  • Page 240 > > > > > 0 : 0 : 0 contents of register C are placed on the bottom half (AD through A7) of the address to select device at one of 256 possible ports. contents Register B are placed on the top half (A8 through...
  • Page 241 Set if input data is negative; reset otherwise Set if input data is zero; reset otherwise Reset P/V: Set if parity is even; reset otherwise Re se t affected If the contents of register Care 07R, contents register B are lOR, and the byte 7BR is available...
  • Page 242 > > > > > > : > a :a :0 11 : The contents of register C are p~aced on the bottom half (AO through A7) of the address to select device at one of 256 possible ports. Register used as a byte counter,...
  • Page 243 lOOOH 7BH, memory location will contain register lOOlH, pair will contain register will contain OFH.
  • Page 244 INIR > > > : > > : < > > > :a :a The contents of register C are placed on the bottom half (AD through of the address to select device at one of 256 possible ports. Register B is used as a...
  • Page 245 Unknown Unknown plY: Unknown llot affected If the contents of register Care 07H, the contents register Bare 03H, contents of the HL register pair lOOOH, the following sequence of bytes available at the peripheral device mapped to I/O port address 07H: the HL register pair...
  • Page 246 < < < > > > 1«««<01 The contents of register C are placed on the bottom half (AO through of the address to select device at one of 256 possible ports. Register used as a byte counter, its contents are placed top half (A8 through...
  • Page 247 peripheral device mapped to I/O port address 07H, then after execution memory location lOOOH will contain 7BH, register pair will contain OFFFH, register B will contain OFH.
  • Page 248 INDR < < < < < > < < < < < The contents of register C are placed on the bottom half through A7) of the address to select device at one of 256 possible ports. Register B is used as a byte counter,...
  • Page 249 Unknown Unknown P/V: Unknown affected If the contents of register Care 07ll, the contents register Bare 03H, the contents of the HL register pair 1000H, the following sequence of bytes available at the peripheral device ~apped to I/O port address 07H: SIll the HL register...
  • Page 250 (n], < < > > > ;0 :a I I •. The operand n is placed on the bottoQ half (AD through of the address select" I/O device of 256 possible ports. The contents of the AccuQulator (register A) also appear on the top half (AB through...
  • Page 251 (CJ, > > > < < < > > The contents of register C are placed on the bottom half (AO through A7) of the address to select device at one of 256 possible ports. The contents Register B are placed on the top half (A8 through...
  • Page 252 If the contents of register Care 01ll contents of register Dare SAH, after the execution the byte SAH will have been written to the peripheral device mapped to I/O ~ort address 01H.
  • Page 253 OUTI > > > < < < > >> < :a :a :a contents of the HL register pair are placed on the address to select a location in memory. The byte contained in this memory location is temporarily stored in the CPU.
  • Page 254 register B will contain OFH, HL register pair will contain 1001H, the byte 59H will have been written to the peripheral device mapped to I/O port address 07H.
  • Page 255 OTIR < < < > > > > > > > < :a :a The contents of the HL register pair are placed address to select a location in"Demory. byte contained in this memory location is temporarily stored in the CPU. Then, after the byte...
  • Page 256 Unknown Unknown P/V: Unknown affected If the contents of register Care 07H, the contents register Bare 03H, contents of the HL register pair 1000H, and memory locations have the following contents: l-OOOH 100lH 1002H HL register pair will contain 1003H, register B will contain...
  • Page 257 OUTO > > : 1 : 1: < < 11 : 1: 1 contents of the HL register pair are placed on the address to select a location in memory. The byte contained in this memory location is temporarily stored in the CPU.
  • Page 258 register Bare 10H, the contents of the HL register pair 1000H, the contents memory location 1000H 59H, after the execution register will contain OFH, HL register pair will contain OFFFH, the byte 59H will have been written to the peripheral device mapped to I/O port...
  • Page 259 OTDR >> > < < < >> < < < < The contents of the HL register pair are placed address to select a location in memory. byte contained in this memory location is temporarily stored the CPU. Then, after the byte counter (B) is...
  • Page 260 Unknown Se t Un known P/V: Un known affected If the contents of register Care 07H, the contents register Bare 03H, contents of the RL register pair lOOOH, and memory locations have following contents: OFFER OFFFH lOOOH HL register pair will contain OFFDR,...
  • Page 263 flag register (F and F') supplies information user regarding the status of the Z80 at any given time. The bit positions for each flag is shown below: CARRY FLAG ADD/SUBTRACT FLAG PARITY/OVERFLOW FLAG HALF-CARRY FLAG ZERO FLAG SIGN FLAG USED Each Z-80 Flag...
  • Page 264 instructions RRCA, RRC s, SRA sand SRL s the carry contains last value shifted out of bit register memory location. logical instructions the carry will reset. Carry Flag also (SCF) complemented (CCF) • This flag is used decimal adjust accumulator instruction (DAA) distinguish...
  • Page 265 minuend sign has changed from a positive negative, giving an incorrect difference, Overflow therefore set, Another method for predicting an overflow to observe the carry into and out of sign bit, there carry carry out, or if there is no carry a carry out, then...
  • Page 266 Zero Flag set or reset the result generated by the execution of certain instructions zero. For 8-bit arithmetic logical operations, flag will be set to a the resulting byte Accumulator zero. the byte is not zero, the Z flag reset to '0' compare (search)
  • Page 268 ALPHABETICAL ASSEMBLY MNEMONIC ADC HL, aa Add with Carry Reg. pair ss to HL ••••••• 6- 2 ADC A, a Add with carry operand a to Ace ••••••••• 4- 6 ADD A,n value n to Ace ••••••••••••••••••••• 2- 4- 2 ADD A,r Ad d Re g.
  • Page 269 Exchange the location (SP) I Y • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 2- 3- 6 Exchange the contents...
  • Page 270 PAGE SECTION NZ,e Jump relative zero PC+e (Z-O) •••••••••••••••••• 2- 9- Jump relative zero ( Z-l ) •.••••.•••••••..••.•.• PC+e LD A, (BC) Load with location Ace. (Be) •••••••••••• 2- 1-12 LD A, (DE) with Load Ace. location (DE) •••••••••••• 2- 1-13 LD A,I with Load...
  • Page 271 Load location (DE) with location (HL). increment DE.HL. decrement BC ••••••••••• Load location (DE) with location (HL). increment DE.HL. decrement BC and repeat until BC-a •••••••••••••••• 3- 8 Negate Ace. complement) •••••••••••• (2'5 5- 3 No operation •••••••••••••••••••••••••••• 5- 6 Logical 'OR' of operand and Ace.
  • Page 272 No license is granted by implication or other· wise under any patent or patent rights of SGS-ATES. This publication supersedes and substitutes all information previously supplied. SGS - ATES GROUP OF COMPANIES Italy - France - Germany - Singapore - Sweden - United Kingdom - U.S.A.
  • Page 273 Elettronici Via C_ Olivetti 20041 Agrate Brianza Italy Tel.: 039-650341-;-4/650441-;-5/650841-"-5 Telex: 36141-36131 BENELUX ITALY SGS-ATES Componenti Elettronici SGS-A TES Componenti Elettronici Benelux S.llies Office Sales Offices: -B-1180 Etruxelles 50127 Firenze Giovanni Del Pian Dei Carpini 96/1 Winston Churchill Avenue, Tel.: 02-3432439 Tel.:...