Alcatel MTC-20172 Reference Manual
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Alcatel MTC-20172 Reference Manual

Alcatel MTC-20172 Reference Manual

S interface circuit for isdn (sic)
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Features
• Single chip 4 wire S
-interface
0
for ISDN
• Basic access at 144 kbits/s,
with 2B+D
• Complying with CCITT I.430
• Applicable in all ISDN
So-interface Configurations :
- NT : Network Termination
- TE : Terminal Equipment
- LTS : Line Termination
Subscriber
- LTT : Line Termination Trunk
Analog
transmitter
SX
P
SX
N
Analog
receiver
SR
P
SR
N
activity
detector
Block Diagram
• Switching of Test-loops
• S-bus drivers with high-
impedance when not powered
• Balanced S-bus receivers
• Line-length up to 1.2 km in
point-to-point configuration
• Handles V*, IOM1™, IOM2 ™
and GCI digital interfaces
• Supports Multiframing
• Includes Maintenance channel
• Absorption of clock wander in
LTT mode
s_transmitter
FL detection
DPLL
s_receiver
7680 kHz
oscillator
XTI
XTLO
MTC-20172
'S' Interface Circuit
for ISDN (SIC)
Data Sheet &
Reference Manual
Rev. 1.1 February 1997
Application Specific Standard Products
• Operating power < 50 mW
• Single 5V supply
™ IOM is a trademark of Siemens
S, Q
S/Q control
B, D
buffer
B, D
status
controller
S, Q
asynchronous
power up/down
Stand-by power < 3 mW
M control
B, D
B, D
V*/GCI
MUX
C/I
CHP boundary
DIN
DOUT
DFR
DCLK

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Summary of Contents for Alcatel MTC-20172

  • Page 1 MTC-20172 'S' Interface Circuit for ISDN (SIC) Data Sheet & Reference Manual Rev. 1.1 February 1997 Application Specific Standard Products Features • Single chip 4 wire S -interface • Switching of Test-loops • Operating power < 50 mW for ISDN •...
  • Page 2 Page 56, Table 6.4.b, shows incorrect command codes for the Ald and AIL states. Data Sheet & Reference Manual Rev. 1.1 February 1997 The correct table is given here. 6.5.8 Command and Indications for NT Applications. Table 6.4.a : MTC-20172 SIC C/I : NT overview Downstr Upstr. Downstr Upstr.

  • Page 3: Table Of Contents

    ..................... . 4.4 Overview of the Use of MTC-20172 SIC in the ISDN System .
  • Page 4 ....................5.3.6 MTC-20172 SIC RX Signal Dynamics and Detection at TE/LT-T .
  • Page 5 ..................... . . 6.1.1 General Content of the GCI Bus for the MTC-20172 SIC .
  • Page 6 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 8. Loops, Test Modes, System Tests 8.1 Wafer Test of the Device ....................
  • Page 7 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 10. Quality and Reliability Specification 10.1 Quality ....................... .
  • Page 8 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 List of Abbreviations Automatic Gain Control ..... Alternating mark inversion .
  • Page 9 Fig. 3.2 28 pin PLCC square package and dimensions. Fig. 3.3 22 pin DIP, signal names. Fig. 3.4 28 pin PLCC, signal names. Fig. 4.1 MTC-20172 SIC Applications Fig. 4.2 Frame Structure GCI Fig. 5.1 S Frame Structure Fig. 5.2 S Coding with AMI Fig.
  • Page 10 Table 3.1 : Pin list and description, 22 and 28 pin package Table 3.2 : Input/Output types in function of the modes Table 4.1 .a : SBC 2080 compatible modes of operation with the MTC-20172 SIC Table 4.1 .b : SBCX 2081 compatible modes of operation with the MTC-20172 SIC Table 4.2 : Mode-selection pins in MTC-20172 SIC...

  • Page 11: General Description

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 1. General Description The MTC-20172 is an enhanced Termination’ (NT), providing link between the MTC-20172 SIC version of the MTC-2072 SIC. In transparent data transmission from the and, for example, the MTC-2071...

  • Page 12: Interface And Operation Overview

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 2. Interface and Operation Overview 2.1 The Digital Interface Only 1 channel is available. Remark: In LTS and LTT applications, This mode is applicable in TE mode. there is automatic recognition of...

  • Page 13: Table 2.1 : Possible Mode Combinations

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 2nd byte B2: 4th byte B1*: The interpretation of the received Second transparent data channel of D1, D2: Two transparent D-channel command codes and the transmitted 64 kBits/s. bits at 16 kBits/s.

  • Page 14: The So-Interface - Functional Overview

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 2.2 The So-Interface The frame structures are shown in with respect to the frame received from - Functional overview fig.2.5. the NT. Furthermore, an echo bit (E-bit) for the D-channel and an activation bit...

  • Page 15: Fig. 2.6 Point-To-Point Configuration

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 The SIC can be used in a point-to-point Controlled access to the shared data The terminal that transmitted the and in a point to multipoint channels is realized within the SIC by "zero"...

  • Page 16: The Mtc-20172 Sic Operation Summary

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 2.3 The MTC-20172 A second digital PLL generates the B and D data are stored in the buffer SIC Operation transmit bit clock (192 kHz), which is and multiplexed together with M, C/I,...

  • Page 17: Test Modes Summary

    Activation from the S-bus is possible, clock of 512 kHz is less than 50 mW and is indicated by a special code in the C/I channel. a) 22 PDIL : MTC-20172-PD b) 28 PLCC : MTC-20172-PC AUX2 3 2 1 28...

  • Page 18: Pin And Package Data

    Data Sheet & Reference Manual Rev. 1.1 February 1997 3. Pin and Package Data 3.1 Package and Dimensions The MTC-20172 SIC is available in two package styles. For specific requirements, please contact your Mietec representative. 28 pin plastic leaded chip-carrier (28PLCC).

  • Page 19: Pin Allocation And Short Description

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 3.2 Pin Allocation and Brief Description Table 3.1 contains the pin number for the each package style, the pin name, I/O type, and a brief description. The I/O column describes the Input/Output buffer type used.

  • Page 20: Table 3.1: Pin List And Description, 22 And 28 Pin Package

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 Table 3.1: Pin List and Description, 22 and 28 pin Package name Description Supply voltage +5V 5% Supply voltage 0V RSTB Reset signal, inverted polarity AUX2 Previously Rref input, analog I/O test pin,...

  • Page 21: Input/Output Types In Function Of The Modes

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 3.3 Input/Output Types in Function of the Modes Table 3.2 : Input/Output types in function of the modes XTR4 pos. MOD2 MOD1 MOD0 AUX4 AUX3 AUX1 SCLK XTR3 XTR2 XTR1 XTR0 DOUT DIN...

  • Page 22: Values And Usage Of The Pull-Up Devices

    4.11, 4.12) in certain modes. It has an internal pull-up of nominally 50kΩ in those modes. DIN: In the MTC-20172 SIC, the DIN pin is a simple input. DOUT: In the NT modes , the DOUT pin is an open drain with an inte- grated pull-up resistor of nominally 20 kΩ.

  • Page 23: Functional Description

    4.1 General Features 4.2 Compatibility 4.3 Improved Features The main properties of the circuit are: The MTC-20172 SIC is a single * The ternary S-bus receiver is - Single Chip Transceiver on the component, which can cover all balanced, backwards compatible 4 wire S-bus, single 5V supply;...

  • Page 24: Overview Of The Use Of Mtc-20172 Sic In The Isdn System

    A with application note. 4) LT-T mode: Inside the NT2 (e.g. a sion of two B-channels (64 kbit/s When the MTC-20172 SIC is in an un- PABX) at the T-interface, which is each) and one D-channel (16 kbit/s). powered state (supply voltage = 0 V)

  • Page 25: The Gci Interface

    GCI interface. with the commands (towards MTC- Interface 20172 SIC) or the indications (from In the LT-T, the MTC-20172 SIC must MTC-20172 SIC), and two extra bits At the digital control interface, the handle jitter, wander and slip between (MR and MX) to control the M-channel.

  • Page 26: Power-Down On Gci

    250 µs. used to write and read the internal 1/40 every 250 µs. Note that jitter MTC-20172 SIC registers. Its use is on the 192 kbit S-bus signals is a The GCI clock and frame are optional in the MTC-20172 SIC.

  • Page 27: Clock Speed

    TE mode. To accept the S-bus or the GCI interface. used to halt the clock (either by MTC- wander of 18 µs, the MTC-20172 SIC 20172 SIC in TE, or by the controller has a long FIFO buffer between the The GCI part runs at the clock speed in NT).

  • Page 28: Mtc-20172 Sic Activation

    SIC Activation Activation in TE Mode Activation in LT/S and LT/T Modes Activation of the MTC-20172 SIC Activation through the S-bus is depends on the position and mode. possible. The signal detector enables In this case, the GCI bus cannot be the crystal, the GCI clock and frame is shut down.

  • Page 29: Modes Of Operation

    MTC-20172 SIC. in 4.12. The mode is determined by the state of the MOD2-0, XTR0-4, SCLK pins, as shown in Table 4.2. Table 4.1.a: Basic modes of operation with the MTC-20172 SIC APPLICATION LT-T LT-T LT-S LT-S...
  • Page 30 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 Table 4.1.b : Extended modes of operation of MTC-20172 SIC APPLICATION LT-T LT-S Operation GCI or of GCI Mode Inverted# Inverted# Mode or interface Submodes Inverted selected in SW Mode#...
  • Page 31 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 Table 4.2 : Basic and Extended mode-selection pins in MTC-20172 SIC pos. bus type MOD2 MOD1 MOD0 SCLK XTR3 XTR2 XTR1 XTR0 inverted inverted LT-T GCI/inverted LT-S GCI/inverted LT-T GCI/inverted...

  • Page 32: Functional Explanation Of The Special Signals

    LP- : Loss of Power input and output; INFO3 transmission in response of these signals are NOT IMPLEMENTED INFO2 or INFO4, is allowed without in the MTC-20172 SIC. CON after synchronization. This signal in NOT overridable via the GCI MFD : Multiframe Disable when 1, M-channel.

  • Page 33: Detailed Operational Description Of The S-Bus Interface

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 5. Detailed Operational Description of The S-Bus Interface Introduction 5.1.1 Transmission Rate An overview of the functional environ- The nominal transmission rate is 192 ment is given in chapter 4. In this chap- kbit/s in each direction.

  • Page 34: Ami S-Bus Coding (General In Rx And Tx)

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 5.1.3 AMI S-bus Coding (general in RX and TX) For both directions, a pseudo-ternary coding (AMI) is used. A binary '1' (high level logic) is coded as 'no signal' whereas a binary '0' state is represented by alternating positive and negative pulses (see Figure 5.2).

  • Page 35: Synchronization Principles, With Adaptive Bit-Timing

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 5.1.8 Synchronization 5.1.9 Synchronization Principles, with Adaptive Principles, Fixed Bus Timing at Bit-timing NT/LT-S 1) The receiver first finds the AMI On a short passive bus, the position of violations by oversampling.

  • Page 36: Transmitted Frames

    Depending on the activation state of INFO0 No signal, open circuit INFO0 No signal, open circuit the interface, the MTC-20172 SIC can transmit different signals called INFO INFO2 Frame with all bits of INFO1 Continuous signal with 0, 1, 2, 3, and 4. Moreover, two test...

  • Page 37: S-Bus Transmitter Analog Blocks

    The pulse shape has 5% margin around the nominal height, when the MTC-20172 SIC supply voltage is nominal. When the supply voltage has a 5% range, the pulse will be within the 10% tolerance of the CCITT recommendations.

  • Page 38: Ternary Drivers : High-Ohmic State When Not Powered

    The 34Ω includes the real part of the impedance of the sending transformer. When an MTC-2072 SIC is replaced by the MTC-20172 SIC, the extra resistors must be added to the PCB. Originally the MTC-2072 SIC drivers...

  • Page 39: S-Bus Transmitter Timing And Framing; Jitter

    The 192 kHz is derived from the crystal frequency of 7 MHz, by division by 40. The transmitter framing The MTC-20172 SIC has an improved is at 4 kHz. The timing is slaved to the ternary receiver. It is fully balanced, to downlink clocks, the 4 kHz S-bus better reject longitudinal noise.

  • Page 40: Ternary Receivers: Impedance While Not Powered

    TE (or LT-T) position, when the step to avoid continuous toggling of multiple drivers can enhance the F-bit bus is active but the MTC-20172 SIC the gain (i.e. hysteresis). up to 140%. The amplitude of the F-bit is not powered, a minimal input...

  • Page 41: Filtering

    2 subsequent frames, The bit-sampling moment is fixed, and oversamples the incoming bits with a MTC-20172 SIC restarts the hunt of coupled with the TX bit clock, which in fixed threshold, which is at 33 % of the 5.3.11.1.
  • Page 42 100 mVpp (peak to peak) is applied, In between t1 and t2, the RX part as specified in CCITT I.430 8.6.2.1. In the MTC-20172 SIC, the theoretical counts "Y", the number of zeros, igno- zero crossing is derived from the t2 ring possible marks.

  • Page 43: Timing Relation Between Rx And Tx On The S-Bus

    S-bus signals. E- The timing relation between RX and TX channel operation is only correct if the In all modes of the MTC-20172 SIC on the S-bus depends on the MTC- delay is 0 to 8 bits.

  • Page 44: S-Bus Transmitter Clock And Frame In Te Mode

    GCI clock to the crystal. multiple D-channels in a star L. The MTC-20172 SIC will force the Note also that activation via the S-bus configuration to a single HDLC leading edge of bit 0 of the B2 is possible during the loop mode.

  • Page 45: E-Channel Generation In Nt/Lt-S

    (pin XTR0 in NT channel considerations are explained mode, pin AUX4 in LT-S mode). Each in 6.5.6. MTC-20172 SIC can pull the bus low with an open drain output. 5.6.2 E-Channel Generation In When a group of SICs is tied to a DE/...

  • Page 46: D-Channel Access In Te/Lt-T

    The collision detection is based strictly fair access protocol is defined on E-channel observation. The TE Note that each individual MTC-20172 by the CCITT I.430. To detect the which sends D = binary one which is SIC tied to the DE/CEB bus must work...

  • Page 47: D-Channel Access Working Principles For The Mtc-20172 Sic

    The priority is diagram, to allow the last zero of the indicated via the C/I nibble in the tail flag to leave. The MTC-20172 SIC GCI B1*-channel, see 6.5.10. has only a limited control on the Fig. 5.7 : State Diagram of...

  • Page 48: Ready Signal

    50 % of the time. Giving more BUSY bit in the M-channel change anticipation is impossible, because simultaneously. The MTC-20172 SIC has a BUSY bit then it could happen that the ready in the GCI M-channel at the 5th indication arrives too soon at the position (numbering 1 to 8), in TE and HDLC controller.

  • Page 49: E-Channel To External-Hdlc Device At Te Position

    MTC-20172 SIC can send a When multiframing is disabled, the multiframe indication and the S- MTC-20172 SIC will send the FA and The D-channel access can also be channel at 800 bit/s. the M bits and also the S-channel as controlled outside the MTC-20172 binary zero, in downlink direction.

  • Page 50: Functional Behaviour At Te/Lt-T Side

    FA = 1, in response to each downlink frame with FA = 1. Table 5.1 : Multiframing Sequence (with i = 2, 3, 4 or 5) Synchronization at the TE/LT-T: When the MTC-20172 SIC sees M = 1, and frame number FA downl. FA uplink M downl.

  • Page 51: The Gci Interface

    Moreover, - V* master mode, with clock at 512 generated by the MTC-20172 SIC. the MTC-20172 SIC can use one of 8 kHz; Here, the timing is slaved to the S-bus consecutive GCI channels, numbered 0 - V* slave mode, defined at 4096 kHz, and the network.

  • Page 52: Channel Selection

    POWER-DOWN the serial data lines. The clock entering the MTC-20172 SIC can be ANY The MTC-20172 SIC will access the first The principles of the shut down multiple of 16 kHz between 512 kHz GCI channel group after the frame procedure are shown in Figure 6.1a.

  • Page 53: Fig. 6.2 Sdl Diagram Nt

    7 MHz clock on the XTLI pin can be After validating the DC or DId, the shut down. downstream device goes to the idle Here, the MTC-20172 SIC is a slave on state, it will release the upstream data the GCI bus. The asynchronous signal detector is...

  • Page 54: Fig. 6.3 Sdl Diagram Lt-S

    6.2.4.2 Power-down and Extended Basic Power-up in TE Mode Extended In the TE mode, the MTC-20172 SIC is Basic master of the GCI timing. POWER-down of the MTC-20172 SIC in TE mode The procedure to shut down the GCI bus...

  • Page 55: Fig. 6.4 Sdl Diagram Te, Lt-T

    In the LT-S/LT-T modes the GCI bus is not put in power-down. The GCI clock and frame run continuously. However, the MTC-20172 SIC can be forced in a low power state via the dedicated "1111" command. This is the "did" or DC command in LT-S and the DIu command in LT-T, see 6.5.9...

  • Page 56: The B-Channels On The Gci Bus

    The C/I channel works according to the Mietec MTC-2072 SIC. It can be linked to the MTC-2071 UIC (4B3T) of MIETEC and the IEC of Siemens at the NT. The MTC-20172 SIC is fully compatible, with a few extra commands available. 2) The GCI version The C/I channel is compatible with many other devices.

  • Page 57: General Information On The C/I State Diagrams

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 the V*, some indications were split or The LT-S diagram is a simplified version The commands and indications are added. of the NT state diagram. One will notice commented in 6.5.5 to 6.5.10.

  • Page 58: State Diagram For The Nt Position

    "AIu" and waits for "AId" (or AIL) to prevent accidental errors. The MTC- synchronizes. go to the G3 state. The MTC-20172 20172 SIC accepts a command only SIC signals "AIu". ARL (the loop 2 after it is present for 2 consecutive...

  • Page 59: Fig. 6.8 Activation Sequence Incoming Call

    Modes, the reset is shown dif- ferently. However, for the Basic mode, the reset state (12) is a sub-state hidden in state (3). In the MTC-20172 SIC, the split states (3) and (12) are implemented for the Basic and extended modes.

  • Page 60: State Diagram For The Lt-S Position

    16 ms of INFO0 reception, the 20172 SIC on the AR command is not they are not terminated correctly. MTC-20172 SIC goes to state (2). required. However, the MTC-20172 SIC reacts on AR in state (1) as (2) G4 Unacknowledged indicated.

  • Page 61: State Diagram For The Te/Lt-T Position

    AMI signal). MTC-20172 SIC state (1) is not required. However, indicates "ARu". Without waiting Some remarks are the same as those MTC-20172 SIC reacts on AR in state for the "ARd" command, the MTC- listed under the NT description. (1) as indicated.
  • Page 62 INFO3 is sent without receiver is NOT synchronous yet the checking the CON condition. (6) F7 Activated MTC-20172 SIC is in state (12). Once MTC-20172 SIC achieved INFO4 the receiver is synchronous MTC- Remark 3: Some of the transitions in synchronization.

  • Page 63: The Commands And Indications, Basic Mode

    Data Sheet & Reference Manual Rev. 1.1 February 1997 6.5.5 The Commands and Indications of the Basic Mode The MTC-20172 SIC implements the full list of C/I codes of the basic mode as indicated below: Table 6.1: The Original Basic Mode Commands and Indications mode Terminal equipm.

  • Page 64: Commands And Indications Extended Mode

    Data Sheet & Reference Manual Rev. 1.1 February 1997 6.5.6 Extended Mode Commands and Indications The MTC-20172 SIC implements the full list of C/I codes of the extended mode as indicated below: Table 6.2: Extended mode commands and indications mode Terminal equipm.

  • Page 65: C/I Equivalence Table

    (uplink an downlink). Those are cation codes (i.e. used * unused) are marked as single C/I in Mixed Case. merged in the MTC-20172 SIC. This is marked with "&". The command used All commands and indications which in one device is allowed in the unused have different abbreviation but same position of the other device.

  • Page 66: Command And Indications For Nt Applications

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 6.5.8 Command and Indications for NT Applications Table 6.4.a : MTC-20172 SIC C/I : NT overview Downstr Upstr. Downstr Upstr. Command Indicat. Command Indicat 0000 1000 0001 -& * RES (lsl)*&-...

  • Page 67: Commands And Indications Lt-S

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 6.5.8.2 Indications (Upstream) in NT Mode Table 6.4.c : MTC-20172 SIC indications (US) NT 0000 Timing The MTC-20172 SIC requires GCI clocks and also Request Master clock input, if no crystal is used.
  • Page 68 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 6.5.9.1 Commands (Downstream) In LT-S Mode Table 6.5.b : MTC-20172 SIC commands (DS) LT-S 0000 DR # Deactivate Forces MTC-20172 SIC to deactiv. the S-bus (=INFO0) Request followed by DIu and did=DC...

  • Page 69: Commands And Indications Te/Lt-T

    "TIM" indication is not expected from the basic mode, it cannot be allowed it to appear in the C/I channel in LT-S modes of the MTC-20172 SIC. As the GCI bus is never shut down in LT-S modes, the timing request "TIM" is not needed.
  • Page 70 This loop is not transparent, it is a special case, see text 6.5.4 1111 Deactivate GCI clock can be disabled by MTC-20172 SIC together Indication with other clocks see 6.2.4 * Marks functional difference; & Marks difference that can be merged.
  • Page 71 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 6.5.10.2 Indications (Downstream) in TE/LT-T Mode Table 6.6.c: MTC-20172 SIC common indications (Downstream) in LT-T mode 0000 Deactivation Deactivation request via S/T-bus: state F3 Request reached in state diagrams 0100...

  • Page 72: Fig. 6.10 Sdl Diagram Te/Lt-T, Unconditional States, Extended Mode

    The frame buffer slipped, cause is wander Meaning identical to "sd" for basic mode 1010 Activate Acknowledges ARL, loop 3 closing, MTC-20172 SIC Request loop sends INFO3/4 not transparent to S-bus, receiver not synchronous on the looped signal; replaced by PU in the basic mode 1110 Activate Ind.

  • Page 73: M-Channel + Mx + Mr : Physical Layer

    The bytes are organized in subsequent bytes. messages. The MTC-20172 SIC will adjusts to any 6.6.2 M-Channel Format, Bit and Use and Compatibility lower speed on the channel, but it can Byte Numbering Convention The M-channel should not be used in the transfer one M-channel byte in 250 µs...

  • Page 74: Byte Transfer Procedure

    For that purpose, the two M- On detection of the SOM, the receiver 6.6.3.4 Further Byte Transfers channels (to and from the MTC-20172 will read the M-byte. It will SIC) have separate handshake bits, acknowledge reception, provided that...

  • Page 75: Fig. 6.13 Examples Of Received M-Channel Messages

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 to the active state (negative edge 1 to 6.6.3.5 Further Byte 6.6.3.8 Sender Not Ready 0), before transmitting the second byte, Acknowledgement see previous paragraph. If the sender is not ready (second byte...

  • Page 76: Comments On The Mtc-20172 Sic M-Transceiver State Diagrams

    The transmitter changes states half-duplex direction, if a message The MTC-20172 SIC aborts a message synchronous with the MX, MR reception must be sent; ONLY when it is forced in HARD RESET.

  • Page 77: M-Channel Messages And Registers

    In the basic mode, the use of the M- channel is not necessary. However, it 7.5.2 S/Q M-Channel Messages, is available to allow access to the In the MTC-20172 SIC in TE/LT-T, the MTC-20172 SIC In TE/LT-T With Multiframing multiframe S and Q bits, and to...

  • Page 78: S/Q M-Channel Messages, Mtc-20172 Sic Multiframing Disabled

    MTC-20172 SIC Multiframing The second nibble is the address of Disabled the internal register, limited from 1 to 6 in the MTC-20172 SIC. The write If Multiframing is not enabled, the addresses must differ from 0000, MTC-20172 SIC ignores the content...

  • Page 79: Detailed Bitmap Of The Internal Registers

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 7.7 Detailed Bitmap of the Internal Registers Table 7.1: Register Bitmap of MTC-20172 SIC name sent first sent last I.D. BUSY READ V.N. BUSY READ CONF BT1/SC DEX1 DEX0 BUSY...

  • Page 80: Output Register; Write And Read; Address 3H

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 7.7.4 Output Register; WRITE and READ; Address 3h AUX4b1 AUX4b0 AUX3b1 AUX3b0 BUSY TEST AUX1b1 AUX1b0 Reset AUXib1 AUXib0 : Configure the AUX4, AUX3 and AUX1 input/output pins : The AUXi pin works as listed in 4.11 and 4.12 : The AUXi pin is tristate and usable as input.

  • Page 81: M-Channel Operation Messages Overview

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 7.8 M-Channel Operation Messages Overview Table 7.2: M-Channel Message Overview To the SIC From the SIC READ message WRITE message CONTENT mess. register name Byte 1 Byte 2 Byte 1...

  • Page 82: Loops, Test Modes, System Tests

    The tests outlined in 8.3 and 8.4 are These are mainly functional tests, analog part of the MTC-20172 SIC. system tests, performed by the user - described here to assist the evaluation they are not used to test proper device of the device in a real application.

  • Page 83: System Tests, For Characterization Of All Modes

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 and SCZ- pins of MTC-20172 SIC 8.4.4 D-Channel Access Protocol 8.4.7 S-bus Input to Output low. MTC-20172 SIC will send the (TE/LT-T) "ei" indication to the UIC, which Correctness, fairness, advance of the responds with the test signal.

  • Page 84: Electrical, Physical And Environmental Specifications

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 9. Electrical, Physical and Environmental Specifications 9.4 Recommended Related documents: In case of IC deliveries not in dry bag, Electrical Operating See chapter 11. the conditions for a maximum storage...

  • Page 85: Static Characteristics

    V amplitude (transformed with 2:1 a maximal (100%) mark density, while sending INFO4, with a normal ratio). If the MTC-20172 SIC S-bus digital inputs at VDD or VSS, digital (50%) mix of marks and zeros, on the outputs are driving a shorted bus an outputs unloaded, S-bus outputs nominal S-bus impedance.

  • Page 86: Static Characteristics Of Digital Outputs

    The worst case situation happens when symmetrical. Therefore, it will reject When the MTC-20172 SIC is not one input would be kept at a constant unwanted AC common mode noise powered, the AC input voltages are...

  • Page 87: Static Characteristics Of Analog S-Bus Outputs

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 9.5.5 Static Characteristics Of Analog S-bus Outputs. Table 9.6: Static Characteristics of the S-bus Outputs PARAMETERS TEST COND. UNIT Ω External Series Impedance SIC side Ω Output Impedance MARK on S-bus...

  • Page 88: Dcl Output Clock (Te) And Other Derived Clock Signals

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 However, the clock period is allowed to be modulated, as could be needed to adjust its frequency. In all applications (NT/TE/LT) the period can be shortened to as low as 65 ns, provided that the width (high or low) never descends below 20 ns.

  • Page 89: Serial Gci Interfaces

    Figure 9.2 explains the general behaviour of the signals. Note the frame signals and the SLAVE modes, MASTER modes (TE), where the MTC- where the MTC-20172 SIC receives 20172 SIC generates the DCLK clock DCLK clock and DFR frame. and DFR Table 9.9: Characteristics of GCI Signals, Master modes...

  • Page 90: Fig. 9.3 Gci Timing Parameters In Nt, Lt-S And Lt-T Mode

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 9.6.3.2 SLAVE Modes Figure 9.3 shows the timing parameters. Fig. 9.3 : GCI Timing Parameters in NT, LT-Sand LT-T Mode Table 9.10: Characteristics of GCI Frame, Slave modes PARAMETERS DESCRIPTION...

  • Page 91: Rdy Pin

    Force unconditional state change of Delay to the GCI DCLK signal is bus pull the bus low when a D-channel the MTC-20172 SIC to send TEST1 or maximally 100 ns, for a 50 pf load. bit at binary 0 is sampled, i.e. a TEST2 signal on the S-bus outputs.

  • Page 92: Quality And Reliability Specification

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 10. Quality and Reliability Specifications Related documents: See chapter 11. 10.1. Quality 10.1.1 Product acceptance tests All products are tested 100 %, at guardband, by means of production ambient temperatures with full...

  • Page 93: Delivery Lot Certification

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 10.2 Reliability 10.1.4 Delivery lot Certification 10.2.3 The Useful Life Specification Each delivery lot to be accompanied by The useful life, when used under a Certificate of Conformance In order to guarantee the specified...

  • Page 94: Related Documents

    (3) ISDN Application note - CCITT LAPD. AN0148a (4) GCI interface, Industry standard bus, description agreed by Siemens, Alcatel, Plessey and Italtel. Evolution of the Siemens IOM-1 (trademarked), and later further enhanced to Siemens IOM-2 (also trademarked). (5) "Mietec Packaging Handbook" PB026a, and specification number 16505 (6) "Standard Marking specification", specification number 16020...

  • Page 95: Application Note : Ets-Tm3 Qualification

    12.3 ETSI-TM3 Configuration Setup In order to pass succesfull the conformance test procedures a Fig. 12.1 : MTC-20172 SIC external circuity number of device dependant parameters mst be set : 12.3.1 Network Terminations (NT) 12.3.2 Terminal Equipments (TE, LTT) Use a range for PX M;...

  • Page 96: Qualification Results

    Rev. 1.1 February 1997 12.4 Qualification Results Results will be shown for the pulse tem- Transformer Transmitter series MTC-20172 version plate tests and input and output impe- resistance dance tests. The LCL test is not mentio- ned in this application note because it VAC ZKB505/105 2 x 34Ω...

  • Page 97: Fig. 12.3 Output Pulse Template For 400Ω

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 12.4.1.2 Output Pulse Template for 400Ω Fig. 12.3 : Output pulse template for 400Ω...
  • Page 98 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 12.4.1.3 Output Impedance Power off State Fig. 12.4 : Output impedance State_F1 12.4.1.4 Output Impedance Power on State Fig. 12.5 : Output impedance State_F1...
  • Page 99 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 12.4.1.5 Input Impedance Power off State Fig. 12.6 : Input impedance State_F1 12.4.1.4 Input Impedance Power on State Fig. 12.7 : Input impedance State_F1...

  • Page 100: Application Note Network Terminator

    MTC-20172 in a network termination (NT) configuration. Also 13.2.1 Schematic Diagram recommendations are given for the choice of external components in the See figure 13.1 receive and transmit path. see Figure 2 Fig. 13.1 : MTC-20172 SIC in NT mode with MTC2071 UIC...

  • Page 101: Description

    MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997 13.2.2 Description The SIC receives its clock from the UIC via the pin CLS. This clock (7.6BMHz) Atthesubscriberpremises,the2–wire is synchronous to the received data at U–interface is terminated by a UlC in the U–interface and is derived from...

  • Page 102: Requirement For The Input And Output Stage

    Data Sheet & Reference Manual Rev. 1.1 February 1997 13.3 Requirements for the Input and Output Stage Fig. 13.3 : Schematic of MTC-20172 input and output stage In the receive path the So-interface is (so 80Ω seen at the secondary of the terrninated with 50Ω...
  • Page 103 MTC-20172 Data Sheet & Reference Manual Rev. 1.1 February 1997...
  • Page 104 The information furnished by Alcatel Mietec in this other rights of third parties resulting from its use. Alcatel Mietec reserves the right to make changes in document is believed to be accurate and reliable. No licence is granted under any patents or patent rights specifications at any time and without notice.

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