MAI Basic Four 2000 Series Service Manual

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Basic Four

Series 2000

Desktop Computer System

8079

Service Manual

BFISD

Table of Contents

Summary of Contents for MAI Basic Four 2000 Series

Page 1 Basic Four Series 2000 Desktop Computer System 8079 Service Manual BFISD...
Page 3: Table Of Contents
Specifications ........1-5 SECTION II INSTALLATION AND OPERATION General ..........2-1 Unpacking and Inspecting the Base Unit ..... 2-1 Installing the 2000 Series Computer System ..2-1 Switch Settings, Jumper Placements, Cable Connections ........2-7 2.4.1 Central Microprocessor Board ..... 2-7 2.4.2...
Page 4 BFISD 8079 TABLE OF CONTENTS (continued) Page SECTION III FUNCTIONAL DESCRIPTION (cont'd) 3.2.6 Interrupt Logic ....3.2.6.1 Interrupt Control Logic ... . 3-10 3.2.6.2 Interrupt Acknowledge Decoder .
Page 5 BFISD 8079 TABLE OF CONTENTS (continued) Page SECTION III FUNCTIONAL DESCRIPTION (cont'd) 3.2.19.3 MFM Data Separation ....3-57 3.2.19.4 Bit-Shifting....3-61 3.2.19.5 Floppy Drive Disk Control .
Page 6 BFISD 8079 TABLE OF CONTENTS (continued) Page SECTION 5.25" FLOPPY DISK DRIVE (cont'd) 7.1.2.1 Stepper Motor Control ... . . 7.1.2.2 Drive Motor Control ....7.1.2.3 Head Load Circuit .
Page 7 BFISD 8079 TABLE OF CONTENTS (continued) Page SECTION VIII 20 MEGABYTE WINCHESTER DRIVE SYSTEM (cont'd) 8.3.1 Basic Disk Principles ....8-11 8.3.2 Control Lines....8-13 8.3.3 Winchester Drive...
Page 9 BFISD 8079 LIST OF ILLUSTRATIONS Figure Page Model 4108 Base Unit....Block Diagram of the Base Unit Hardware System. . . The Layout of the Central Microprocessor Board. . . Rear View of Base Unit, Showing Location of all Connectors .
Page 10: Location Of Jumpers On Central Microprocessor Board
BFISD 8079 LIST OF ILLUSTRATIONS (continued) Figure Page 5—1 Location of Jumpers on Central Microprocessor Board ..... . Central Microprocessor Board Cable Part Numbers . . Location of Address Switches on Memory Array Module.
Page 11: Location Of Jumpers On The Winchester Drive Controller Pcba
BFISD 8079 LIST OF ILLUSTRATIONS (continued) Figure Page 7-29 Read Timing Diagram ....7-16 7-30 DC Control Circuit ....7-16 7-31 Power-On Reset Circuit...
Page 13 Table Page Specifications, MAI 2000 Series Desktop Computer System ..... . CMB Jumper Configuration....
Page 14 BFISD 8079 LIST OF TABLES (continued) Table Page 8-11 Type 1 Error Codes, Controller ..8-26 8-12 Type 2 Error Codes, Command and Miscellaneous . . . 8-27 8-13 Request Sense Status Error Codes .
Page 15 BFISD 8079 PREFACE This manual provides service information for the Model 4108 Base Unit, used in the MAI® 2000 Series Desktop Computer System. The information is presented as an aid for field service personnel and supports the installation, operation and maintenance of each device contained in the Base Unit.
Page 16: Model 4108 Base Unit
BFISD 8079 Figure 1-1. Model 4108 Base Unit...
Page 17: Section I
A maximum of six plug-in memory array boards provides 1.5 megabytes of system (main) memory. SYSTEM DESCRIPTION The configuration of the MAI 2000 Series Desktop Computer System is defined by the architecture of the Model 4108 Base Unit. Hence the following discussion...
Page 18: Central Microprocessor Board (Cmb)
BFISD 8079 Figure 1-2. Block Diagram of the Base Unit Hardware System. 1.2.1 Central Microprocessor Board (CMB) The CMB logic comprises three major functional areas: (1) the central processor section, (2) the memory control section and (3) the I/O section. The sections are linked primarily by the system bus structure.
Page 19: Memory Array Boards
BFISD 8079 Figure 1-3. The Layout of the Central Microprocessor Board. For an entry-level system, external peripherals are provided for by two serial (RS-232) connectors and one parallel connector. Logic and controllers for these are located on the GMB. The parallel connector allows attachment of the MAI/Basic Four®...
Page 20: 1.2.3 Winchester Disk Controller Board
BFISD 8079 1.2.3 Winchester Disk Controller Board The Winchester Disk Controller (WDC) board supports one or two Winchester (hard disk) drives, both residing in the Base Unit. (Two drives are possible only in the absence of floppy disk drives.) The WDC board, via its bus adapter, pro- vides high performance DMA (direct memory access) to the system memory.
Page 21: Local Area Network Controller Board
Local Area Network Controller Board The Local Area Network Controller (LANC) board allows the creation of a local area network (LAN) or, where possible, allows connection of the MAI 2000 Series Computer System to an existing network. The LANC board is a single-channel communications controller, providing an interface to CORVUS-licensed OMNINET.
Page 22: Specifications, Mai 2000 Series Desktop Computer System
BFISD 8079 Table 1-1. Specifications, MAI 2000 Series Desktop Computer System (continued) PARAMETERS CHARACTERISTICS Input Surge Current Less than 35 amperes , maximum peak Frequency 50 or 60 hertz LINE FUSE 100-120 VAC 6A, "Normal-Bio" 220-240 VAC 3A, "Normal-Bio" POWER SUPPLY OUTPUTS Voltage +5.000 and +12.000 VDC (nominal)
Page 23 BFISD 8079 Table 1-1. Specifications, MAI 2000 Series Desktop Computer System (continued) PARAMETERS CHARACTERISTICS Winchester Disk Drives One or two 5 1/4-inch, non-removable hard disks (two drives may be installed only in the absence of floppy drives) Serial I/O Channels...
Page 25: Installation And Operation
SECTION II INSTALLATION AND OPERATION GENERAL The Base Unit of the MAI® 2000 Series Computer System is designed to work in a normal office environment, free from dust and dirt. Hence, there are few restrictions on the suitability of location.
Page 26 BFISD 8079 CAUTION Only three-wire connectors and three-pronged plugs with the third wire connected to earth ground are acceptable electrical connectors. No two-wire con- nectors or plugs, with or without connection to a conduit ground, are to be used. Unstable equipment operation may result.
Page 27 BFISD 8079 Connect a video display terminal to serial port 3 (the leftmost port of the four serial ports on the bottom 4-Way Controller board, as seen from the rear of the Base Unit. (Note: If you are connecting a Model 4310 EOT, the cable part number is 907753-001, and the PA end connects to the Base Unit.) Secure all connector screws.
Page 28 BFISD 8079 Proceed with normal system load by pressing CR for Boot Device and then pressing CR again for SYSTEM FILE. Press CR again when the date prompt comes on the screen. (Note: If the operating system does not load, refer to the User's Guide, BFISD 6203A.) The following is an example of what you will see on the screen at this point (last few lines only):...
Page 29 BFISD 8079 Connect the rest of the peripherals to the Base Unit. Refer to the appropriate installation/maintenance manuals for setup procedures. A parallel printer may be connected to the Base Unit parallel I/O port (port 2, 37-pin connector). A serial printer or another terminal may be connected to Base Unit serial I/O port 1 (25-pin RS-232 connector).
Page 30 BFISD 8079 Select PORT CONFIGURATION (2). (Refer to the User's Guide, BFISD 6203A, "Utilities" section, for details.) Press CR and select ADD DEVICE. Type in the port number. Type in the number corresponding to the device type. Type in the number corresponding to the device model. Select a device name.
Page 31: Switch Settings, Jumper Placements, Cable Connections
BFISD 8079 Verify operation of the Magnetic Cartridge Tape Streamer (MCS) unit (if present) as follows: Log on by typing in 'admin' to get to the command interpreter. Turn on the MCS unit, insert a scratch tape. Label the tape by typing in MCSLABEL SET=TEST ID=TEST SER=1 (CR) (The utility will rewind the tape;...
Page 32 BFISD 8079 Figure 2-2. Location of Jumpers on Central Microprocessor Board...
Page 33 BFISD 8079 Figure 2-3. Central Microprocessor Board Cable Part Numbers...
Page 34 BFISD 8079 Connect jumper N between points 1 and 2. (This jumper allows the master oscil- lator to be disconnected from the dividers and buffers. An external oscillator can be injected at this point. Normal operation is with jumper N installed.) Connect jumpers C and P.
Page 35 BFISD 8079 PORT MODEM TERMINAL PRINTER Name Jumper B Cable Jumper B Cable Jumper B Cable CTSB 7 and 8 pin 5 7 and 9 pin 4 7 and 9 pin 4 DSRB 3 and 4 pin 6 3 and 1 pin 20 3 and 1 pin 20...
Page 36 BFISD 8079 Connect jumpers L and M. (The serial ports are capable of communicating at a number of different speeds and can communicate both synchronously and asynch- ronously. Jumper L connects the master clock to the Baud rate generator, used for asynchronous input/output.
Page 37: Cmb Jumper Configuration
BFISD 8079 For a standard Central Microprocessor Board configuration, recheck the jumper nstallation by referring to the jumper configuration table (2-1). The fol- lowing assumptions are made: 2732 or 2764 EPROMs 2K x 8 sector buffer Standard RS-232 DCE on serial ports A and B Analog Data Separator Standard density disk drives Table 2-1.
Page 38: Memory Array Pcba
BFISD 8079 2.4.2 Memory Array PCBA Set the appropriate switches for the desired physical address of the Memory Array PCBA. Refer to table 2-2 for a listing of switch settings, and see figure 2-4 for switch locations. Be careful not to duplicate addresses of existing Memory Array PCBAs;...
Page 39 BFISD 8079 Figure 2-4. Location of Address Switches on Memory Array Module 2-15...
Page 40 BFISD 8079 Figure 2-5. Location of Jumpers on (Single-Board) Winchester Disk Controller 2-16...
Page 41: 4-Way Controller Pcba
BFISD 8079 2.4.4 4-Way Controller PCBA Set the appropriate switches on the 4-Way Controller PCBA for the controller board address/DMA arbitration number and for the kind of peripheral(s) served by the Base Unit according to the listings shown in table 2-4. See figure 2-6 for the location of the switches.
Page 42 BFISD 8079 Figure 2-6. Location of Switches on 4-Way Controller PCBA 2-18...
Page 43 BFISD 8079 Figure 2-7. Location of Switch on Magnetic Cartridge Streamer Controller PCBA 2-19...
Page 44: Installing The Local Area Network (Lan)
One Tap Box™ A user's manual If this is the first 2000 Series system being installed, and a local area net- work does not yet exist, the following hardware also may be required. Network cables in 1,000-foot lengths, or shorter (total length not to...
Page 45 BFISD 8079 Figure 2-8. Location of Switches and Cable Information for LANC PCBA 2-21...
Page 46 BFISD 8079 The address switch comprises eight smaller switches, each set individually. The "off" position of each switch represents binary 1. SWITCH SW1 Bias Terminator Station Address ↑ ↑ ↑ ↑ ↑ ↑ * represents the "bias." Switch 1 is set to 1 (off) on only one LAN con- troller board in a network;...
Page 47 BFISD 8079 The Local Area Network Controller board now is ready to be Installed in the Base Unit. To do so, proceed as follows: Shut down the system, and turn off the Base Unit power. Insert a screwdriver, or similar device, in the slot at the bottom right-hand side of the Base Unit cover, and push in to disengage the the latch.
Page 48: Installing The Tap Box
BFISD 8079 2.5.2 Installing the Tap Box The Tap Box connects the tap cable to the LAN cable. It is a passive device, designed to allow easy connection of the Base Unit to the LAN cable. Once in- stalled, it should not be removed; to do so will break the network connection.
Page 49: 2.5.3 Installing The Repeater
BFISD 8079 The following instructionsare for creating the network tap connection. Cut the network cable at the place you wish the tap to be, and remove approximately one inch of covering from each of the two ends of the cable. This exposes the red, black and ground wires. Slide a rubber grommet over each end of the cable, and strip approx- imately 3/8 inches of insulation from all four red and black wires.
Page 50 BFISD 8079 Figure 2-10 shows the layout of the repeater box, indicating the position of the two screw connector terminal strips. The terminal strip at the top of the box is for connecting the power tranformer. The terminal strip at the bottom of the printed circuit board is for connecting the LAN cables.
Page 51: Connecting Network Segments
BFISD 8079 2.5.3.1 Connecting Network Segments The following procedure may be used as a guide for installing a repeater to connect two network segments. Open the repeater by removing the screws at the four corners. Strip all wire leads on the two LAN cable segments to be joined. Insert the red wire from one segment into the left-hand + connector on the terminal strip at the bottom edge of the repeater printed circuit board, and tighten the screw.
Page 52: Connecting Power To The Repeater
The local area network (LAN) software is supplied on a tape or a floppy disk- ette. The LAN software must be installed before local area networking can be used on the 2000 Series System. To install the LAN software, follow the procedure in Chapter 7, MAGNET 2000 Local Area Networking User's Guide, BFISD 6351C.
Page 53: Use And Care Of Floppy Diskette And Drive
BFISD 8079 With the LAN software installed, the customer may use the LAN Configuration Utility, according to his manual, MAGNET 2000 Local Area Networking User's Guide, BFISD 6351B. USE AND CARE OF FLOPPY DISKETTE AND DRIVE The Model 4108 Base Unit may contain no more than two 5-1/4 inch floppy disk drives, mounted one atop the other in the front panel.
Page 54: Write Protection
BFISD 8079 2.6.2 Write Protection Each box of diskettes provides a sheet of 3/4-inch foil stickers. These are called write protect tapes and are used to prevent alteration of the contents of the diskettes. Diskettes that have been write protected can be read by the drives, but no data can be recorded.
Page 55: Functional Description
CMB. CENTRAL MICROPROCESSOR BOARD (CMB) DESCRIPTION The CMB is the central processing unit (CPU) for the MAI® 2000 Series Desktop Computer System. The CMB embraces the single-board, integrated bus concept.
Page 56 BFISD 8079 Figure 3-1. Simplified Block Diagram, Central Microprocessor Board...
Page 57: Clock Generator
BFISD 8079 3.2.1 Clock Generator The 68010 microprocessor subsystem requires a master clock to make the system operate satisfactorily. An 8-MHz clock signal is produced by a 16-MHz master oscillator (5K) whose output is divided in half by a 74S112 J-K flop-flop (5J). (Refer to the CMB Logic Diagram, sheet 5.) Other clocks needed by the system are developed in a 74S161 4-bit...
Page 58: Boot Prom
BFISD 8079 The function code outputs from the 68010 are valid whenever the CPU Address Strobe (CAS-) output is asserted. Therefore, the decoder is gated by CAS- so that the decoding happens only when the function codes are valid. Also, the decoder is disabled when the 68010 has relinquished control of the bus (when the CPU Bus grant ACKnowledge [CBACK-] signal is asserted).
Page 59: Cmb Diagnostic Hardware
BFISD 8079 The Central Microprocessor Board can support three different size EPROMs: bytes, 16K bytes or 32K bytes. Whatever the size used, two EPROMs are wired in parallel with respect to the address bus to give a word size 16 bits wide. highest boot PROM address depends, of course, on the size EPROMs used;...
Page 60: Main Memory Fault Detection Circuits
BFISD 8079 Table 3-1. Central Microprocessor Board Status Bits NAME DESCRIPTION CDOO+ MMERF+ Memory management unit error flag CD01+ PARITY+ Main memory parity error flag CD02+ RTCZERO+ Hardware timer count zero interrupt flag CD03+ PFD+ Power fail flag CD04+ Always high CD05+ Always low CD06+...
Page 61: Central Microprocessor Board Control Register Bits
BFISD 8079 Table 3-2. Central Microprocessor Board Control Register Bits ADDRESS (HEX) BIT NAME FUNCTION 200000 TSTOL Drives testpoint TP8 high for testing purposes; otherwise it is always low 200002 TSTERL Drives test point TP9 high for testing purposes; otherwise it is always low 200004 TSTMD+ Inhibits the parallel port drivers;...
Page 62: Parity Error Register
BFISD 8079 The base address of the faulty memory chip and two bits of GMB status are stored in a parity error register. The parity bit to the CMB status driver is set. A 68010 level 7 interrupt is generated. 3.2.5.1 Parity Error Register The parity error signals from the 74S280s (2V and 3V) are gated in the parity...
Page 63: Parity Error Interrupt Cycle
BFISD 8079 3.2.5.3 Parity Error Interrupt Cycle When a parity error occurs, the SINT7- output from the parity logic PAL (6Y) is asserted. SINT7- latches a flip-flop whose Q output then sends a low to the 7 input of an 8-to-3 priority encoder. (Refer to the CMB Logic Diagram, sheet 22.) The output forms an interrupt request via three 68010 interrupt request...
Page 64: Interrupt Control Logic
BFISD 8079 LEVEL SOURCE Parallel port, from the PI/T (local) System I/O bus peripheral device controllers Floppy disk controller (local) System I/O bus peripheral device controllers Serial ports, from the SCC (local) PI/T timer—real time clock count is zero (local) Power fail, reset, parity error (non-maskable interrupt) 3.2.6.1...
Page 65: Interrupt Acknowledge Decoder
BFISD 8079 Then, as in the autovectored case, the content of the vector number (after multiplication by four) is fetched and then loaded into the 68010 program counter, and normal instruction execution begins in the interrupt service routine. This is the bus-vectored interrupt mode of the 68010. The data selector (10K) thus is used to switch between autovectoring and bus- vectoring for interrupt levels 2 and 4.
Page 66: System I/O Bus Control Logic
WR- (WRite), which is asserted when the 68010 is in a WRITE cycle. 3.2.9 Non-Volatile RAM For flexibility; the MAI® 2000 Series system allows the system console to be chosen from several kinds of terminals and to be connected to any available serial port.
Page 67 BFISD 8079 • System boot device, unit number and baud rate • System console terminal type, port and baud rate • System printer port and baud rate, if serial • System download port and baud rate The Central Microprocessor Board provides a means for inputting the parameters and for storing them while power is off.
Page 68: Data Transfer Acknowledge Generator
BFISD 8079 The data must first be recalled from the EAROM section by a supervisor READ to memory location 6CXXXX, which transfers the data to the RAM section. Then, the data may be read by doing supervisor reads to as many 68XOYY locations as is necessary (OYY is the NVRAM internal address).
Page 69: Nvram Contents
BFISD 8079 Table 3-3. NVRAM Contents NVRAM ADDRESS CONTENT 680000 Boot device type 680002 Boot device unit number 680004 Boot device baud rate (if applicable) 680006 Console device type 680008 Console device unit number 68000A Console device baud rate 68000C Printer device type 68000E Printer device unit number...
Page 70: Device Nybble Specifiers
BFISD 8079 Table 3-4. Device Nybble Specifiers PARAMETER NYBBLE SPECIFIER Device Type Serial Communications Controller 4-Way Controller Floppy Disk Controller Winchester Disk Controller Winchester Disk Controller (NEC) Magnetic Cartridge Streamer Controller Parallel I/O (PI/T) Unit Number Serial Communications Controller 4-Way Controller 0-15 Floppy Disk Controller Winchester Disk Controller...
Page 71: Timing Generation
BFISD 8079 Although the main system RAM memory is designed not to require wait states, the various "slower" peripheral chips on the Central Microprocessor Board do need wait states. The following paragraphs describe the hardware that generates the PDTACK- signal, and also introduce the Bus ERRor Flag (BERRF-) signal and in- clude a list of the wait states for the various slave devices.
Page 72: Bus Error Generation
BFISD 8079 A23+A-A21+A WAIT STATES DEVICE ADDRESSED Boot PROM during boot; system memory otherwise Local CMB status registers Boot PROM Local I/O (floppy controller; serial and parallel ports; Baud rate selection) Memory management unit control Memory management unit control Peripheral I/O controllers (external DTACK-) Interrupt acknowledge (external DTACK-) Note: One cycle of the clock equals two wait states (125 nanoseconds).
Page 73: Bus Arbitration Logic
BFISD 8079 The bus error flip-flop will reset when the shift register (7K) is cleared or the CVPA- signal is asserted. The timing of the shift register and bus error generation is shown in figure 3-2. When a peripheral device controller is the bus master, the bus error flip-flop Q output is gated onto the system I/O bus as BERR- by the bus grant acknowledge signal (CBACK+, discussed in paragraph 3.2.11), via another 74LS38 NAND gate (3F).
Page 74: Bus Arbitration Cycle
BFISD 8079 The arbiter prioritizes bus access requests by devices (i.e., peripheral con- trollers) aspiring to bus mastership. The design of the arbiter is such that the 68010 always wants the bus, but gets it only when no other device wants it. This means that the 68010 is the lowest-priority device in the system, giving up the bus to any requesting device as soon as possible.
Page 75: Fast Bus Grant
BFISD 8079 The priority bus signals indicate the highest number of four groups of four devices, one or more of which is requesting the system I/O bus. The group with the highest priority number on the bus qualifies to continue with the second step; any competing groups with smaller numbers may continue the bus request signal (BR-1).
Page 76: Address Space Decoding Logic
BFISD 8079 3.2.12 Address Space Decoding Logic Some devices on the Central Microprocessor Board are meant to be read from and written to, and others are meant to be read-only or write-only. (Table 3-5 shows the address space decoding.) This allows a simplification in design, in that a READ or a WRITE strobe may be combined with the chip enable strobe going to the restricted device.
Page 77 BFISD 8079 This is done with decoder chip 7Z. (Refer to the CMB Logic Diagram, sheet 9.) The chip decodes A20+A, A21+A, A22+A and A23+A, the four high-order address bits from the 68010 (via address drivers). Three decoder outputs are active during READ cycles only;...
Page 78: Read Cycle Decoding
BFISD 8079 3.2.12.1 READ Cycle Decoding When the decoder chip (7Z) is used for READ cycles, signal RD- must be active, and BOOT+ must be inactive (low), to enable the decoder. BOOT+ active enables the Boot PROMs, rather than the system memory, for all addressing at reset.
Page 79: Local I/O Decoding
BFISD 8079 When MDENB+ is inactive, column address strobes are prevented from going to the memory array boards, thereby deselecting the main memory. (A column address strobe is one of two enable signals required by a dynamic RAM chip--the other signal is the row address strobe [both are explained in paragraph 3.2.15].) 3.2.12.4 Local I/O Decoding...
Page 80: Memory Array Board Selection
BFISD 8079 3.2.14.1 Memory Array Board Selection MAD17+ through MAD20+ are the memory array board select strobes. (Refer to the CMB Logic Diagram, sheet 39.) The strobes are generated in one of two ways: • When the 68010 is in the supervisor mode, or a system I/O peripheral device controller is the bus master, system I/O bus address...
Page 81: Dynamic Memory Support
BFISD 8079 3.2.15 Dynamic Memory Support The memory array boards, which plug into the Central Microprocessor Board, use dynamic RAM chips. Interfacing with these is more complex than for static RAM chips. This is because the dynamic RAM chips require address multiplexing, for which timing is more critical.
Page 82: Memory Timing
BFISD 8079 Finally, unlike static RAMs, dynamic RAM chips cannot retain data indefinitely without external support logic. This is because data is stored as electrical charge in small "capacitors," and the charge tends to dissipate over a period of time. Hence it is necessary to refresh memory periodically.
Page 83 BFISD 8079 Figure 3-5. Simplified Block Diagram, Dynamic Memory Support Subsystem 3-29...
Page 84: Memory Refresh
BFISD 8079 Because 8-bit or 16-bit (byte or word) data are accessible in one memory cycle, two column address strobes are required: MCASL- (Memory Column Address Strobe Lower) and MCASU- (Memory Column Address Strobe Upper). Two 74S22 NAND gates (6Y and 6Z) decode both column address strobes: one pair is for memory write cycles, and one pair is for memory read cycles, determined by the R/W- (Read/ Write) signal.
Page 85: Refresh Address And Request Generation
BFISD 8079 Figure 3-6. Memory Control Timing Diagram To make this burden more tolerable, dynamic memory chips are arranged in two- dimensional arrays of bits, so that all bits in a row are refreshed when one bit in that row is read. Hence, refreshing requires only that each row of bits be read every 4 milliseconds.
Page 86: 3.2.15.6 Refresh Arbitration
BFISD 8079 The ripple carry output is asserted (high) for 1 clock cycle, or 1 microsecond. This is ANDed with the negative-going half cycle of the clock to produce the RFREQ+ signal, with a 500-nanosecond assertion time. (Jumper R can be inserted to eliminate refresh cycles during testing.) 3.2.15.6 Refresh Arbitration All refresh cycles require a system I/O bus arbitration procedure.
Page 87: Memory Management Unit
BFISD 8079 The refresh circuitry acknowledges the bus grant and drives the modulo 256 counter output (8 bits) onto the system I/O bus. The refresh circuitry issues a row address strobe, 250 nanoseconds in length, to the memory array boards. The refresh circuitry releases the system I/O bus.
Page 88: Swapping
BFISD 8079 The starting location and length of each segment are defined by the contents of segment registers on the Central Microprocessor Board (CMB). A logical address from the 68010 specifies the segment number and the offset into that segment. The content of the selected segment register then determines the actual memory location to be accessed by the 68010.
Page 89 BFISD 8079 Figure 3—8. Simplified Block Diagram, Memory Management Unit 3-35...
Page 90: Supervisor And User Access Of The Mmu
BFISD 8079 All of these detection functions can be set in CMB hardware. (A logical block diagram of the MMU error detection and status reporting functions is shown in figure 3-9.) How the CMB hardware performs these and the other functions dis- cussed in previous paragraphs is explained in the following paragraphs.
Page 91: Mmu Address Translation
BFISD 8079 3.2.16.5 MMU Address Translation The MMU translates address bits A09+ through A23+ from the 68010. Bits A01+ through A08+ are not translated but go directly to the memory (thus setting the inimum segment size to 512 bytes). (Address bit A00 does not exist outside the 68010.
Page 92: Segment Attributes
BFISD 8079 The addition is done in three 74S283 4-bit full adders (2X, 2Y and 2Z). (Refer to the CMB Logic Diagram, sheets 30 and 31.) The summed A09 through A16 are the column addresses for the memory array (MA1- through MA8-); these are driven onto the memory address bus by a 74S240 tristate inverter (IX), enabled by the NAND of PAENB- (Physical Address ENaBle) and CADSEL+ (Column ADdress SELect).
Page 93: Segment Status
BIFSD 8079 These are the ABSEG- (ABsent SEGment) and SEGDC(X)- (SEGment DeCode) signals: SIGNAL EXPLANATION ABSEG- Generates a memory management error (MMERR-) when an absent segment is addressed SEGDC1- Generates a memory management error when the logical address is equal to or greater than the limit address SEGDC2- Generates a memory management error when the...
Page 94: Mmu Error Generation
BFISD 8079 (Refer to the (MB Logic Diagram, sheet 34.) The W output of a 74LS151 l-of-8 data selector (7V) is the input to the segment-written bit of the 74S189 (7X). The W output always is high while the 68010 is in the supervisor mode. This is to allow the segment-written bit to be initialized before the 68010 switches to the user mode.
Page 95: Serial Ports
BFISD 8079 The memory access is a stack access (indicated by SEGDC2- or SEGDC3- asserted), and the address is less than the limit address (the stack address is out of bounds, indicated by ADLTLM+ asserted). SEGOVF-, ORed with ABSEG-, produces the SAERR- (Segment Access ERRor) signal, which is written to the segment status word register, as described in paragraph 3.2.16.7.
Page 96 BFISD 8079 Figure 3-10. Simplified Block Diagram, CMB Serial Ports 3-42...
Page 97: Simplified Block Diagram, 8530 Scc Chip
BFISD 8079 The interface with a serial peripheral device, on the other hand, is a serial interface in which those same data bits are transmitted on a single output line or received on a single input line, one bit at a time. The conversion occurs in the LSI serial communications controller chip, on the Central Microprocessor Board.
Page 98: Communications Protocol Selection
BFISD 8079 Serial Data Reception The receive and transmit sections each have separate data registers because of a need to buffer data in transit through the port. There is a variable delay between the receipt of a byte-wide datum from a peripheral and the availability of a 68010 bus cycle that will accept that datum.
Page 99 BFISD 8079 Synchronous Protocol In the synchronous mode, each successive datum in a data stream is controlled by a master data clock. Hence the clock controls not only the bits within a character byte, but the character-to-character spacing as well. (One benefit of this method is higher communication speed, as an entire block of data may be exchanged, with only normal bit spacing between characters.)
Page 100: Electrical Configuration Selection
BFISD 8079 They are selected by the 74LS153 data selectors that were mentioned earlier (2J and 2H). The control and data bits are available to the SCC when the SCC is selected by the local I/O address decoder (discussed in paragraph 3.2.12.4) in the Central Microprocessor Board.
Page 101 BFISD 8079 Table 3-6. Serial Port Electrical Configuration Jumper Connections PORT A: MODEM TERMINAL PRINTER Name Jumper A Cable Jumper A Cable Jumper A Cable 7 and 8 pin 5 7 and 9 pin 4 7 and 9 pin 4 3 and 4 pin 6 *1 and 3...
Page 102: Addressing And Control
BFISD 8079 In the Model 4108 Base Unit, only Port B can be configured for RS-422; although either port may be used as a synchronous data channel, it may be advantageous to use port B, because of the balanced link associated with the RS-422 config- uration.
Page 103 BFISD 8079 Table 3-7. Bit Patterns for Serial Port Configuration and Data Rate Selection DATA BUS CD03+ CD02+ CD01+ CDOO+ LOGICAL PORT CONFIGURATION Port A, Synchronous Port A, Asynchronous Port A, Split Baud Rate Port B, Synchronous Port B, Asynchronous Port B, Split Baud Rate CD07+ CD06+...
Page 104: Parallel Port
BFISD 8079 3.2.18 Parallel Port In the following paragraphs we discuss the interfacing of external devices to the Model 4108 Base Unit through the parallel I/O port. Controller circuitry to support the parallel port is contained on the Central Microprocessor Board, inside the Base Unit.
Page 105: Data Transmission To A Printer
BFISD 8079 Thus an interrupt request level 1 is encoded on the 68010 interrupt request lines (IPLO- through IPL2-). If the priority of the interrupt is greater than the current processor priority, then the interrupt processing sequence begins. The 68010 places the interrupt priority number on the lines carrying the three least significant address bits.
Page 106 BFISD 8079 Each sector contains an identifier field that appears on the data stream just before the data field. To read data, the head is first positioned at the cor- rect track, where it reads the data stream continuously. When the read/write head detects an identifier with thecorrect sector number, the data block fol- lowing that identifier is accepted.
Page 107: Centronics Protocol
BFISD 8079 Table 3-9. Centronics Protocol SIGNAL DESCRIPTION CONNECTOR (J13) PIN Data Strobe Sent by the Model 4108 Base'Unit to cause the printer to accept information on the data lines. The data lines must stabilize at least 50 nanoseconds before the Data Strobe is sent.
Page 108: Simplified Block Diagram, Cmb Floppy Disk Controller
BFISD 8079 Figure 3-12. Simplified Block Diagram, CMB Floppy Disk Controller 3-54...
Page 109: Double-Density Recording
BFISD 8079 A hard-sectored format, on the other hand, allows somewhat greater data density than does a soft-sectored. This is because no identifier field occupies space that otherwise is usable for data. However, the advantages of a soft-sectored format are many, and the double-density disk recording techniques, described in paragraph 3.2.19.2, more than compensate for the data density problem.
Page 110 BFISD 8079 The transmission rate of the Kansas City Standard can be increased by simply using fewer transitions to encode each datum. Figure 3-14(a) shows a binary 1100 sequence encoded at a transmission rate of 1200 bits/second. Here the bi- nary 0 requires one full cycle of 1200 Hz, and the binary 1 requires two cycles of 2400 Hz.
Page 111: Mfm Data Separation
BFISD 8079 Figure 3-15. Encoded Data for FM Recording Clearly, both the data transfer rate and the amount of data on the diskette now can be doubled with respect to the (single-density) FM method. To recover the data, the detector section of the disk controller circuitry generates a pulse stream equal in frequency to the data rate.
Page 112: Encoded Data For Modified Fm (Mfm) Recording
BFISD 8079 Figure 3-16. Encoded Data for Modified FM (MFM) Recording Phase Detection Data separation is enabled by the VCOE+ (VCO Enable) signal input to a 74LS51 combination gate (13X). (Refer to the CMS Logic Diagram, sheet 51.) The VCOE+ signal comes from the floppy disk controller chip and is asserted (high) when the chip is ready to transfer data to or from the diskette.
Page 113: Simplified Block Diagram, Data Separator Phase Detector Logic
BFISD 8079 A simplified and generalized block diagram of the phase detector logic is shown in figure 3-17. To help the reader to understand the phase detector logic, the block diagram contains only generic logic blocks, and all signals are positive logic (active high), regardless of their true active voltage level.
Page 114 BFISD 8079 For example, if the VCO clock pulse (via a 74LS161 synchronous 4-bit counter [15T]) toggles the flip-flop (14X) connected to it before the pulse from the diskette toggles the other flip-flop, then PUMP DOWN will produce a pulse. The pulse informs the VCO that it is generating too high a frequency, and the pulse will bring down the voltage reference going to the MC4024 VCO chip.
Page 115 BFISD 8079 Thus the error amplifier and phase detector logic circuits provide necessary corrections to the VCO frequency to ensure synchronous clocking of data bits from the diskette into the floppy disk controller chip. However, certain ac- tivity occurs during the writing of data onto the diskette that degrades the read data and that cannot adequately be compensated for by the data separator.
Page 116: Bit-Shifting
BFISD 8079 Consequently, the read head, responding to the magnetic flux lines of the re- corded data bit, sends the bit to the drive electronics as if it were repelled by the bit that will arrive after it (which is the bit to its right in figure 3-18).
Page 117: Floppy Drive Disk Control
BFISD 8079 Likewise, if the shift register gets a LATE+ command from the controller chip, then that command becomes the data bit and is shifted out of the shift register 125 nanoseconds later than the nominal write time. (The LATE+ command is gated through the 74LSOO NAND gate [13R] to input A of the shift register.) However, if both commands are inactive (low), then they are ANDed by the 74LS00 NAND gate (13R) and sent to input B of the shift register.
Page 118: Register Layout, Wd1793 Floppy Disk Controller Chip
BFISD 8079 Figure 3-19. Register Layout, WD1793 Floppy Disk Controller Chip The controller checks each ID for a match against the contents of the track and sector registers. As the disk rotates, the correct sector arrives under the head. This is indicated by a match of the ID to the track and the sector reg- isters.
Page 119: Command List, Wd1793 Floppy Disk Controller Chip
BFISD 8079 There are 11 commands available on the WD1793; they are listed in table 3-10. The Type I commands move the arm to the correct track. STEP IN and STEP OUT commands move the arm one track in or out. The STEP command moves the arm one track in the same direction as the last arm movement.
Page 120: Buffered Data Transfer
BFISD 8079 Signal HLD commands the drive to load the read/write heads. In the Model 4108 Base Unit, however, the heads are automatically loaded whenever motor power is on; so the HLD signal is sent directly to the HLT input of the floppy disk con- troller chip.
Page 121 BFISD 8079 Since the transfer of data between the system memory and the floppy disk con- troller is under program control, this method allows the shortest data transfer time. The buffer memory is a 6116 2K X 8 static RAM chip (12S), which holds data for a complete sector.
Page 122 BFISD 8079 Signal FMEMRE- (Floppy MEMory Read Enable) is the read enable for the sector buffer RAM. This signal is asserted from the 74LS139 (12W) when LCIORE- (LoCal I/O Read Enable) is active. Both FMEMWR- and FMEMRE- require MEM- (MEMory) to be asserted;...
Page 123: State Machine States
BFISD 8079 State 1 Latch buffer address (LTCHBUFADR+): latches the sector buffer addresses in two 74LS374 8-bit latches (12L and 12N). (Refer to the CMB Logic Diagram, sheet 45.) The local address bus is dis- abled from the main address bus. The BUSY- line is asserted to prevent the state machine from restarting while it is in the middle of a cycle.
Page 124: Floppy Disk Controller Section Control
BFISD 8079 Thus the floppy buffer state machine controls data flow between the floppy disk controller chip and the floppy sector buffer. When the state machine is not in control of the buffer, however, the operating system software may fill or empty it under program control, as mentioned earlier.
Page 125 BFISD 8079 It latches the control bit pattern from the byte-wide I/O data bus that deter- mines which drive is to be used (SELO-/SEL1- and MOTORONO-/MOTORON1-) and which side of the diskette in the chosen drive is to be used (SIDE-). The latch is mapped in with a write to FLOPLTCH-, at address 76XXXX (hex).
Page 126: Memory Array Board Functional Description
BFISD 8079 (The vector number [when multiplied by four] is the address in the lowest 1K bytes of main memory that contains the address of the routine that will handle the interrupt.) The content of the vector number is fetched and loaded into the 68010 program counter, and normal instruction execution commences in the interrupt service routine.
Page 127: Introduction
This section contains maintenance information for the Central Microprocessor Board (CMB), Base Unit Power Supply and peripheral controller boards contained in the Model 4108 Base Unit of the MAI® 2000 Series Desktop Computer System. Included are procedures for preventive maintenance and trouble analysis, along with a diagrammed presentation of a system power-up check and a discussion of diagnostic programs.
Page 128: Trouble Analysis
BFISD 8079 Table 4-2. Base Unit Power Supply Voltage Adjustments MEASUREMENT TEST POINT VOLTAGE ADJUSTMENT +xx.x V to +xx.x V +xx.x V to +xx.x V None +xx.x V to +xx.x V None +xx.x V to +xx.x V None TROUBLE ANALYSIS The steps that follow provide an organized, general approach toward trouble- shooting the system.
Page 129: Removal/Replacement
BFISD 8079 SECTION V REMOVAL/REPLACEMENT INTRODUCTION This section provides detailed procedures for replacing major subassemblies, and includes jumper/switch installation/settings and cable part numbers. REPLACING THE CENTRAL MICROPROCESSOR BOARD (CMB) To remove the Central Microprocessor Board, proceed as follows: Shut down the system, and turn the Base Unit power OFF. Unplug all connections to the Base Unit, including all attached peri- pherals.
Page 130 BFISD 8079 c. Push the drive slightly toward the rear of the CMB so that the flange at the bottom front of the drive clears the slot in the Base Unit bottom panel, and lift the Winchester drive chassis from the CMB.
Page 131 BFISD 8079 Figure 5-1. Location of Jumpers on Central Microprocessor Board...
Page 132 BFISD 8079 Figure 5-2. Central Microprocessor Board Cable Part Numbers...
Page 133 BFISD 8079 EPROM JUMPER C 2716 (2K x 8) 2 and 3 2732 (4K x 8) 1 and 2 Connect jumper R. (This jumper, when disconnected, disables the mem- ory refresh circuitry, thereby allowing easier debugging of memory and bus arbitration circuits. Normal operation is with jumper R connected between points 1 and 2.) Connect jumpers A, B, G, H and K according to the following tables.
Page 134 BFISD 8079 Jumper H Jumper H DCDB 1 and 2 1 and 2 Jumper K Jumper K Jumper K D422 *1 and 2 *1 and 2 *1 and 2 NOTE: Be sure to disconnect all unused jumper positions on port PORT B - RS-422: Jumper Connect...
Page 135 BFISD 8079 RAM SIZE JUMPER 2K x 8 2 and 3 8K x 8 1 and 2 Connect Jumper E. (The floppy disk controller, located on the Central Microprocessor Board, has three different data separators available: the Analog, the Standard Microsystems Corp. [SMC], and the Western Digital [WD].
Page 136: Cmb Jumper Configuration
BFISD 8079 Table 5-1. CMB Jumper Configuration JUMPER CONNECT FUNCTION 7 and 9 Serial Port A - CTS 8 and 10 Serial Port A - RTS 11 and 13 Serial Port A - RXDA 12 and 14 Serial Port A - TXDA 1 and 3 Serial Port B - DSRB 2 and 4...
Page 137 BFISD 8079 Plug the ribbon cable into the CMB. (Note: the two connectors on the CMB are situated side by side. The right-hand connector re- ceives the "0" cable; the left-hand connector receives the "1" cable. Pull the drive slightly to the front of the CMB so that the flange at the bottom of the drive chassis enters the slot in the Base Unit front panel.
Page 138: Replacing The Base Unit Power Supply
BFISD 8079 30. Plug In all connections to the Base Unit, including all previously at- tached peripherals. REPLACING THE BASE UNIT POWER SUPPLY To replace the Base Unit Power Supply, proceed as follows: Shut down the system, and turn the Base Unit power OFF. Insert a screwdriver, or similar device, into the slot at the bottom right-hand side of the Base Unit cover, and push in to disengage the...
Page 139: Replacing The Memory Array Modules
BFISD 8079 Reinstall the Base Unit Power Supply by lowering the Supply into the Base Unit, onto the CMB, and plugging the Supply into the CMB. Replace the two (2) Phillips-head screws at the bottom right-hand side of the Power Supply. Replace the rear facia by reversing the removal procedure in Step 8.
Page 140: Memory Array Module Address Switch Settings
BFISD 8079 CAUTION Do not remove these boards when power is applied to the Base Unit. 1. Shut down the system, and turn the Base Unit power OFF. 2. Insert a screwdriver, or similar device, into the slot at the bottom right-hand side of the Base Unit cover, and push in to disengage the plastic latch.
Page 141 BFISD 8079 Figure 5-3. Location of Address Switches on Memory Array Module 5-13...
Page 142: Replacing The 4-Way Controller Boards
BIFSD 8079 Reinstall the Memory Array PCBAs into the card cage at the front right-hand corner of the CMB by plugging the bottom PCBA into the CMB. (Each board may be plugged into another, and the entire stack may be installed as a unit.) Replace the Base Unit cover by lowering the cover onto the Base Unit and allowing it to "snap"...
Page 143 BFISD 8079 Table 5-3. 4-Way Controller PCBA Switch Settings SWITCH S1 DMA Arbitration PCBA Address Board 1 Board 2 Board 3 Board 4 SWITCHES PGM1-4* For PGM1 through PGM4, connect the pins according to the PCB detail used: PCB detail 904741-001 (current production) TERMINAL/PRINTER MODEM...
Page 144 BFISD 8079 Figure 5-4. Location of Switches on 4-Way Controller PCBA 5-16...
Page 145: Replacing The Winchester Drive Controller (Wdc) Board
BFISD 8079 Plug the 4-Way Controller PCBA into the CMB (or into the PCBA from which the original was removed) at the rear right-hand corner of the CMB. Replace any other boards that were removed in step 4, in the or- der recorded in that step.
Page 146: Replacing The Magnetic Cartridge Streamer Controller (Mcsc) Board
BFISD 8079 To Install the replacement Winchester Drive Controller PCBA, proceed as follows: Verify that the jumpers listed below are not installed, for normal operation. See figure 5-5 for the location of the jumpers. Jumper A to B Jumper C to D Jumper E to F Jumper...
Page 147 BFISD 8079 Figure 5-5. Location of Jumpers on the Winchester Drive Controller PCBA 5-19...
Page 148: Replacing The Winchester Drive Controller Bus Adapter Board
BFISD 8079 Insert a screwdriver, or similar device, into the slot at the bottom right-hand side of the Base Unit cover, and push in to disengage the the plastic latch. Repeat with the left-hand side, and remove the cover. Unplug the WDC Bus Adapter PCBA and the WDC PCBA (which carries the WDC PCBA) as a single unit from the top of the "stack."...
Page 149: 5-6. Location Of Switch On Magnetic Cartridge Streamer Controller Pcba
BFISD 8079 Figure 5-6. Location of Switch on Magnetic Cartridge Streamer Controller PCBA 5-21...
Page 150 BFISD 8079 CAUTION Do not remove this board when power is applied to the Base Unit. Shut down the system, and turn the Base Unit power OFF. Insert a screwdriver, or similar device, into the slot at the bottom right-hand side of the Base Unit cover, and push in to disengage the the plastic latch.
Page 151: Replacing The Local Area Network (Lan) Board
BFISD 8079 Plug the 4-pin power connector coming from the WDC Bus Adapter into J3 on the WDC PCBA. Plug the WDC Bus Adapter PCBA into the CMB (or into the PCBA from which it was removed) at the rear right-hand corner of the CMB. Replace the Base Unit cover by lowering the cover onto the Base Unit and allowing it to "snap"...
Page 152 BFISD 8079 LAN CONTROLLER (LANC) Figure 5-7. Location of Switches on Local Area Network Controller PCBA 5-24...
Page 153 BFISD 8079 The address switch comprises eight smaller switches, and each switch is set individually. The "off" position of each switch represents binary 1. SWITCH SW1 Bias Terminator Station Address ↑ ↑ ↑ ↑ ↑ ↑ * represents the "bias." Switch 1 is set to 1 (off) on only one IAN controller board in a network;...
Page 154: Replacing The Winchester Drive
BFISD 8079 SWITCH SW2 Bus Arbitration Address Decode Note: The top line is for for a single board; a second board normally is used only with diagnostics. The Local Area Network Controller board is now ready to be installed. Plug the Local Area Network Controller PCBA into the CMB (or into the PCBA from which the original LANC PCBA was removed) at the rear right- hand corner of the CMB.
Page 155 BFISD 8079 (Note: two of the drive connectors on the WDC PCBA are situated side by side; the right-hand connector [JO] receives the "0" drive cable, and the left-hand connector [Jl] receives the "1" drive cable.) Using a screwdriver, or similar tool, push back the two (2) plastic latches at the bottom rear of the Winchester Drive chassis, while lifting the back of the Drive to clear the latches.
Page 156: Replacing The Floppy Disk Drive
BFISD 8079 5.11 REPLACING THE FLOPPY DISK DRIVE To replace the floppy disk drive(s), proceed as follows: Shut down the system, and turn the Base Unit power OFF. Insert a screwdriver, or similar device, into the slot at the bottom right-hand side of the Base Unit cover, and push in to disengage the the latch.
Page 157 BFISD 8079 Connect the 4-wire power cable to the connector located at the top right-hand corner of the floppy drive chassis. Replace the front facia by reversing the removal procedure. Reinstall the Memory Array PCBAs into the card cage at the front right-hand corner of the CMB by plugging the bottom PCBA into the CMB.
Page 159: Illustrated Parts List
BFISD 8079 SECTION VI ILLUSTRATED PARTS LIST INTRODUCTION This section provides parts list information for the assemblies/subassemblies recommended for replacement at the field level. NOTE Refer to Engineering Change Notices and appropriate documents for changes to the parts list and for drawings not included.
Page 160 BFISD 8079 Figure 6-1. CMB PCBA...
Page 161 BFISD 8079 Table 6-1. CMB PCBA (MM531011) Parts List REFERENCE PART NUMBER DESCRIPTION DESIGNATION 903441-001 PCBA, CMB (MM531011) 903442-001 PCB, CMB Diagram, Schematic Capacitors 104001-002 Capac, Ceram Z5U 1000 pFD 5V 20% C125 104001-016 Capac, Ceram Z5U 0.47 MFD 50V 20% 104003-006 Capac, Ceram X7R 0.01 MFD 100V 10% C124...
Page 162 BFISD 8079 Table 6-1. CMB PCBA Parts list (continued) REFERENCE PART NUMBER DESCRIPTION DESIGNATION Integrated Circuits 101612 IC, MC1489L Quad Line Receiver 1C,3C,ID,3D 101613 IC, MC1488L Quad Line Driver 1B,3B 101615 IC, 74S08 Quad 2-Input Pos AND 7T,8Y 101624 IC, 74S20 Dual 4-Input NAND 101626 IC, SN74S37 Quad 2-Input Pos NAND Buffer 101627...
Page 163 BFISD 8079 Table 6-1. CMB PCBA Parts List (continued) REFERENCE PART NUMBER DESCRIPTION DESIGNATION Integrated Circuits 161039-001 IC, 74LS164 8-Bit Par Output Ser S/R 161053-001 IC, 74LS38 Quad 2-Input Pos NAND Buffer 161055-001 IC, 74LS221 Dual Monostable MVB 161061-001 IC, 74S299 8-Bit Univ. S/R 161064-001 IC, 74LS240 Octal Buffer/Line Driver,3-State 1K,1L,1M...
Page 164 BFISD 8079 Table 6-1. CMB PCBA Parts List (continued) REFERENCE PART NUMBER DESCRIPTION DESIGNATION Resistors 111000-031 Resis, Comp 1K Ohm 5% Rll,15,16,18,21,22, 111000-033 Resis, Comp 39K Ohm 5% 111000-052 Resis, Comp 470 Ohm 5% R46,47 111000-043 Resis, Comp 100 Ohm 5% 111000-044 Resis, Comp 120 Ohm 5% Rl,2,8,44...
Page 165 BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY...
Page 166 BFISD 8079 Figure 6-2. Memory Array 256K PCBA...
Page 167 BFISD 8079 Table 6-2. Memory Array 256K PCBA (MM531030) Parts List REFERENCE PART NUMBER DESCRIPTION DESIGNATION 903368-001 PCBA, Memory Array 256K (MM531030) 904693-001 PCB, Memory Array Diagram, Schematic Capacitors 104007-001 Capac, Ceram Z5U DIP 0.1 MFD 50V 20% C3-C49 108016-003 Capac, Alum Elect 47 MFD 10V -20+50% Cl,2 Connectors...
Page 168 BFISD 8079 Figure 6-3. WDC Bus Adapter PCBA 6-10...
Page 169 BFISD 8079 Table 6-3. WDC Bus Adapter PCBA (MM531100) Parts List REFERENCE PART NUMBER DESCRIPTION DESIGNATION 903439-001 PCBA, WDC Bus Adapter (MM531100) 904854-001 PCB, WDC Bus Adapter Diagram, Schematic Capacitors 104007-001 Capac, Ceram Z5U DIP 0.1 MFD 50V 20% C3-32 108016-004 Capac, Alum Elect 100 MFD 6V -20/+75% Cl,2...
Page 170 BFISD 8079 Table 6-3. WDC Bus Adapter PCBA Parts List (continued) REFERENCE PART NUMBER DESCRIPTION DESIGNATION Integrated Circuits 911006-008 IC, PAL WDC Controller/Host Sequencer 911009-004 IC, PAL WDC Host/Controller Sequencer Resistors 111000-029 Resis, Comp 330 Ohm 5% 119001-002 Resis Ntwk, DIP 1K Ohm 8-Pin 7 Resis Rl,2 Sockets 325005-011...
Page 171 BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6-13...
Page 172 BFISD 8079 Figure 6-4. 4-Way Controller PCBA 6-14...
Page 173 BFISD 8079 Table 6-4. 4-Way Controller PCBA (JM531040 ) Parts List REFERENCE PART NUMBER DESCRIPTION DESIGNATION 903390-001 PCBA, 4-Way Controller (MM531040) 904741-001 PCB, 4-Way Controller Diagram, Schematic Capacitors 104007-001 Capac, Ceram 250 DIP 0.1 MFD 50V 20% Cl-4 104008-004 Capac, Ceram X/R DIP 220 pFD 50V 5% C9-54 101127 Capac, Tant Sleeved 47 MFD 20V 10%...
Page 174 BFISD 8079 Table 6-4. 4-Way Controller PCBA Parts List (continued) REFERENCE PART NUMBER DESCRIPTION DESIGNATION Integrated Circuits 161086-001 IC, 74LS139 Decoder/DeMUX 161108-001 IC, RAM Static 2Kx8 CMOS 200ns 162002-002 IC, Z80A 8-Bit Micro-P 162031-001 IC, Serial Communications Controller 5F,6F 161111-001 IC, 74LS640 Octal Bus Receiver Resistors 111000-043...
Page 175 BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6-17...
Page 176 BFISD 8079 Figure 6-5. MTCS Controller PCBA 6-18...
Page 177 BFISD 8079 Table 6-5. MTCS Controller PCBA (MM531070) Parts List REFERENCE PART NUMBER DESCRIPTION DESIGNATION 903406-001 PCBA, MTCS Controller(MM531070) 904769-001 PCB, MTCS Controller Diagram, Schematic Capacitors 108016-004 Capac, Alum Elect 100 MFD 6V,-20/+75% Cl,2 101144 Capac, Ceram 0.1 MFD 50V 20% 104004-018 Capac, Ceram COG 33 pFD 50V 5% 104007-001...
Page 178 BFISD 8079 Table 6-5. MTCS Controller PCBA Parts List (continued) REFERENCE PART NUMBER DESCRIPTION DESIGNATION Integrated Circuits 161076-001 IC, 74S133 13-Input NAND 161107-002 IC, RAM Static 2Kx8 100ns 4E,4R 161111-001 IC, 74LS40 Octal Bus XCVR 161134-001 IC, 74LS34 Octal D-Reg Inv 3-State 1L,2L,1M,2M 161145-001 IC, 74LS97 Sync U/D Binary Counter...
Page 179 BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6-21...
Page 180 BFISD 8079 Figure 6-6. LAN Controller PCBA 6-22...
Page 181 BFISD 8079 Table 6-6. IAN Controller PCBA (MM531060) Parts List REFERENCE PART NUMBER DESCRIPTION DESIGNATION 903405-001 PCBA, LAN Controller (MM531060) 904773-001 PCB, IAN Controller Diagram, Schematic Capacitors 104003-008 Capac, Ceram X7R 220 pFD 100V 20% 104007-001 Capac, Ceram Z5U DIP 0.1 MFD 50V 20% C2-69,71-82,84-86 104009-002 Capac, Ceram COG DIP 47 pFD 50V 5%...
Page 182 BFISD 8079 Table 6-6. LAN Controller PCBA Parts List (continued) REFERENCE PART NUMBER EESCRIPTION EESIGNATION Integrated Circuits 161065-001 IC, 74LS374 Octal Register D-Type F/F 2H,3H,3J,4K,3L,4L, 2P,2R 161068-001 IC, 74LS244 Octal Buffer/Line Driver 1J,3K,6L,4M,4P 161074 IC, 74S244 Octal Buffer 161076-001 IC, 74S133 13-Input NAND 161085-001 IC, 7407 Hex Buffer/Driver 161137-001...
Page 183 BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6-25...
Page 184 BFISD 8079 Figure 6-7. Winchester Drive (Single-Board) Controller PCBA 6-26...
Page 185 BFISD 8079 Table 6-7. WDC Controller PCBA (MM531150) Parts List ITEM PART NUM QTY-PER HREV PART DESCRIPTION STAT REMARKS ---- ----------- -------- ---- ----------------------------------------- ---- --------------------- 0001 9O4923-001 1.000 PCB 5 1/4 DISK CONTROLLER 0003 762022-003 1.000 LABEL TAB . 375X1. 250 YEL O005 165007-001 1.000...
Page 186 BFISD 8079 Figure 6-8. Power Supply Input Module PCBA 6-28...
Page 187 BFISD 8079 Table 6-8. Power Supply Input Module (MM533000) Parts List ITEM PART NUM QTY-PER HREV PART DESCRIPTION REMARKS ---- ----------- -------- ---- ----------------------------------------- --------------------- 0001 904761-001 1.000 PCB INPUT MCOLLE 0002 762022-003 l.000 LABEL TAB .375X1.250 YEL 0001 123004-003 2.000 THERMISTOR INRUSH PROTECT 15 AMP .03 OHM R1,2...
Page 188 BFISD 8079 Table 6-8. Power Supply Input Module PCBA Parts List (continued) ITEM PART NUM QTY-PER HREV PART DESCRIPTION REMARKS ---- ----------- -------- ---- ----------------------------------------- --------------------- 0023 141021-001 2.000 TRANSISTOR NPN 2N6675 10A 450V Uit2 0027 180054-001 1.000 TRANSFORMER E?I BALUN 0028 180053-001 2.000...
Page 189 BFISD 8079 THIS PAGE LEFT BLANK INTENTIONALLY 6-31...
Page 190 BFISD 8079 Figure 6-9. Power Supply Output Module PCBA 6-32...
Page 191 BFISD 8079 Table 6-9. Power Supply Output Module PCBA (MM533000) Parts List ITEM PART NUM QTY-PER HREV PART DESCRIPTION STAT REMARKS ---- ---------- ------- ---- ----------------------------------------- ---- ---------------------- 0001 904859-001 1.000 PCB POWER SUPPLY OUTPUT MODULE 0002 762022-003 1.000 LABEL TAB . 375X1. 250 0003 116000-229 3.000...
Page 192 BFISD 8079 Table 6-9. Power Supply Output Module PCBA Parts List (continued) ITEM PART NUM QTY-PER HREV PART DESCRIPTION STAT REMARKS ---- ----------- -------- ---- ----------------------------------------- ---- ------------------------ 0063 104010-002 10.000 CAP CERAMC Z5U AXIAL .01UF 20% 100V C5,14,15,16,17,18, ,42,50,51 0066 1O4010-OO1 12.000...
Page 193 BFISD 8079 Figure 6-10. Power Supply Control Module PCBA 6-35...
Page 194 BFISD 8079 Table 6-10. Power Supply Control Module PCBA (MM533000) Parts List ITEM PART NUM QTY-PER HREV PART DESCRIPTION REMARKS ---- ----------- ------- ---- ----------------------------------------- ---------------------- 0001 904765-001 1.000 PCB CONTROL MODULE P/S 0003 762022-003 1.000 LABEL TAB .375X1.250 YEL 0004 325026-037 1.000...
Page 195: Floppy Disk Drive
Its purpose is to allow the Model 4108 Base Unit to store and retrieve blocks of data (records) onto and from a rotating disk, thus provid- ing secondary storage for the MAI® 2000 Series Computer System. The Drive functions as an input/output device in the Base Unit.
Page 196: Head Load/Interlock Mechanism
BFISD 8079 Figure 7-1. Spindle Mechanism Stepper Motor is converted into rectilinear motion, by the Pulley/Steel Belt assembly (connected directly to the Stepper Motor axle), to drive the Carriage Assembly. The Carriage Assembly consists of the Carriage, the Side 0 R/W Head, and the Side 1 R/W Head.
Page 197 BFISD 8079 Figure 7-3. Head Load/Interlock Mechanism...
Page 198: Functional Block Diagram
BFISD 8079 Analog System DC Control Circuit Erase Amplifier Circuit Read Amplifier Circuit Write Circuit Digital System Stepper Motor Control Circuit Index Ready Circuit Write Protect Circuit Head Load Solenoid Control Circuit Brief explanations of the major circuits are presented in the following par- agraphs.
Page 199: Stepper Motor Control
BFISD 8079 7.1.2.1 Stepper Motor Control The Stepper Motor is a 4-phase DC motor. The circuit in ICl controls the motor (see figure 7-5 for a block diagram of the Stepper Motor Control Circuit). The STEP signal rotates the motor 3.6 degrees (48 TPI) or 1.8 degrees (96 TPI). The rotation of the Stepper Motor is converted to linear motion of the Read/ Write Heads by the Pulley/Steel Belt assembly.
Page 200: Drive Motor Control
BFISD 8079 Figure 7-8. Stepper Motor Phase Transfer Chart 7.1.2.2 Drive Motor Control The Drive Motor is a brushless DC motor and is controlled by the PCBA of the Drive Motor itself. The Drive Motor is started and stopped by the MOTOR-ON signal (Jl, pin 16).
Page 201: Write Protect Detector
BFISD 8079 Figure 7-10. Head Load Timing Diagram Head Carriage cutting off the light to the photo switch. The TRACK 00 signal is output when the output level of the Track 00 photo switch is the same as the output level of phase A and phase C of the Stepper Motor. Figure 7-11 is a simplified schematic of the Track 00 detection circuit, and figure 7-12 and...
Page 202 BFISD 8079...
Page 203: Ready Detector
BFISD 8079 Figure 7-15. Index Detection Circuit tor, and a negative pulse of 2.5 ms to 5 ms is generated in the comparator out- put. This pulse enters the counter and, as a 4 ms pulse, is conveyed to the Central Microprocessor Board as a negative pulse when the SELECT signal is ac- tive.
Page 204: Read/Write Heads
BFISD 8079 Figure 7-18. Write Start Timing Diagram 7.1.2.9 Read/Write Heads The Read/Write Head is a tunnel erase ceramic head. The head consists of the read/write coils and the erase coil. The erase coil is excited in the write mode, and a noise prevention area is formed at both sides of a track recorded by the read/write coil.
Page 205: Write Circuit
BFISD 8079 7.1.2.10 Write Circuit The Write Circuit converts the serial data passed from the Central Microproces- sor Board into the magnetic pattern on the disk. Figure 7-18 shows the write start timing (96 TPI). Loading the heads and making the WRITE GATE signal log- ic level low causes the Drive to enter the writable status.
Page 206: Read Circuit
BFISD 8079 Figure 7-22. Erase Delay Timing Diagram write timing diagram, figure 7-21 shows the erase delay circuit (simplified), and figure 7-22 is the erase delay timing diagram. 7.1.2.11 Read Circuit Data stored on the floppy disk are recovered by the Read Circuit. Loading the heads and making the WRITE GATE signal a logic level high causes the Drive to enter the readable status.
Page 207: Read Amplifier Circuit And Filter Work
BFISD 8079 Note: It is 26 msec in the 48 T.P.I. Model. Figure 7-24. Read Start Timing Diagram of the switch is connected to the Read Amplifier Circuit. When the Drive is in the write mode, the WRITE ENABLE signal is at logic level low, and the diodes are turned off.
Page 208: Timed Main Filter And Crossover Detector
BFISD 8079 ters are coupled through an RLC network. The RLC network differentiates the input signal voltage so that the amplifier output is a differentiated version of the input signal. The output of the differential amplifier is input to the Comparator.
Page 209 BFISD 8079 arator caused by shouldering of the differentiated read data signal. When a high resolution head is used, shouldering sometimes occurs in the outer cir- cumference of the Drive. The Timed Main Filter consists of a pulse generator, a timed one-shot MV, and a timed main flip-flop. The pulse generator outputs a short pulse to trigger the timed main one-shot at every input transfer.
Page 210 BFISD 8079 capacitor value. The data passed from the Comparator is delayed by 2.2 microseconds by the timed main one-shot and loaded on the timed main flop-flop. Even if the timed one-shot is clocked by an erroneous crossover, the timed main flip-flop output does not change, because the erroneous crossover time is shorter than 2.2 microseconds.
Page 211: Dc Control Circuit
BFISD 8079 Figure 7-28 is a block diagram of the Timed Main Filter and Crossover Detector; figure 7-29 is the read timing diagram. 7.1.2.16 DC Control Circuit The DC Control Circuit is used to monitor the 5VDC and 12VCD Power Supplies. When either supply voltage deviates from the limits listed below, the write current and erase current are turned off.
Page 212 BFISD 8079 Table 7-1. Specifications PARAMETERS CHARACTERISTICS Storage Capacity Per Diskette 1 MB Per Track 6.25 KB Data Transfer Rate (bits per second) 250 K Average Latency Time 100 ms Track-to-Track Positioning Time 3 ms Average Access Time 100 ms Head Loading Time 25 ms Head Settling Time...
Page 213 BFISD 8079 Table 7-1. Specifications (continued) PARAMETERS CHARACTERISTICS Error Rates The following error rates are valid only when the drive is being used accord- ing to specifications. Media defects or equipment failures are excluded. Written data should be veri- fied as being correctly written.
Page 214: Installation And Maintenance
BFISD 8079 INSTALLATION AND MAINTENANCE This subsection contains unpacking, installation and maintenance information for the Floppy Disk Drive. 7. 2.1 Unpacking Prior to unpacking the Drive, inspect the packaged Drive to determine Aether any damage was incurred during shipment. Using shipping documents, verify that all items have been received. Open the protective shipping carton at the top.
Page 215: Index Burst Position Adjustment
BFISD 8079 Track 00 position adjustment Rotation adjustment 0-1 head gap adjustment 7.2.4.1 Index Burst Position Adjustment Load the alignment diskette, and step it to track 34. Set an an oscilloscope as follows: Channel 1 200 mV AC Channel 2 200 mV AC (inverted) Mode...
Page 216: Track 00 Position Adjustment
BFISD 8079 Mode Time Base 20 milliseconds Trigger EXTERNAL, NORMAL, NEGATIVE d. Connect the Channel 1 test probe to the Drive test point labeled CHK1; connect the Channel 2 test probe to the Drive test point labeled CHK2; connect the Trigger input to pin 49 of IC1, on the Main PCBA. Select sides 0 and 1 alternately and monitor the waveforms on both sides while moving the Stepper Motor to put the amplitude ratios (small waveform divided by large waveform) within the range prescribed...
Page 217: Rotation Adjustment
BFISD 8079 Channel 1 5V DC Channel 2 2V DC (inverted) Mode Time Base 5 milliseconds Trigger INTERNAL (CH. 2), NORMAL, NEGATIVE Connect the Channel 1 test probe to pin 54 of IC1, on the Main PCBA; connect the Channel 2 test probe to the Drive test point labeled CHK3. Step the head between track 00 and 06 alternately.
Page 218: Reference Information
BFISD 8079 REFERENCE INFORMATION This subsection provides schematics and other reference data for the Floppy Disk Drive. 7.3.1 Interface The Floppy Disk Drive interface consists of two sections: Signal Power Supply Each line is detailed below. 7.3.1.1 Signal Interface The daisy chain or radial chain is used for the signal interface of the Select line, allowing connection to a maximum of four Drives.
Page 219: Input Lines
BFISD 8079 POWER SUPPLY CONNECTOR Pin No. Power Name +12VDC +12V GND +5V GND +5VDC The signal interface lines are illustrated in figure 7-33, on the next page. 7.3.1.2 Input Lines SELECT 1-4 - A maximum of four Drives can be connected in the daisy chain mode.
Page 220: Signal Interface Lines
BFISD 8079 Figure 7-33. Signal Interface Lines 7-26...
Page 221: Output Lines
BFISD 8079 Figure 7-34. WRITE DATA Timing (FM) nal is at logic level 0. The function of this signal is to control the operation confirmation LED. SIDE SELECT - The function of this signal is to select the two read/write heads.
Page 222: Jumper Pin
BFISD 8079 READ DATA - The function of this signal is to output the raw data that was read by the read circuit of the Drive. Usually this line is at logic level 1 and becomes logic level 0 when the magnetic inversion exists on the track.
Page 223 BFISD 8079 Figure 7-37. Factory Arrangement of Jumper 7-29...
Page 224: Drive Timing Diagram
BFISD 8079 Note 1: In 48 T.P.I Model, the period is 6 ms. Note 2: In 48 T.P.I Model, the period is 26 ms. Figure 7-38. Drive Timing Diagram 7-30...
Page 225 BFISD 8079 7-31...
Page 226 BFISD 8079 7-32...
Page 227 BFISD 8079 7-33/34...
Page 229: 20 Megabyte Winchester Drive System
Its purpose is to allow the Model 4108 Base Unit to store and retrieve blocks of data (records) onto and from rotating disks, thus pro- viding storage for the MAI® 2000 Series Computer System. The Drive functions as an input/output device in the Base Unit. The Drive contains four magnetic disks and has a total data storage capability of 20.97 megabytes, formatted.
Page 230 BFISD 8079 Figure 8-1. Major Component Location...
Page 231 BFISD 8079 Figure 8-2. Head Disk Assembly...
Page 232: Functional Concepts
BFISD 8079 DC Motor and Brake - The dc motor is a brushless, two-phase external rotor motor with integral hub. Commutation is effected by a Hall sen- sor. The rotational speed of the motor is 3600 revolutions per minute (rpm). The disk hub is grounded to the Master Electronics PCBA via the motor shaft and a button contact.
Page 233: Equipment Specifications
BFISD 8079 Interface logic - The interface logic translates the input/output sig- nals of the Winchester Drive to ensure drive-to-controller signal com- patibility. Winchester Drive logic signal levels are transistor-to- transistor logic (TTL) compatible. The transmission line signals are differential signals. Read/Write Logic - To execute read or write commands, the Drive must be free of faults, and the selected head must be at the correct location on the disk (i.e., on cylinder).
Page 234 BFISD 8079 Table 8-1. Specifications (continued) PARAMETERS CHARACTERISTICS Storage Capacity Formatted Data bytes per sector Data sectors per track Data bytes per track 8,192 Capacity (megabytes) 20.97 Recording Parameters Bit density 8,900 bpi (inner track, nominal) Coding Modified-frequency-modulation (MFM) Track density 360 tracks per inch (average) Rotational Parameters Disk rotational speed...
Page 235 BFISD 8079 Table 8-1. Specifications (continued) PARAMETERS CHARACTERISTICS STORAGE TRANSIT OPERATING Temperature: -40°F to 158°F -40°F to 158°F 50°F to 122°F -40°C to 70°C -40°C to 70°C 10°C to 50°C Temperature Gradient: 27°F per hour 20°F per hour 18°F per hour 15°C per hour 15°C per hour 10°C per hour...
Page 236: Installation And Operation
BFISD 8079 INSTALLATION AND OPERATION This subsection contains unpacking, installation and checkout information for the 20 MB Winchester Drive System. 8.2.1 Unpacking Prior to unpacking the Drive, inspect the packaged Drive to determine whether any damage was incurred during shipment. Using the shipping documents, verify that all items have been received.
Page 237: System Installation
BFISD B079 8.2.5 System Installation Installation of the Winchester Drive system consists of plugging the WDC PCBA/ WDC Bus Adapter PCBA combination into the Central Microprocessor Board, in the Base Unit, and then routing the Winchester Drive cables to the WDC and the pow- er supply and connecting them.
Page 238 BFISD 8079 Table 8-3. Diagnostic and Failure Code Indicators ABNORMAL RESULT ACTION (DOT-DASH CODE) RESULT Power-Up LED flashes at 0.5 second intervals Drive After 25 seconds maximum, the LED stops flashing and remains on. Heads are at track 000 Code 1 LED displays* .
Page 239: Functional Description
BFISD 8079 FUNCTIONAL DESCRIPTION The following paragraphs describe the theory of the various electronic subsys- tems that comprise the 20 megabyte 5.25" Winchester Drive. This information provides maintenance personnel with a comprehensive understanding of the func- tions of the Drive. A brief discussion of disk recording principles is fol- lowed by a functional description of the Winchester Drive unit, explaining how...
Page 240 BFISD 8079 8-12...
Page 241: Control Lines
BFISD 8079 All heads are mounted on a carriage such that the heads and carriage move as one unit. The carriage moves the heads radially over the disks' surfaces. the heads are positioned at the same cylinder at any given time. 8.3.2 Control Lines The control data is exchanged between the Winchester Drive and the Winchester...
Page 242: Winchester Drive Controller
BFISD 8079 Table 8-4. Head Select Decode Matix LINE Head Select 0 False True False True False True False True Head Select 1 False False True True False False True True Head Select 2 False False False False True True True True Index - The...
Page 243 BFISD 8079 The simplified block diagram in figure 8-6 shows the functional organization of the WDC. Only the major areas are shown, and they are defined as follows: • Host Interface - The host interface connects the internal data bus to the WDC Bus Adapter PCBA.
Page 244: Signal Definitions
BFISD 8079 • Data Separator - The data separator converts serial TTL data to MFM for transfer to the selected Drive. It converts MFM data coming from the selected Drive to serial TTL data for the SERDES. • Sector Buffer - The sector buffer stages data transfers between the disk and the host to prevent data overuns.
Page 245: Controller - Host Handshaking
BFISD 8079 Table 8-5. SASI Bus Status Signals NAME DRV/RCVR DEFINITION I-/0 Drv OC Input-/Output: The controller drives this line. A low level on this line indicates that the controller is driving the data in on the SASI bus. A high level on this line indicates that the WDC Bus Adapter is driving the data out on the SASI bus.
Page 246: Host Bus Control Signals
BFISD 8079 Table 8-8. Host Bus Control Signals NAME DRV/RCVR DEFINITION RST- Rcvr, Reset: The WDC Bus Adapter sends this active low signal to 220/330 the WDC to force the controller WDC to the idle state. After RST- has become active, any controller status is cleared.
Page 247: Detailed Description (Handshaking And Timing)
BFISD 8079 8.3.3.2 Detailed Description (Handshaking and Timing) The following paragraphs describe the interaction between the Winchester Drive Controller (WDC) and the WDC Bus Adapter. Controller Selection - Before the WDC Bus Adapter can begin a transaction, it must select the controller. The WDC Bus Adapter selects the controller by activating the SEL- control signal and the address bit of the control- ler.
Page 248 BFISD 8079 Command Mode - The Winchester Drive Controller (WDC) receives commands from the WDC Bus Adapter using a handshaking sequence. The controller places a low level on the C-/D (Control-/Data) line to indicate that it wants a command from the WDC Bus Adapter and places a high level on the I-/0 line to indicate that the movement of information is from the Adapter to the controller.
Page 249: Programming Information
BFISD 8079 Figure 8-9. Data Transfer from Host, Timing Status Bytes - Two bytes of status are passed to the host at the end of all commands. The first byte informs the host (Central Microprocessor Board via the WDC Bus Adapter PCBA) whether any errors occurred during the execution of the command.
Page 250 BFISD 8079 8.3.3.4 Commands The host sends a six-byte block to the controller to specify the operation. This block is the Device Control Block (DCB). Figure 8-10 shows the compos- ition of the DCB. The list that follows figure 8-10 defines the bytes that make up the DCB.
Page 251 BFISD 8079 Byte 0 Bits 7, 6 and 5 identify the class of the command. Bits 4 through 0 contain the opcode of the command. Byte 1 Bits 7, 6 and 5 identify the logical unit number (LUN). Bits 4 through 0 contain logical block address 2. Byte 2 Bits 7 through 0 contain logical block address 1.
Page 252 BFISD 8079 The commands fall into eight classes, 0 through 7; only classes 0 and 1 are used. Class 0 commands are data, non-data transfer, and status com- mands. Classes 1 through 6 are reserved. Class 7 are diagnostic com- mands.
Page 253 BFISD 8079 command returns the logical address of the failing sector in bytes 1, 2 and 3. If the Request Sense Status command is issued after any of the format commands or the Check Track Format command, then the logical ad- dress returned by the controller points to one sector beyond the last track formatted, or checked, if there was no error.
Page 254: Type 0 Error Codes, Disk Drive
BFISD 8079 Table 8-10. Type 0 Error Codes, Disk Drive CODE DEFINITION The controller detected no error during execution of the previous oper- ation. The controller did not detect an index signal from the drive. The controller did not get a seek complete signal from the drive after seek operation.
Page 255: Type 2 Error Codes, Command And Miscellaneous
BFISD 8079 Table 8-12. Type 2 Error Codes, Command and Miscellaneous CODE DEFINITION Invalid Command: the controller has received an invalid command from the disk. Illegal Block Address: the controller detected an address that is be- yond the maximum range. Volume Overflow Bad Argument Invalid Logical Unit Number...
Page 256: Command
BFISD 8079 Format Unit (Class 0, Opcode 04) - This command formats all sectors with ID and data fields, according to the selected interleave factor. The con- troller will write from index to index all ID and data fields with a block size as specified by an Immediately previous Mode Select command.
Page 257 BFISD 8079 Reserved (Class 0, Opcode 05) - This opcode is not used. Reserved (Class 0, Opcode 06) - This opcode is not used. Reserved (Class 0, Opcode 07) - This opcode is not used. Read (Class 0, Opcode 08) - This command transfers to the host the spec- ified number of blocks starting at the specified logical starting block address.
Page 258 BFISD 8079 d = drive, 0 or 1 Byte 0 Byte 1 Logical Block Address Byte 2 Logical Block Address Byte 3 Logical Block Address (LSB) Byte 4 Block Count Byte 5 Seek (Class 0, Opcode OB) - This command causes the selected drive to seek to the specified starting address.
Page 259 BFISD 8079 Reserved (Class 0, Opcode 0C) - This opcode is not used. Reserved (Class 0, Opcode OD) - This opcode is not used. Reserved (Class 0, Opcode OE) - This opcode is not used. Translate (Class 0, Opcode OF) - This command performs a logical address to physical address translation and returns the physical location of the requested block address in a cylinder/head/bytes-from-index format.
Page 260 BFISD 8079 d = drive, 0 or 1 76543210 Byte 00010011 Byte OOdOOOOO Byte 00000000 Byte 00000000 Byte 00000000 Byte 00000000 Read Buffer RAM (Class 0. Opcode 14) - Read Buffer RAM will pass the host IK bytes of data from the buffer.
Page 261: Mode Select Parameter List
BFISD 8079 MODE SELECT PARAMETER LIST Byte 0 Byte 1 Byte 2 Byte 3 EXTENT DESCRIPTOR LIST Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Block Size (MSB) Byte 6 Block Size Byte 7 Block Size (LSB) Byte 0 of the Extent Descriptor List specifies the data density of the drive.
Page 262: Drive Parameter List
BFISD 8079 DRIVE PARAMETER LIST Byte 0 List Format Code == 01 Byte 1 Cylinder Count (MSB) Byte 2 Cylinder Count (LSB) Byte 3 Data Head Count Byte 4 Reduced Write Current Cylinder (MSB) Byte 5 Reduced Write Current Cylinder (LSB) Byte 6 Write Precompensation Cylinder (MSB) Byte 7...
Page 263 BFISD 8079 Reserved (Class 0, Opcode 16) - This opcode is not used. Reserved (Class 0, Opcode 17) - This opcode is not used. Reserved (Class 0, Opcode 18) - This opcode is not used. Reserved (Class 0, Opcode 19) - This opcode is not used. Mode Sense (Class 0, Opcode 1A) - This command is used to interrogate the Winchester Drive Controller parameter table to determine the specific characteristics of any disk drive currently attached.
Page 264 BFISD 8079 d = drive, 0 or 1 s = Start/Stop, 0 or 1 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Receive Diagnostic Result (Class 0, Opcode 1C) - This command sends analy- sis data to the host (Central Microprocessor Board) after completion of a SEND DIAGNOSTIC command.
Page 265 BFISD 8079 Byte 0 Data Block Length (MSB) Byte 1 Data Block Length (LSB) Byte 2 Starting Address of Dump (MSB) Byte 3 Starting Address of Dump (LSB) Byte 4 Dumped Data (xxOO) • • • Byte 103 Dumped Data (xxFF) Send Diagnostic (Class 0, Opcode 1D) - This command sends data to the con- troller to specify diagnostic tests for controller and peripheral vmits.
Page 266 BFISD 8079 diagnostic specified. Therefore, a Patch RAM operation with a third byte of Al (hex) will overwrite an area of RAM starting with 80A1 (hex). The fourth byte gives the number of bytes to be overwritten. This can range from 1 to 256, with a zero yielding 256. the data block for the Send Diagnostic Command is as follows.
Page 267 BFISD 8079 Reserved (Class 0, Opcode 1E) - This opcode is not used. Reserved (Class O, Opcode 1F) - This opcode is not used. Reserved (Class 1, Opcode 20) - This opcode is not used. Reserved (Class 1, Opcode 21) - This opcode is not used. Reserved (Class 1, Opcode 22) - This opcode is not used.
Page 268 BFISD 8079 Reserved (Class 1, Opcode 26) - This opcode is not used. Reserved (Class 1, Opcode 27) - This opcode is not used. Reserved (Class 1, Opcode 28) - This opcode is not used. Reserved (Class 1, Opcode 29) - This opcode is not used. Reserved (Class 1, Opcode 2A) - This opcode is not used.
Page 269 BFISD 8079 d = drive, 0 or Byte 0 Byte 1 Byte 2 Logical Block Address (MSB) Byte 3 Logical Block Address Byte 4 Logical Block Address Byte 5 Logical Block Address (LSB) Byte 6 Byte 7 Number of Blocks Byte 8 Number of Blocks Byte 9...
Page 270 BFISD 8079 d = drive, 0 or i = invert, 0 or 1 Byte 0 Byte 1 Byte 2 Logical Block Address (MSB) Byte 3 Logical Block Address Byte 4 Logical Block Address Byte 5 Logical Block Address (LSB) Byte 6 Byte 7 Number of Blocks Byte 8...
Page 271: Search Command Argument
BFISD 8079 SEARCH COMMAND ARGUMENT Byte 0 Record Size (MSB) Byte 1 Record Size Byte 2 Record Size Byte 3 Record Size (LSB) Byte 4 First Record Offset (MSB) Byte 5 First Record Offset Byte 6 First Record Offset Byte 7 First Record Offset (LSB) Byte 8...
Page 272: Maintenance
BFISD 8079 SEARCH COMMAND ARGUMENT REQUIRED DATA BYTES PARAMETER 0 to 3 Record Size (bytes) - This must equal the blocksize or zero. Zero will be taken to mean the format blocksize. 4 to 7 First Record Offset (bytes) - This must be zero. 8 to 11 Number of Records - This must be less than or equal to the number of blocks specified in the command and...
Page 273: Power-Up Sequence Error Codes
BFISD 8079 The Power On LED is used to flash error messages when fault conditions occur in the Drive. A 4-bit binary code is used (long flash = logic 1; short flash = logic 0) with the most significant bit occuring first (e.g., short, short, long, long = 0011 = Table 8-14.
Page 274: Operational Error Check
BFISD 8079 involves checking for the data burst on track 3, if it cannot be located in track 2. link B is present, failure to complete this operation re- sults in fault code 1 (but not when link B is cut). The actuator then is positioned on track 00, and a final check is made on the motor speed.
Page 275 BFISD 8079 Table 8-16. Fault Diagnostics FAULT PROBABLE CAUSE CORRECTIVE ACTION CODE Fault in data burst detection Replace Master Electronics PCBA circuitry Fault in head 0 or preamp Replace the preamp PCBA PCBA (not recommended) Transit lock label not removed Remove Connector fault between Motor Check connector or replace PCBA...
Page 276: Removal And Replacement Procedures
BFISD 8079 In practice, however, the most likely sources of trouble are (a) power supplies out of tolerance and (b) step rates out of the Drive constraints. In any case, the following should be verified: connectors are clean and properly attached. Link A is removed for the 3.1-millisecond to 8.0-millisecond range.
Page 277 BFISD 8079 Figure 8-12. Winchester Drive Assembly 8-49...
Page 278 BFISD 8079 Figure 8-13. Head Disk Disassembly 8-50...
Page 279: Brack Removal And Replacement
BFISD 8079 Remove the front facia by removing two (2) top and two (2) bottom mounting screws (Phillips head). See figure 8-13. Using the Allen hex drive, remove the six (6) screws securing the Master Electronics PCBA to the Drive. Carefully loosen connector J4 from the Preamplifier PCBA, and remove the Master Electronics PCBA.
Page 280: Motor Control Pcba Removal And Replacement
BFISD 8079 8.5.3 Motor Control PCBA Removal and Replacement Remove the Master Electronics PCBA, as described in paragraph 8.5.1. Disconnect brake connector J6, dc motor connector J9 and stepper motor connector J8 from the Motor Speed Control PCBA. Unscrew both the rear standoff with ground tab and left standoff; re- move the Motor Speed Control PCBA.
Page 281 BFISD 8079 Motor Speed Control PCBA Schematic 3-53...
Page 282 BFISD 8079 Master Electronics PCBA Schematic (1 of 4) 3-54...
Page 283 BFISD 8079 Master Electronics PCBA Schematic (2 of 4) 8-55...
Page 284 BFISD 8079 Master Electronics PCBA Schematic (3 of 4) 8-56...
Page 285 BFISD 8079 Master Electronics PCBA Schematic (4 of 4) 8-57...
Page 286 BFISD 8079 Motor Speed Control PCBA Layout 8-58...
Page 287 BFISD 8079 Master Electronics PCBA Layout 8-59/60...
Page 289: 50 Megabyte Winchester Drive System
Its purpose is to allow the Model 4108 Base Unit to store and retrieve locks of data (records) onto and from rotating disks, thus providing storage for the MAI® 2000 Series Computer System. The drive functions as an input/out- put device in the Base Unit.
Page 290: Functional Concepts
BFISD 8079 DC Motor and Brake - The dc motor is a brushless, direct-coupled , two- phase external rotor motor with integral hub. Commutation is effected by three Hall-effect sensors mounted within the drive motor assembly. The rotational speed of the motor is 3600 revolutions per minute (rpm). The disk hub is grounded to the Device Electronics PCBA via the motor shaft and a button contact.
Page 291: Equipment Specifications
BFISD 8079 Interface logic - The drive interface logic translates the input/output signals of the Winchester Drive to ensure drive-to-controller signal compatibility. Drive I/O logic signal levels are transistor-transistor logic (TTL) compatible. The transmission line signals are differential signals. Read/Write Logic - To execute read or write commands, the drive must be free of faults, and the selected head must be at the correct location on the disk (i.e., "on cylinder").
Page 292 BFISD 8079 Table 9-1. Specifications (continued) PARAMETERS CHARACTERISTICS Storage Capacity Formatted (33 sectors) Data bytes per sector Data bytes per track 8,448 Capacity (megabytes) 42.07 MBytes per surface 7.01 Recording Parameters Bit density 9,077 bpi (inner track, nominal) Coding Modified-frequency-modulation (MFM) Track density 960 tracks per inch (average)
Page 293 BFISD 8079 Table 9-1. Specifications (continued) PACKAGED UNPACKAGED OPERATING Temperature: -40°F to 149°F -40°F to 149°F 50°F to 115°F -40°C to 65°C -40°C to 65°C 10°C to 46°C Temperature Gradient: 43.2°F per hour 43.2°F per hour 3.6°F per 5 minutes 24°C per hour 24°C per hour 2°C per 5 minutes...
Page 294: Installation And Operation
BFISD 8079 INSTALLATION AND OPERATION This subsection contains unpacking, installation and checkout information for the 50 Megabyte Winchester Disk Drive. 9.2.1 Unpacking Prior to unpacking the drive, inspect the packaged drive to determine whether any damage was incurred during shipment. Using the shipping documents, verify that all items have been received.
Page 295: Power And Interface Cables And Connectors
BFISD 8079 9.2.5 Power and Interface Cables and Connectors Electrical interface between the 50 Megabyte Winchester Drive and the WDC PCBA is accomplished via four connectors: Jl, J2, J3 and J4. The connectors and their mating connectors are shown in figure 9-2. The signal interface connection is made through connectors Jl and J2 on the Device Electronics PCBA.
Page 296 BFISD 8079 Table 9-2. Control Signal Connector Jl Pin Assignments Jl CONNECTOR PIN Signal Ground SIGNAL NAME SOURCE Reserved Head Select 2* Write Gate* Seek Complete* Drive Track 00* Drive Write Fault* Drive Head Select 0* Reserved — Head Select 1* Index* Drive Ready*...
Page 297: Dc Power Connector J3 Pin Assignments
BFISD 8079 Table 9-3. Data Transfer Connector Pin Assignments J2 CONNECTOR PIN Signal Ground SIGNAL NAME SOURCE Drive Selected* Drive Reserved — Reserved — Reserved — Reserved — Ground — Ground — MFM Write Data+ — MFM Write Data- — Ground —...
Page 298: Installation Of The Winchester Drive And The Wdc Pcba
BFISD 8079 Figure 9-3. Drive Address Jumpers and Interface Terminator 9.2.7 Installation of the Winchester Drive and the WDC PCBA To install the 50 Megabyte Winchester Drive system, proceed as follows: Turn the Base Unit power OFF. Insert a screwdriver, or similar device, into the slot at the bottom right-hand side of the Base Unit cover, and push in to disengage the the plastic latch.
Page 299 BFISD 8079 Examine the new WDC PCBA and verify that the jumpers listed below are not installed, for normal operation. See figure 9-4 for the location of the jumpers. Jumper A to B Jumper Jumper 0 to P Jumper C to D Jumper If the WDC PCBA is already attached to the WDC Bus Adapter PCBA, con- tinue with step 12.
Page 300 BFISD 8079 Figure 9-4. Location of Jumpers on the Winchester Drive Controller PCBA 9-12...
Page 301: Operation
BFISD 8079 Replace the front facia by reversing the removal procedure. Reinstall the Memory Array PCBAs into the card cage at the front right-hand corner of the CMB by plugging the bottom PCBA into the CMB. (The entire stack may be reinstalled as a unit.) Replace the Base Unit cover by lowering the cover onto the Base Unit and allowing it to snap into place.
Page 302: Functional Description
BFISD 8079 FUNCTIONAL INSCRIPTION The following paragraphs describe the theory of the various electronic subsys- tems that comprise the 50 Megabyte 5.25" Winchester Drive. This information provides maintenance personnel with a comprehensive understanding of the func- tions of the drive. A brief discussion of disk recording principles is followed by a functional description of the Winchester Drive unit, explaining how the drive interfaces with the Winchester Drive Controller.
Page 303 BFISD 8079 9-15...
Page 304: Control Lines
BFISD 8079 9.3.2 Control Lines The control data is exchanged between the Winchester Drive and the Winchester Drive Controller board (WDC), on the Central Microprocessor Board, via a con- trol cable. The following paragraphs define each control line interface sig- nal.
Page 305 BFISD 8079 Figure 9-8. Index Timing Table 9-6. Head Select Decode Matix LINE Head Select 0 False True False True False True Head Select 1 False False True True False False Head Select 2 False False False False True True Index - The Index signal is a 200-microsecond output pulse used to mark a fixed reference point relative to the disk.
Page 306: Winchester Drive Controller
BFISD 8079 prior to each seek. Once the first step pulse is received, the drive im- mediately begins seeking. Additional pulses received before completion of the seek are buffered into the counter, and the heads move at a rate pro- portional to the Step pulse count.
Page 307: Signal Definitions
BFISD 8079 • SERDES - The serializer/deserializer (SERDES) converts parallel data from the internal data bus to serial data for transfer to a selected Drive. converts serial data from the selected Drive to parallel data, which it places on the internal data bus. •...
Page 308 Table 9-7. SASI Bus Status Signals NAME DRV/RCVR DEFINITION I-/0 Drv OC Input-/0utput: The controller drives this line. A low level on this line indicates that the controller is driving the data in on the SASI bus. A high level on this line indicates that the WDC Bus Adapter is driving the data out on the SASI bus.
Page 309: Host Bus Control Signals
BFISD 8079 Table 9-10. Host Bus Control Signals NAME DRV/RCVR DEFINITION RST- Rcvr, Reset: The WDC Bus Adapter sends this active low signal to 220/330 the WDC to force the controller WDC to the idle state. After RST- has become active, any controller status is cleared.
Page 310: Detailed Description (Handshaking And Timing)
BFISD 8079 9.3.3.2 Detailed Description (Handshaking and Timing) The following paragraphs describe the interaction between the Winchester Drive Controller (WDC) and the WDC Bus Adapter. Controller Selection - Before the WDC Bus Adapter can begin a transaction, it must select the controller. The WDC Bus Adapter selects the controller by activating the SEL- control signal and the address bit of the control- ler.
Page 311: Data Transfer To Host, Timing
BFISD 8079 Command Mode - The Winchester Drive Controller (WDC) receives commands from the WDC Bus Adapter using a handshaking sequence. The controller places a low level on the C-/D (Control-/Data) line to indicate that it wants a command from the WDC Bus Adapter and places a high level on the I-/0 line to indicate that the movement of information is from the Adapter to the controller.
Page 312: Programming Information
BFISD 8079 Figure 9-12. Data Transfer from Host, Timing Status Bytes - Two bytes of status are passed to the host at the end of all commands. The first byte informs the host (Central Microprocessor Board via the WDC Bus Adapter PCBA) whether any errors occurred during the execution of the command.
Page 313: Commands
BFISD 8079 9.3.3.4 Commands The host sends a six-byte block to the controller to specify the operation. This block is the Device Control Block (DCB). Figure 9-13 shows the composi- tion of the DCB. The list that follows figure 9-13 defines the bytes that make up the DCB.
Page 314 BFISD 8079 Byte 0 Bits 7, 6 and 5 identify the class of the command. Bits 4 through 0 contain the opcode of the command. Byte 1 Bits 7, 6 and 5 identify the logical unit number (LUN). Bits 4 through 0 contain logical block address 2. Byte 2 Bits 7 through 0 contain logical block address 1.
Page 315 BFISD 8079 The commands fall into eight classes, 0 through 7; only classes 0 and 1 are used. Class 0 commands are data, non-data transfer, and status commands. Classes 1 through 6 are reserved. Class 7 are diagnostic commands. Each command is described below. The description includes its class, opcode and format.
Page 316 BFISD 8079 If the Request Sense Status command is issued after any of the format commands or the Check Track Format command, then the logical address returned by the controller points to one sector beyond the last track formatted, or checked, if there was no error. If there was an error, then the address returned points to the track in error.
Page 317: Type 0 Error Codes, Disk Drive
BFISD 8079 Table 9-12. Type 0 Error Codes, Disk Drive CODE DEFINITION controller detected no error during execution of the previous oper- ation. controller did not detect an index signal from the drive. The controller did not get a seek complete signal from the drive after seek operation.
Page 318: Type 2 Error Codes, Command And Miscellaneous
BFISD 8079 Table 9-14. Type 2 Error Codes, Command and Miscellaneous CODE DEFINITION Invalid Command: the controller has received an invalid command from the disk. Illegal Block Address: the controller detected an address that is be- yond the maximum range. Volume Overflow Bad Argument Invalid Logical Unit Number...
Page 319 BFISD 8079 Format Unit (Class 0, Opcode 04) This command formats all sectors with ID and data fields, according to the selected interleave factor. The con- troller will write from index to index all ID and data fields with a block size as specified by an immediately previous Mode Select command.
Page 320 BFISD 8079 Reserved (Class 0, Opcode 05) - This opcode is not used. Reserved (Class 0, Opcode 06) - This opcode is not used. Reserved (Class 0, Opcode 07) - This opcode is not used. Read (Class 0, Opcode 08) - This command transfers to the host the spec- ified number of blocks starting at the specified logical starting block address.
Page 321 BFISD 8079 d = drive, 0 or 1 Byte 0 Byte 1 Logical Block Address Byte 2 Logical Block Address Byte 3 Logical Block Address (LSB) Byte 4 Block Count Byte 5 Seek (Class 0, Opcode OB) - This command causes the selected drive to seek to the specified starting address.
Page 322 BFISD 8079 Reserved (Class 0, Opcode 0C) - This opcode is not used. Reserved (Class 0, Opcode OD) - This opcode is not used. Reserved (Class 0, Opcode 0E) - This opcode is not used. Translate (Class0, Opcode 0F) - This command performs a logical address to physical address translation and returns the physical location of the requested block address in a cylinder/head/bytes-from-index format.
Page 323 BFISD 8079 drives 0 or 1 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Read Buffer RAM (Class 0, Opcode 14) - Read Buffer RAM will pass the host 1K bytes of data from the buffer. It is intended for RAM diagnostic pur- poses.
Page 324 BFISD 8079 Table 9-16. Mode Select Parameter List Byte 0 Byte 1 Byte 2 Byte 3 Byte 0 of the Extent Descriptor List (shown in table 9-17) specifies the data density of the drive. The Winchester Drive Controller supports only MFM, and a value of 00 is required in this byte.
Page 325 BFISD 8079 Table 9-17. Extent Descriptor List Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Block Size (MSB) Byte 6 Block Size Byte 7 Block Size (LSB) Table 9-18. Drive Parameter List Byte List Format Code == 01 Byte Cylinder Count (MSB) Byte...
Page 326 BFISD 8079 The Step Pulse Output Rate Code specifies the timing of seek steps. Three options are available: = non-buffered, 3 ms; 01 = buffered, 0.028 ms; 02 = buffered, 0.012 ms. Reserved (Class 0, Opcode 16) - This opcode is not used. Reserved (Class 0, Opcode 17) - This opcode is not used.
Page 327 BFISD 8079 d = drive, 0 or s = Start/Stop, 0 or 1 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Receive Diagnostic Result (Class 0, Opcode 1C) - This command sends analy- sis data to the host (Central Microprocessor Board) after completion of a SEND DIAGNOSTIC command.
Page 328 BFISD 8079 Byte 0 Data Block Length (MSB) Byte 1 Data Block Length (LSB) Byte 2 Starting Address Dump (MSB) Byte 3 Starting Address Dump (LSB) Byte 4 Dumped Data (xxOO) • • Byte 103 Dumped Data (xxFF) Send Diagnostic (Class 0, Opcode 1D) - This command sends data to the con- troller to specify diagnostic tests for controller and peripheral units.
Page 329 diagnostic specified. Therefore, a Patch RAM operation with a third byte of A1 (hex) will overwrite an area of RAM starting with 80A1 (hex). The fourth byte gives the number of bytes to be overwritten. This can range from 1 to 256, with a zero yielding 256. the data block for the Send Diagnostic Command is as follows.
Page 330 BFISD 8079 Reserved (Class 0, Opcode 1E) - This opcode is not used. Reserved (Class 0, Opcode 1F) - This opcode is not used. Reserved (Class 1, Opcode 20) - This opcode is not used. Reserved (Class 1, Opcode 21) - This opcode is not used. Reserved (Class 1, Opcode 22) - This opcode is not used.
Page 331 BFISD 8079 Reserved (Class 1, Opcode 26) - This opcode is not used. Reserved (Class 1, Opcode 27) - This opcode is not used. Reserved (Class 1, Opcode 28) - This opcode is not used. Reserved (Class 1, Opcode 29) - This opcode is not used. Reserved (Class 1, Opcode 2A) - This opcode is not used.
Page 332 BFISD 8079 d = drive, Byte 0 Byte 1 Byte 2 Logical Block Address (MSB) Byte 3 Logical Block Address Byte 4 Logical Block Address Byte 5 Logical Block Address (LSB) Byte 6 Byte 7 Number of Blocks Byte 8 Number of Blocks Byte 9 Reserved (Class 1, Opcode 30) - This opcode is not used.
Page 333 BFISD 8079 drive, 0 or 1 invert, 0 or 1 Byte 0 Byte 1 Byte 2 Logical Block Address (MSB) Byte 3 Logical Block Address Byte 4 Logical Block Address Byte 5 Logical Block Address (LSB) Byte 6 Byte 7 Number of Blocks Byte 8 Number of Blocks...
Page 334 BFISD 8079 Table 9-19. Search Command Argument Byte 0 Record Size (MSB) Byte 1 Record Size Byte 2 Record Size Byte 3 Record Size (LSB) Byte 4 First Record Offset (MSB) Byte 5 First Record Offset Byte 6 First Record Offset Byte 7 First Record Offset...
Page 335 BFISD 8079 Table 9-20. Search Command Argument Required Data BYTES PARAMETER 0 to 3 Record Size (bytes) - This must equal blocksize or zero. Zero will be taken to mean the format blocksize. 4 to 7 First Record Offset (bytes) - This must be zero. 8 to 11 Number of Records - This...
Page 337 BFISD 8079 SECTION X REFERENCE DATA FIGURE TITLE PAGE 10-1 PCBA, Central Microprocessor Board 10-2 10-2 Logic Diagram, Central Microprocessor Board (59 drawings) 10-3 10-1...
Page 338: Pcba, Central Microprocessor Board
BFISD 8079 PCBA, Central Microprocessor Board Figure 10-1. PCBA, Central Microprocessor Board 10-2...
Page 339 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 1 of 58) 10-3...
Page 340 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 2 of 58) 10-4...
Page 341 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 3 of 58) 10-5...
Page 342 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 4 of 58) 10-6...
Page 343 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 5 of 58) 10-7...
Page 344 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 6 of 58) 10-8...
Page 345 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 7 of 58) 10-9...
Page 346 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 8 of 58) 10-10...
Page 347 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 9 of 58) 10-11...
Page 348 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 10 of 58) 10-12...
Page 349 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 11 of 58) 10-13...
Page 350 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 12 of 58) 10-14...
Page 351 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 13 of 58) 10-15...
Page 352 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 14 of 58) 10-16...
Page 353 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 15 of 58) 10-17...
Page 354 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 16 of 58) 10-18...
Page 355 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 17 of 58) 10-19...
Page 356 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 18 of 58) 10-20...
Page 357 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 19 of 58) 10-21...
Page 358 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 20 of 58) 10-22...
Page 359 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 21 of 58) 10-23...
Page 360: Logic Diagram, Central Microprocessor Board
BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 22 of 58) 10-24...
Page 361 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 23 of 58) 10-25...
Page 362 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 24 of 58) 10-26...
Page 363 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 25 of 58) 10-27...
Page 364 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 26 of 58) 10-28...
Page 365 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 27 of 58) 10-29...
Page 366 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 28 of 5) 10-30...
Page 367 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 28.1 of 58) 10-31...
Page 368 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 29 of 58) 10-32...
Page 369 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 30 of 58) 10-33...
Page 370 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 31 of 58) 10-34...
Page 371 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 32 of 58) 10-35...
Page 372 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 33 of 58) 10-36...
Page 373 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 34 of 58) 10-37...
Page 374 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 35 of 58) 10-38...
Page 375 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 36 of 58) 10-39...
Page 376 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 37 of 58) 10-40...
Page 377 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 38 of 58) 10-41...
Page 378 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 39 of 58) 10-42...
Page 379 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 40 of 58) 10-43...
Page 380 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 41 of 58) 10-44...
Page 381 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 42 of 58) 10-45...
Page 382 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 43 of 58) 10-46...
Page 383 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 44 of 58) 10-47...
Page 384 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 45 of 58) 10-48...
Page 385 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 46 of 58) 10-49...
Page 386 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 47 of 58) 10-50...
Page 387 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 48 of 58) 10-51...
Page 388 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 49 of 58) 10-52...
Page 389 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 50 of 58) 10-53...
Page 390 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 51 of 58) 10-54...
Page 391 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 52 of 58) 10-55...
Page 392 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 53 of 58) 10-56...
Page 393 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 54 of 58) 10-57...
Page 394 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 55 of 58) 10-58...
Page 395 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 56 of 58) 10-59...
Page 396 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 57 of 58) 10-60...
Page 397 BFISD 8079 Figure 10-2. Logic Diagram, Central Microprocessor Board (Sheet 58 of 58) 10-61/62...
Page 399 BFISD 8079 Memory Array PCBA Figure 10-3. Logic Diagram, Memory Array PCBA, 903369 Rev. A (Sht. 1 of 9) 10-63...
Page 400 BFISD 8079 Figure 10-3. Logic Diagram, Memory Array PCBA, 903369 Rev. A (Sht. 2 of 9) 10-64...
Page 401 BFISD 8079 Figure 10-3. Logic Diagram, Memory Array PCBA, 903369 Rev. A (Sht. 3 of 9) 10-65...
Page 402 BFISD 8079 Figure 10-3. Logic Diagram, Memory Array PCBA, 903369 Rev. A (Sht. 4 of 9) 10-66...
Page 403 BFISD 8079 Figure 10-3. Logic Diagram, Memory Array PCBA, 903369 Rev. A (Sht. 5 of 9) 10-67...
Page 404 BFISD 8079 Figure 10-3. Logic Diagram, Memory Array PCBA, 903369 Rev. A (Sht. 6 of 9) 10-68...
Page 405 BFISD 8079 Figure 10-3. Logic Diagram, Memory Array PCBA, 903369 Rev. A (Sht. 7 of 9) 10-69...
Page 406 BFISD 8079 Figure 10-3. Logic Diagram, Memory Array PCBA, 903369 Rev. A (Sht. 8 of 9) 10-70...
Page 407 BFISD 8079 Figure 10-3. Logic Diagram, Memory Array PCBA, 903369 Rev. A (Sht. 9 of 9) 10-71/72...
Page 409 BFISD 8079 Winchester Disk Controller Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 1 of 15) 10-73...
Page 410 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 2 of 15) 10-74...
Page 411 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 3 of 15) 10-75...
Page 412 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 4 of 15) 10-76...
Page 413 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 5 of 15) 10-77...
Page 414 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 6 of 15) 10-78...
Page 415 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 7 of 15) 10-79...
Page 416 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 8 of 15) 10-80...
Page 417 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 9 of 15) 10-81...
Page 418 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 10 of 15) 10-82...
Page 419 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 11 of 15) 10-83...
Page 420 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 12 of 15) 10-84...
Page 421 PAGE MISSING This Page was misprinted in my original documentation, is was page 10-85 and 10-87 printed on one page 10-85...
Page 422 PAGE MISSING This Page was misprinted in my original documentation, is was page 10-85 and 10-63 printed on one page 10-86...
Page 423 BFISD 8079 Figure 10-4. Logic Diagram, Winchester Disk Controller PCBA, 903461 Rev. C (Sht. 15 of 15) 10-87/88...
Page 425 BFISD 8079 4-Way Controller Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 1 of 10) 10-89...
Page 426 BFISD 8079 Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 2 of 10) 10-90...
Page 427 BFISD 8079 Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 3 of 10) 10-91...
Page 428 BFISD 8079 Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 4 of 10) 10-92...
Page 429 BFISD 8079 Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 5 of 10) 10-93...
Page 430 BFISD 8079 Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 6 of 10) 10-94...
Page 431 BFISD 8079 Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 7 of 10) 10-95...
Page 432 BFISD 8079 Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 8 of 10) 10-96...
Page 433 BFISD 8079 Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 9 of 10) 10-97...
Page 434 BFISD 8079 Figure 10-5. Logic Diagram, 4-Way Controller PCBA, 903391 Rev. E (Sht. 10 of 10) 10-98...
Page 435 BFISD 8079 Local Area Network Controller Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 2 of 20) 10-99...
Page 436 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 3 of 20) 10-100...
Page 437 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 4 of 20) 10-101...
Page 438 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 5 of 20) 10-102...
Page 439 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 6 of 20) 10-103...
Page 440 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 7 of 20) 10-104...
Page 441 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 8 of 20) 10-105...
Page 442 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 9 of 20) 10-106...
Page 443 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 10 of 20) 10-107...
Page 444 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 11 of 20) 10-108...
Page 445 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 12 of 20) 10-109...
Page 446 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 13 of 20) 10-110...
Page 447 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 14 of 20) 10-111...
Page 448 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 15 of 20) 10-112...
Page 449 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 16 of 20) 10-113...
Page 450 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 17 of 20) 10-114...
Page 451 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 18 of 20) 10-115...
Page 452 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 19 of 20) 10-116...
Page 453 BFISD 8079 Figure 10-6. Logic Diagram, Local Area Network Controller PCBA 903410 Rev. C (Sht. 20 of 20) 10-117/118...
Page 455 BFISD 8079 Magnetic Cartridge Streamer Controller Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (2 of 24) 10-119...
Page 456 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (3 of 24) 10-120...
Page 457 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (4 of 24) 10-121...
Page 458 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (5 of 24) 10-122...
Page 459 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (6 of 24) 10-123...
Page 460 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (7 of 24) 10-124...
Page 461 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (8 of 24) 10-125...
Page 462 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (9 of 24) 10-126...
Page 463 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (10 of 24) 10-127...
Page 464 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (11 of 24) 10-128...
Page 465 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (12 of 24) 10-129...
Page 466 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (13 of 24) 10-130...
Page 467 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (14 of 24) 10-131...
Page 468 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (15 of 24) 10-132...
Page 469 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (16 of 24) 10-133...
Page 470 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (17 of 24) 10-134...
Page 471 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (18 of 24) 10-135...
Page 472 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (19 of 24) 10-136...
Page 473 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (20 of 24) 10-137...
Page 474 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (21 of 24) 10-138...
Page 475 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (22 of 24) 10-139...
Page 476 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (23 of 24) 10-140...
Page 477 BFISD 8079 Figure 10-7. Logic Diagram, Magnetic Cartridge Streamer Controller PCBA 903427 Rev. A (24 of 24) 10-141/142...
Page 479 BFISD 8079 Power Supply Input Module Figure 10-8. Logic Diagram, Power Supply Input Module PCBA, 903443 Rev. E (Sht. 1 of 1) 10-143/144...
Page 481 BFISD 8079 Power Supply Output Module Figure 10-9. Logic Diagram, Power Supply Output Module PCBA, 903446, Rev. B (Sht. 2 of 6) 10-145...
Page 482 BFISD 8079 Figure 10-9. Logic Diagram, Power Supply Output Module PCBA, 903446, Rev. B (Sht. 3 of 6) 10-146...
Page 483 BFISD 8079 Figure 10-9. Logic Diagram, Power Supply Output Module PCBA, 903446, Rev. B (Sht. 4 of 6) 10-147...
Page 484 BFISD 8079 Figure 10-9. Logic Diagram, Power Supply Output Module PCBA, 903446, Rev. B (Sht. 5 of 6) 10-148...
Page 485 BFISD 8079 Figure 10-9. Logic Diagram, Power Supply Output Module PCBA, 903446, Rev. B (Sht. 6 of 6) 10-149/150...
Page 487 BFISD 8079 Power Supply Control Module Figure 10-10. Logic Diagram, Power Supply Control Module PCBA, 903404, Rev. A (Sht. 2 of 3) 10-151...
Page 488 BFISD 8079 Figure 10-10. Logic Diagram, Power Supply Control Module PCBA, 903404, Rev. A (Sht. 3 of 3) 10-152...

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