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LSI L64777 Technical Manual

Dvb qam modulator
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L64777
DVB QAM Modulator
Technical Manual
June 2000
Order Number I14031.A

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Summary of Contents for LSI L64777

  • Page 1 L64777 DVB QAM Modulator Technical Manual June 2000 Order Number I14031.A...
  • Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
  • Page 3 Preface This book is the primary reference and technical manual for the L64777 DVB QAM Modulator. It contains a complete functional description for the L64777 and includes complete physical and electrical specifications for the L64777. Audience This document assumes that you have some familiarity with digital video broadcasting, QAM modulators, and related support devices.
  • Page 4 • Chapter 6, Specifications, presents the electrical and timing specifications for the L64777. It also presents the pinout and packaging information. • Appendix A, Programming the L64777 in Serial Host Interface Mode, discusses how to program the L64777 internal registers and data tables in serial host interface mode.

  • Page 5: Table Of Contents

    Contents Chapter 1 Introduction Overview Operating Environment Chapter 2 Modulator Architecture Introduction PLL Modes 2.2.1 PLL Mode 1 2.2.2 PLL Mode 2 2.3.1 Input 2.3.2 Output Signals 2.3.3 Control Interface 2.3.4 Serial Microprocessor Interface 2-10 Input Synchronization 2-10 2.4.1 Sync Acquisition Phase 2-13 2.4.2 Sync Tracking Phase...
  • Page 6 2.11.1 Filter Setup Procedure 2-29 2.11.2 Example 2-30 2.11.3 Default Filter Characteristics 2-34 2.12 Global Control and PLL Module 2-34 2.12.1 Numerically Controlled Oscillator (NCO) 2-35 2.12.2 Acquisition Phase Using the Frequency Measurement Unit 2-36 2.12.3 Autoacquisition Mode 2-38 2.12.4 Regulation Phase 2-39 2.13...
  • Page 7 Chapter 6 Specifications AC/DC Specifications 6.1.1 Electrical Ratings 6.1.2 AC Timing Diagrams for L64777 Pin Descriptions and Lists 6.2.1 L64777 Electrical Pin Descriptions 6.2.2 Numerical Pin List for the L64777 6.2.3 Alphabetic Pin List for the L64777 Package Pinout 6-10 Contents...
  • Page 8 Appendix A Programming the L64777 in Serial Host Interface Mode Serial Bus Protocol Overview Programming the Slave Address Using the Serial Bus Interface Write Cycle Using the Serial Bus Interface Read Cycle Using the Serial Bus Interface Limitations Appendix B...
  • Page 9 Quick Overview of the Serial Bus Serial Bus Write/Read Cycle General Call Structure Burst Write to Slave (Master-Transmitter, Slave-Receiver) Single Read from Slave CATV Block Diagram Signals between the L64724 and L64777 Tables Allocation of Coefficient-Bits for Phase 0 2-30 Default Nyquist Filter Coefficients 2-32...
  • Page 10 Contents...

  • Page 11: Introduction

    Chapter 1 Introduction This chapter provides an introduction to the L64777. It consists of the following sections: • Section 1.1, “Overview,” page 1-1 • Section 1.2, “Operating Environment,” page 1-2 1.1 Overview The L64777 chip implements a QAM modulator that is digital video broadcasting (DVB)-compliant, as described in document ETS 300 429.

  • Page 12: Operating Environment

    The modulator is intended to follow either an MPEG transport stream source (for example, a transport multiplexer) or a satellite receiver, such as the LSI Logic L64724 (see Figure 1.1). It processes MPEG-2 system- compliant frames at the input. You can program the sync word and block length, and the chip can reinsert the sync information.
  • Page 13 • Frame sync byte reinsertion • Input jitter handling and Reed-Solomon gap insertion by a 128-word circular FIFO buffer • IEEE 1149.1 JTAG interface for testing • Up to 10 Mbytes/s parallel data input • Up to 60 Mbits/s serial data input •...
  • Page 14 Introduction...

  • Page 15: Modulator Architecture

    Section 2.11, “Square Root Nyquist Filter,” page 2-27 • Section 2.12, “Global Control and PLL Module,” page 2-34 • Section 2.13, “Interpolator,” page 2-39 • Section 2.14, “Serial Microprocessor Interface,” page 2-40 • Section 2.15, “Test Unit,” page 2-41 L64777 DVB QAM Modulator Technical Manual...

  • Page 16: Introduction

    Encoder conversion Filter Figure 2.2 is a block diagram of the L64777 architecture. The input clock drives only the input synchronizing stage. The OCLK, which is four times the QAM symbol rate, is the base of all residual processing. A numerically controlled oscillator (NCO) module allows the L64777 to interface with LSI Logic L64724.
  • Page 17 Figure 2.2 Data Path PCLK Inter- NCO* divided ICLK polator* & freq compare Data Sync & Circular Square Diff. Input Error flag Buffer Convol. Byte to Root Encoder (204,188) Sync Reinsertion FIFO Interleaver m-tuple Nyquist & QAM Encoder ICLK Stage Energy Filter Mapping...

  • Page 18: Pll Modes

    QAM signals in I and Q. 2.2 PLL Modes Connecting the L64777 to a satellite receiver and the LSI Logic satellite decoder chip set requires the PLL circuits to lock the input and output clocks. Two modes can achieve this: •...

  • Page 19: Pll Mode

    L64777 and the L64724 in Mode 2 operation. Consecutive sync blocks can have any gap length between them. Thus, the L64777 can convert an input block to a block with a gap for RS insertion, as long as the size of the 128-byte circular input buffer is sufficient to insert RS gaps and to cope with possible PLL jitter.

  • Page 20: I/O

    (see Section 2.4, “Input Synchronization,” page 2-10). 2.3.2 Output Signals The L64777 outputs the I and Q components of its signal on two separate analog output interfaces (see Figure 2.4). The output interface contains two internal 10-bit digital-to-analog converters.

  • Page 21: Analog I/Q Output Interface Diagram

    DAC achieves maximum linearity in differential mode). The L64777 I and Q component outputs are available in 10-bit digital format. The related clock depends on the PLL mode: OCLK is used in Mode 1;...

  • Page 22: Control Interface

    The internal VCO of the L64777 can generate OCLK, or it can use the OCLK input. The L64777 selects OCLK based on the selected PLL mode. OCLK drives the Nyquist filter and generates the symbol-processing clock inside the chip after the input circular buffer. The beginning of a sync frame at the I and Q output is indicated by the FSTARTOUT signal.
  • Page 23 C-Compatible Serial Control Interface loads the address byte into APR0 (see Appendix A, "Programming the L64777 in Serial Host Interface Mode"), for programming details. Reading or writing from Group 2 causes a data transfer with the device address specified by APR0: •...

  • Page 24: Serial Microprocessor Interface

    RESET to guarantee proper operation of the device. A default setup that requires no microprocessor download is built in for 64 QAM. In the L64777, the Group 2 register 0 acts as a sequential download register that feeds the 196 bytes of filter coefficients. After every write, the user can read back the last written coefficient to verify the tail entry...
  • Page 25 (TEI) unchanged from the input transport stream, or it can force the TEI to indicate an error with the ERRORIN signal. The L64777 observes the forced signal during the sync byte input and ignores it for the rest of the input packet.

  • Page 26: Fifo Clock Conversion

    * Note that DIN[7:0] is valid data, which is the result of D[7:0] and DVALIDIN HIGH The L64777 synchronizes the input in the ICLK domain and transfers it to the OCLK domain with a reserved bit in the circular buffer. It uses a second bit to transfer the incoming error flag for further insertion into the...

  • Page 27: Sync Acquisition Phase

    SYNC_BYTE in all possible bit positions and automatically detects the byte-alignment. In the L64777, the sync algorithm is fixed to a procedure with programmable values of S and P. In order to achieve the required functionality at the lowest possible gate count, you can select from three values of track steps, which are the number of flywheel repetitions...

  • Page 28: Sync Tracking Phase

    The sync tracking phase checks the detection of S at the correct location (i.e., every P bytes). TS − 1 mismatches are tolerated, but at the last mismatch the L64777 declares a loss-of-sync and goes back to state S0 to look for new synchronization.
  • Page 29 This transition activates a declaration of loss-of-sync. The L64777 activates output SYNCOK in state S3, S4, or S5. This allows easy measurement of synchronization conditions from outside and monitoring during normal operation. The microprocessor interface also provides SYNCOK information.

  • Page 30: Fifo Clock Conversion

    2.5 FIFO Clock Conversion The L64777 uses a dual-ported RAM to implement the circular buffer FIFO function. The circular buffer has a write pointer driven by ICLK and a read pointer driven by the Symbol clock, OCLK/4. The device does not prevent collisions of the pointers;...

  • Page 31: Sync/Ef Reinsertion Unit

    fixed to zero. Every time the L64777 accesses the FIFO delay value in the microprocessor interface (FDEL, see Section 4.1.3, “Register 2,” page 4-5), the pointers are reset to the these values. If the L64777 is programmed to the FIFO Autoreset mode (see Section 4.1.7, “Register 6,”...

  • Page 32: Sync Insertion Mode

    In unsynchronized states S0, S1, and S2, the L64777 bypasses data bits without any modification of the sync byte. After it establishes synchronization (in states S3, S4 and S5), the device inserts the regenerated sync pattern based on the programming of Register 1.
  • Page 33 The L64777 uses a special sync word (0xB8), generated by inverting every eighth transport sync word (0x47), to align the descrambler with the incoming data stream. The L64777 applies the first bit of the PRBS to the first data bit following the inverted sync byte and freezes the scrambler register contents during gaps for RS check words.

  • Page 34: Reed-Solomon Encoder

    SSTARTIN input signal can preset the phase of the inverted SYNC_BYTE and the whole scrambler sequence. The microprocessor can switch off the scrambler module through Register 3 (see Section 4.1.4, “Register 3,” page 4-5). The selected microprocessor control applies the sequence of Start, Run, and Disable modes, depending on the programmed sync block length values in Register 4 (see page 4-6).

  • Page 35: Forward Error Correction (Fec)

    Check Bytes The encoder generates and appends check bytes to the incoming message according to the Reed-Solomon error-correction encoding. The decoder uses check bytes to locate and correct errors due to transmission. Detection Power Detection power has a minimum value of and a --- - maximum value of R.

  • Page 36: Error Handling And Correction

    To achieve RS encoding at the lowest possible gate count and power consumption, the check byte parameters of the RS encoder in the L64777 are fixed to R = 16, according to the DVB standard. When the RS encoder is switched off, data feeds through without check-word insertion at an internal delay of two clock cycles.

  • Page 37: Convolutional Interleaver

    B, the desired interleaving depth, and M, defined as: --- - The values of the interleaver in the L64777 are: N = 204, B = 12, and M = 17. You can switch off the interleaver. It is fully transparent with an intrinsic delay of three clock cycles.

  • Page 38: Bytes To M-Tuples Converter

    Delay – In the L64777, the Delay = (11 x 12 x 17) = 2244 clock cycles. Thus, the delay from the time of the first input byte to the first valid output byte in the maximum delay path of the interleaver is half of this value, which is 1122 valid clock cycles.

  • Page 39: Byte To Symbol Conversion

    Figure 2.16 Symbol Cutting From Bytes m = 8 Byte N Byte N + 1 Byte N + 2 b6 b5 b6 b5 b7 b6 m = 4 b1 b0 b3 b2 b3 b2 b3 b2 Symbol t Symbol t + 1 Symbol t + 2 Symbol t + 3 Symbol t + 4...

  • Page 40: Differential Encoder And Qam Mapping

    2.10 Differential Encoder and QAM Mapping This block performs differential encoding and mapping for 16 and 64 QAM, as specified in the Digital Broadcasting Systems for Television Sound and Data Services: Framing Structure, Channel Coding and Modulation Cable Systems , the baseline document, and its extensions. The QAM 256 mapping is taken from the DVB document 1190.

  • Page 41: Square Root Nyquist Filter

    Each of the two I and Q branches has one filter, realized as polyphase structures. Each filter consists of four filter branches, which compute 1-phase filter results at the symbol rate. Thus, the L64777 Nyquist filter module generates the desired pulse shape by combining the outputs of four identical filter branches for I and Q.
  • Page 42 For an oversampling factor of four, the filter executes the above sequence at four times the symbol rate (60 MHz in PLL mode). Each multiply accumulator (MAC)-structure contains 31 multipliers whose outputs add up to the desired result. The pulse shaper module connects one input of each multiplier to a delayed version of the filter input data;...

  • Page 43: Filter Setup Procedure

    Figure 2.20 Output Scaling by Arithmetic Shift Right BITS_TO_SHIFT[3:0] Shifter I[9:0] IS[19:0] Shifter Q[9:0] QS[19:0] The shifter treats the value of BITS_TO_SHIFT[3:0] like a coefficient, and the value is available separately for every phase. This means that the hardware of the filter is multiplexed in such a way that there are the same coefficient registers for the I and Q channel, and each of the two MACs switches between four banks of coefficients cyclically, driven by OCLK.

  • Page 44: Example

    As shown in Figure 2.18, the filter shifts four coefficient register banks (Register 0) sequentially, starting with register 48 and proceeding down to 0. In this configuration, it shifts bank 3 first, then 49 bytes of bank 2, bank 1, and, finally, bank 0. Table 2.1 shows the exact allocation of bits within each bank.
  • Page 45 Table 2.1 Allocation of Coefficient-Bits for Phase 0 (Cont.) Reg # c6.7 c6.6 c6.5 c6.4 c6.3 c6.2 c6.1 c6.0 c7.7 c7.6 c7.5 c7.4 c7.3 c7.2 c7.1 c7.0 – c6.10 c6.9 c6.8 – c7.10 c7.9 c7.8 c8.7 c8.6 c8.5 c8.4 c8.3 c8.2 c8.1 c8.0...
  • Page 46 Table 2.1 Allocation of Coefficient-Bits for Phase 0 (Cont.) Reg # c23.7 c23.6 c23.5 c23.4 c23.3 c23.2 c23.1 c23.0 – c22.10 c22.9 c22.8 – c23.10 c23.9 c23.8 c24.7 c24.6 c24.5 c24.4 c24.3 c24.2 c24.1 c24.0 c25.7 c25.6 c25.5 c25.4 c25.3 c25.2 c251 c25.0...
  • Page 47 Table 2.2 Default Nyquist Filter Coefficients (Cont.) Phase0 Phase1 Phase2 Phase3 −1 −14 −19 −13 −8 −31 −38 −20 −27 −69 −71 −26 −95 −191 −184 −29 −29 −184 −191 −95 −26 −71 −69 −27 −20 −38 −31 −8 −13 −19 −14 −1...

  • Page 48: Default Filter Characteristics

    Normalized frequency (Nyquist == 1) 2.12 Global Control and PLL Module The L64777 interface supports serial and parallel input modes at the input interface. The global control generates the clocking for the input and output interfaces; it also controls the data path. It contains all the necessary logic to chain the processing units together.

  • Page 49: Numerically Controlled Oscillator (Nco)

    The global control manages the output data stream so that it is continuous (no gaps between the symbols), assuming that the incoming data rate is constant (on average). To achieve this, a PLL must derive the output clock OCLK from the input transport stream rate. The PLL module consists of two independent clock dividers for ICLK and OCLK.

  • Page 50: Acquisition Phase Using The Frequency Measurement Unit

    Figure 2.22 NCO Loop Diagram NPCLK, Frequency N_COUNT, NP_COUNT, Measurement Unit NM_COUNT Step Correction ICLK Virtual FIFO for Automatic Threshold If Serial Frequency Acquisition Byte Clock Phase Loop CNT_I CNT_O OCLK Divider Divider Interpolator Ctrl EXOR phase_gain enable_phase_loop = 1 Step (for Frequency Selection) 2.12.2 Acquisition Phase Using the Frequency Measurement Unit...
  • Page 51 The host computes the following formulae to get the initial step for phase 2, where ñ indicates the average n value. C 2 n ( ) C 3 n C 1 n 1 – n ˜ Equation 2.3 --------------------------------------------------------------------------------------- C 1 C 2 C 3 and from this: Sync length Equation 2.4...

  • Page 52: Autoacquisition Mode

    2.12.3 Autoacquisition Mode To ease the usage of phase 1, the NCO can use an automatic frequency acquisition. Enable regulation of the NCO_LOOP_ENABLE (bit 5) and set the AUTO_ACQUI bit (bit 3) in the NCO control register. Figure 2.23 outlines the parameter usage during automatic frequency acquisition. Figure 2.23 Frequency Acquisition Loop Overview init step = init step (reg 16 to 18)

  • Page 53: Regulation Phase

    Note that the virtual FIFO, which indicates the FIFO under- or over-run, is an internal location. If the NCO_GAIN has reached the smallest possible value of 1, the AUTO_ACQUISITION terminates. The AUTO_ACQUI_RUNNING bit (Register 13, bit 3) sets to zero, indicating termination. If enabled, the NCO can issue an interrupt on this condition.

  • Page 54: Serial Microprocessor Interface

    (for example, the FIFO alarm signal). The following interface signals are used: Serial control line Serial data access INT_n Interrupt, open drain output The same type of two-wire serial interface is available on the LSI Logic L64724. 2-40 Modulator Architecture...

  • Page 55: Test Unit

    • Digital-to-analog conversion test • PLL tests Select the L64777 test modes through the FTMODE pins. The default values for normal operation are: FTMODE = 000, SCAN_ENABLE = 0, TNn = 1. If TNn is cleared, all outputs are high-impedance.
  • Page 56 To guarantee the proper operation of the L64777 in the printed circuit board environment, an additional IEEE 1149.1 JTAG module is included in the device, which operates on the following pins: • TRSTn = 0 • TCK = 0 •...

  • Page 57: Transport Interface

    The transport interface can operate in either parallel or serial mode. 3.1.1 Synchronization The L64777 can synchronize the transport interface in two ways. In both modes, it works synchronously with ICLK and reads all signals, including input data, on the raising edge of ICLK.

  • Page 58: Synchronization Methods

    (TEI) unchanged from the input transport stream, or it can force the TEI to indicate an error with the ERRORIN signal. The L64777 observes the forced signal during the sync byte input and ignores it for the rest of the input packet.

  • Page 59: Analog Output Interface

    If APR0 is not at zero, the Serial Control Interface expects only a single data byte and applies an autoincrement to the APR0. The L64777 ignores Group 1 and Groups 3 to 7. It does not apply any reading or writing from them.

  • Page 60: Analog I/Q Output Interface Diagram

    (Test mode is Vref2 selected using FT mode pins) VDDX2 AVDD2COMP2 10-Bit DAC Differential Q Output QAM_Q, QAM_Qn Q Filter Output AVSS2 On-Chip Off-Chip Figure 3.2 shows a typical application for interfacing with the outputs of the two L64777 DACs. Interfaces...
  • Page 61 Figure 3.2 I And Q DAC Filter Diagrams 5 V A 10 µF/16 V R169 QAM_I − −VS IN− QAM_IN −VS AD8048AR 10 µF/16 V − 5 V A 5 V A 10 µF/16 V QAM_Q − IN− QAM_QN −VS AD8048AR 10 µF/16 V −...

  • Page 62: Digital Output Interface

    DAC achieves maximum linearity in differential mode). 3.4 Digital Output Interface The L64777 I and Q component outputs are available in 10-bit digital format. Depending on the PLL mode, either OCLK or PCLK is the related clock. The output format can be programmed either as a two’s complement, or as a sine magnitude representation.

  • Page 63: Register Descriptions

    Group 0 Address Pointer register. All 43 registers of the L64777 are 8-bit. Table 4.1 provides an overview of the bit allocations for the L64777 registers. Note that an R in column A indicates a read-only register; an RW indicates a read/write register.

  • Page 64: Group 2 Bit Allocation

    Table 4.1 Group 2 Bit Allocation Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FCOEFF.7 FCOEFF.6 FCOEFF.5 FCOEFF.4 FCOEFF.3 FCOEFF.2 FCOEFF.1 FCOEFF.0 R/W 0 FREQ_PHA SERIN NEWSYNC EXTSYNC PLLSET MSIZE.2 MSIZE.1 MSIZE.0 R/W 1 RESERVED FDEL.6 FDEL.5 FDEL.4 FDEL.3 FDEL.2 FDEL.1 FDEL.0 R/W 2...
  • Page 65 Table 4.1 Group 2 Bit Allocation (Cont.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 REF_DUR.7 REF_DUR.6 REF_DUR.5 REF_DUR.4 REF_DUR.3 REF_DUR.2 REF_DUR.1 REF_DUR.0 REF_DUR. REF_DUR REF_DUR. REF_DUR. REF_DUR. REF_DUR. REF_DUR.9 REF_DUR.8 PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR. PROB_DUR.

  • Page 66: Register

    Serial/Parallel Input Setting R/W 7 When this bit is 1, the L64777 uses DIN[0] as serial input and considers ICLK as a bit clock. When this bit is 0, the L64777 uses DIN[7:0] as parallel input and ICLK as a byte clock.

  • Page 67: Register

    SMAG Sign Magnitude R/W 7 When this bit is 0, the L64777 outputs a two’s complement at the Nyquist filter. When this bit is 1, the L64777 inverts the sign bit and the output sign magnitude representation. The reset value is 0.

  • Page 68: Register

    IQ_EX I and Q Channel Exchange R/W 5 When this bit is 1, the L64777 exchanges the I and Q channels at the Nyquist filter input. When this bit is 0, the L64777 leaves the data stream unchanged. The reset value is 0.
  • Page 69 AMPL AUTORESET Automatic Reset Setting R/W 7 When this bit is 1, the L64777 loads the FIFO address counters with the initial values in register 2 after the detection of a FIFO alarm (pointer collision). When this bit is 0, the FIFO address counters remain unchanged after a pointer collision until an external microcontroller intervenes.

  • Page 70: Registers 7 And

    R/W 1 This controls the amplitude of the on-chip PLL oscillator. When this bit is 0, the L64777 is in low-power mode with higher jitter. When this bit is 1, the L64777 is in high-power mode with lower jitter. For normal operation, set this bit to 0.

  • Page 71: Register

    4.1.10 Register 11 UNCONST. TRACKSTEPS INPUT TRACKSTEPS Steps to Sync R/W [7:6] This value indicates the number of steps to acquire synchronization and to declare loss of sync if the sync pattern is missing for this number of events: 0b00 = 3 0b01 = 4 0b11 = 5 The reset value is 0b00.

  • Page 72: Nco-Related Registers

    4.2 NCO-Related Registers 4.2.1 Register 12 SYNCOK FIFO_ALARM MASK_SYNC MASK_FIFO SYNCOK ERF_STORE NCO_EVENT MASK_ERF _STORE _STORE _ALARM SYNCOK State of SYNCOK Pin R/W 7 This value reflects the actual state of the SYNCOK pin. This signal is slow enough to be sampled by the external microcontroller.

  • Page 73: Register

    MASK_SYNCOK If this bit is 1, a missing SYNCOK does not generate an interrupt. If this bit is 0, a missing SYNCOK generates an interrupt. The reset value is 0. MASK_FIFO_ALARM If this bit is 1, a FIFO alarm (pointer collision) does not generate an interrupt.

  • Page 74: Register

    4.2.3 Register 14 START_ AUTO_ ENABLE_ MASK_NCO_ MASK_ACQ_ EN_PHASE_ MEASURE- ACUISITION FIFO_INT NCO_LOOP LOOP MENT Reserved This bit is reserved. START_MEASUREMENT R/W 6 A transition from 0-to-1 starts a measurement of the byte clock connected to the ICLK input. MEASUREMENT_ DONE in status register (13) indicates the end of the measurement.

  • Page 75: Registers 16, 17, And

    NCO_GAIN NCO Loop Bandwidth Adjustment R/W [15:0] The L64777 can use this parameter to adjust the NCO loop bandwidth. The value becomes valid on writing to the most significant portion. These are NCO-related register fields; they are used only in PLL Mode 2. Bit 8 is reset to 1;...

  • Page 76: Registers 21 And

    4.2.7 Registers 21 and 22 REF_DUR REF_DUR Duration Between NCO Step Updates R/W [15:0] This parameter determines the duration between the NCO step updates in multiples of the sync length. These are NCO-related register fields; they are used only in PLL Mode 2.

  • Page 77: Registers 29, 30, And

    register is valid only if the MEASUREMENT_DONE bit in the NCO control register is set. These are NCO-related register fields; they are used only in PLL Mode 2. The reset value is 0. 4.2.11 Registers 29, 30, and 31 N_COUNT N_COUNT ICLK Cycles R [23:0]...

  • Page 78: Registers 38 And

    4.2.14 Registers 38 and 39 CUR_UPD CUR_UPD Current NCO Loop Update Step R [15:0] This value indicates the current NCO loop update step. It differs from the programmed update step if autoacquisi- tion is enabled. The registers are read-only. These are NCO-related register fields;...

  • Page 79: Register

    4.2.17 Register 42 EXT_GAP EXT_GAP Gap Bytes R/W [7:0] This value indicates the number of gap bytes applied to the TS input. These are NCO-related register fields; they are used only in PLL Mode 2. The reset value is 0b0100 0110. 4.2.18 Register 43 THRESHOLD THRESHOLD FIFO Measurement Threshold...
  • Page 80 Table 4.2 Reset Values for Register Fields (Cont.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 4-18 Register Descriptions...

  • Page 81: Overview

    Chapter 5 Signals This chapter defines the signals for the L64777. It consists of the following sections: • Section 5.1, “Overview,” page 5-1 • Section 5.2, “MPEG Transport Stream Multiplexer Signals,” page 5-3 • Section 5.3, “Status Information Signals,” page 5-4 •...

  • Page 82: Logic Symbol For The L64777

    Figure 5.1 Logic Symbol for the L64777 Serial Microprocessor Interface AVDD1 AVDD2 DIN[7:0] AVSS1 AVSS2 DVALIDIN COMP1 COMP2 ERRORIN IREF1 MPEG TS Analog IREF2 FSTARTIN QAM_I QAM_IN ICLK L64777 QAM_Q QAM Modulator QAM_QN SCLK VDDX_I VDDX_Q SSTARTIN VREF_I VREF_Q DIG_I[9:0]...

  • Page 83: Mpeg Transport Stream Multiplexer Signals

    MPEG transport packet by a hardwired signal. If the incoming bitstream contains no unique sync words, this pulse must be applied to the L64777. The L64777 forces synchronization with FSTARTIN pulses into the chip; it does not flywheel-stabilize synchronization as in the sync word detection mode.

  • Page 84: Status Information Signals

    SCLK is a clock output synchronous to internally processed symbols and bytes; it is identical to OCLK/4. The L64777 uses SCLK to determine the phase of the Nyquist filter output. The rising edge of SCLK is followed by Phase 0. The falling edge is the transition of Phase 1 to Phase 2 in 4-fold oversampling mode.

  • Page 85: Test Signals

    FSTARTOUT Frame Start Output Output FSTARTOUT is asserted during the first symbol in every sync frame. The width of FSTARTOUT reflects the number of bytes that the gap parameter inserts. A one-cycle width indicates no inserted gaps; a width of 17 means 16 inserted bytes as an Reed-Solomon gap.

  • Page 86: Control Signals

    5.5 Control Signals OCLK Encoder Out/Processing Clock In Bidirectional OCLK is a positive-edge-triggered clock. The L64777 internally processes data based on a fraction of OCLK (for example: scrambler, interleaver, Reed-Solomon encoder) and references data outputs (I, Q, FSTARTOUT) to OCLK.

  • Page 87: Analog Qam Signals

    5.7 Analog QAM Signals AVDD1 Analog VDD Input: I Component DAC Analog Input For usage and value, see the LSI Logic datasheet ® -p CW900100 10-bit Direct Digital Synthesis Digital- to-Analog Converter (September 1998). AVDD2 Analog VDD Input: Q Component DAC Analog Input For usage and value, see the LSI Logic datasheet ®...

  • Page 88: Serial Microprocessor Interface Signals

    Converter (September 1998). 5.8 Serial Microprocessor Interface Signals INT_n Interrupt Request Output The L64777 asserts INT_n LOW when the interrupt is enabled and an interrupt condition occurs. INT_n is an open drain output that requires an external pull-up resistor for operation. Signals...
  • Page 89 SB_BASE[1:0] Serial Bus Base Address Input The external microprocessor must apply these two signals as static signals to the device because they determine the two LSBs of the serial bus base address. Serial Clock Line Input In conjunction with SDA, SCL controls the microprocessor interface according to the protocol described in Appendix A.
  • Page 90 5-10 Signals...

  • Page 91: Ac/Dc Specifications

    Chapter 6 Specifications This chapter provides information about the electrical ratings, pins, and packaging for the L64777. It consists of the following sections: • Section 6.1, “AC/DC Specifications,” page 6-1 • Section 6.2, “Pin Descriptions and Lists,” page 6-5 •...

  • Page 92: L64777 Absolute Maximum Ratings

    + 3.14 to + 3.45 V °C Ambient Temperature 0 to + 70 When studying the values in Table 6.3, note that the L64777 follows the LSI Logic G10-p process, which is characterized by a 0.35-micron gate length. Table 6.3...

  • Page 93: Ac Timing Diagrams For L64777

    1 & 4 2 & 5 3 & 6 ICLK Inputs Figure 6.2 illustrates the reset timing of the L64777. Figure 6.2 L64777 RESET Timing Diagram RESET Figure 6.3 illustrates the 3-state delay timing of the L64777 bus. AC/DC Specifications...

  • Page 94: L64777 Bus 3-State Delay Timing

    Figure 6.3 L64777 Bus 3-state Delay Timing DATA The numbers in column 1 of Table 6.4 refer to the timing parameters in = 0 °C to the preceding figures. All parameters in this table apply for T 85 °C, V = 3.1 V to 3.6 V, and an output load of 50 pF.

  • Page 95: Pin Descriptions And Lists

    L64777 pins. 6.2.1 L64777 Electrical Pin Descriptions Table 6.5 summarizes the electrical properties of the pins on the L64777. The table provides the signal types for both output and input pins, and the drive capacity for outputs.
  • Page 96 Table 6.5 L64777 Pin Description Summary (Cont.) Drive Mnemonic Description Type (mA) Active FTMODE[2:0] Functional Test Mode Input w/Pulldown – HIGH Ground Analog – – ICLK Input Clock TTL Input – LOW/ HIGH IDDTN IDD Test TTL Input – w/Pullup...
  • Page 97 Table 6.5 L64777 Pin Description Summary (Cont.) Drive Mnemonic Description Type (mA) Active SCAN_ENABLE Scan Enable TTL Input – HIGH w/Pulldown Serial Control Line Input HIGH (5 V-tolerant) SCLK Symbol Clock Output Output LOW/ HIGH Serial Data Access Bidirectional Open-...

  • Page 98: Numerical Pin List For The L64777

    6.2.2 Numerical Pin List for the L64777 Table 6.6 L64777 Numerical Pin List Signal Signal Signal Signal PLL_MODE.0 TRSTN PLL_MODE.1 QAM_I IDDTN NT_OUT QAM_IN INT_N AVDD1 RESET_N SCAN_ENABLE 95 IREF1 FTMODE.0 COMP1 DIG_Q.0 FIFOALARM FTMODE.1 VREF_I DIG_Q.1 FIRSTOUT FTMODE.2 AVSS DIG_Q.2...

  • Page 99: Alphabetic Pin List For The L64777

    6.2.3 Alphabetic Pin List for the L64777 Table 6.7 L64777 Alphabetical Pin List Signal Signal Signal Signal AVDD1 DIN.4 PLL_MODE.132 VDD77 AVDD2 DIN.5 PLL_OUT_CS VDD86 AVSS DIN.6 QAM_I VDD91 AVSS2 DIN.7 QAM_IN COMP1 DVALIDIN QAM_Q COMP2 ERRORIN QAM_QN DIG_I.0 FIFOALARM RESET_N DIG_I.1...

  • Page 100: Package Pinout

    FSTARTIN ERRORIN QAM_I DVALIDIN QAM_IN AVDD1 IREF1 DIN.0 COMP1 DIN.1 VREF_I DIN.2 AVSS1 DIN.3 VDDX_I ICLK VDDX_Q Top View AVSS2 VREF_Q COMP2 L64777 DIN.4 IREF2 DIN.5 AVDD2 DIN.6 QAM_QN DIN.7 QAM_Q FSTARTOUT SYNCOK FIRSTOUT FIFOALARM INT_N PLL_OUT_CS TRSTN 6-10 Specifications...
  • Page 101 120-Pin PQFP (PE) Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code PE. Package Pinout...
  • Page 102 120-Pin PQFP (PE) Mechanical Drawing (Cont.) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code PE. 6-12...

  • Page 103: Programming The L64777 In Serial Host Interface Mode

    Programming the L64777 in Serial Host Interface Mode This appendix discusses how to program the L64777 internal registers and data tables in serial host interface mode. This chapter is intended primarily for system programmers who are developing software drivers using the serial bus.
  • Page 104 7-Bit Slave Address for L64777 Serial Bus SB_BASE1 SB_BASE0 The bus master always generates the clock and cycle start and stop conditions. Figure A.2 gives an overview of the read and write cycles using the serial bus protocol. Programming the L64777 in Serial Host Interface Mode...

  • Page 105: Serial Bus Write/Read Cycle

    Figure A.2 Serial Bus Write/Read Cycle Start Stop Condition Condition Write Cycle bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Master-Transmitter, Slave-Receiver ACK Cycle: Slave Master-Transmitter, Slave-Receiver ACK Cycle: Slave (Master transmits slave address) (Master transmits data to slave) Read Cycle (burst) bit7...

  • Page 106: Programming The Slave Address Using The Serial Bus Interface

    Address Programming register (APR) is to be loaded. (The master accesses Group 0 only to load the APR.) 6. The master then sends the 8-bit data, which initializes the address pointer register (APR0). Programming the L64777 in Serial Host Interface Mode...

  • Page 107: Read Cycle Using The Serial Bus Interface

    7. The master generates another start condition. 8. The master repeats steps 2–7 to address the appropriate group and write 1 or more data bytes. 9. The master terminates the cycle by issuing a stop condition. Figure A.4 Burst Write to Slave (Master-Transmitter, Slave-Receiver) Start Stop Start...
  • Page 108 For burst reads, the master drives SDA LOW for each byte it receives during the ACK cycle, except for the last byte. 19. The master terminates the cycle by issuing a stop condition. Programming the L64777 in Serial Host Interface Mode...

  • Page 109: Limitations

    Figure A.5 Single Read from Slave Start Start Stop Start Condition Condition Condition Condition (Slave) (Slave) (Slave) (Slave) (Slave) (Slave) (Master) 10 11 16 17 7-bit Slave 8-bit Group 7-bit Slave 7-bit Slave 8-bit Group Address Address Address Address Address 8-bit Data 8-bit Data Bit 7...
  • Page 110 Programming the L64777 in Serial Host Interface Mode...

  • Page 111: Overview

    Appendix B PLL Divider Settings and L64724/34 Connection This appendix lists the PLL divider settings for typical applications. It also describes the L64777 connection to the L64724 and contains the following sections: • Section B.1, “Overview,” page B-1 • Section B.2, “PLL Driver Settings for Typical Applications,” page B-2 •...

  • Page 112: Pll Divider Settings And L64724/34 Connection

    SCLK, OCLK, and input data rate is described in the following subsections. If the same serial host controls both the L64724 and the L64777, hold the L64777 in reset until the L64724 PLL has been programmed. B.2 PLL Driver Settings for Typical Applications Table B.1 lists the L64777’s PLL driver settings for Mode 1.

  • Page 113: Connecting The L64777 To The Lsi Logic L64724

    L64777. In this mode, the L64724 outputs 204-byte clock cycles, together with an indication for the 188 valid data bytes. Connect the byte clock to the ICLK input of the L64777, as a reference for generating the output sampling rate (OCLK); and connect the PCLK output of the L64724 to the PCLK input of L64777.
  • Page 114 When the input to the L64777 is from the L64724 for a satellite of selected center frequency and baud rate, the parameters to be programmed into the L64777 for 64 QAM are: Operational Mode = NCO mode (Mode 2) Block Length = 188 bytes...

  • Page 115: Monitoring Device Internal Signals

    Set to 1 for power-down mode; after reset, this is 0 test.5: Set to 1 for power-down mode; after reset, this is 0 test.6: Set to 1 for power-down mode; after reset, this is 0 L64777 DVB QAM Modulator Technical Manual...
  • Page 116 Monitoring Device Internal Signals...

  • Page 117: Customer Feedback

    Customer Feedback We would appreciate your feedback on this document. Please copy the following page, add your comments, and fax it to us at the number shown. If appropriate, please also fax copies of any marked-up pages from this document. Important: Please include your name, phone number, fax number, and company address so that we may contact you directly for...
  • Page 118 Fax your comments to: LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: L64777 DVB QAM Modulator Technical Manual. Place a check mark in the appropriate blank for each category. Excellent Good Average Fair...
  • Page 119 U.S. Distributors by State A. E. Avnet Electronics Colorado Illinois Michigan http://www.hh.avnet.com Denver North/South Brighton B. M. Bell Microproducts, A. E. Tel: 303.790.1662 A. E. Tel: 847.797.7300 I. E. Tel: 810.229.7710 Inc. (for HAB’s) B. M. Tel: 303.846.3065 Tel: 314.291.5350 Detroit http://www.bellmicro.com W.
  • Page 120 U.S. Distributors by State (Continued) New York South Carolina Washington Hauppauge A. E. Tel: 919.872.0712 Kirkland I. E. Tel: 516.761.0960 W. E. Tel: 919.469.1502 I. E. Tel: 425.820.8100 Long Island Maple Valley South Dakota A. E. Tel: 516.434.7400 B. M. Tel: 206.223.0080 A.
  • Page 121 Sales Offices and Design Resource Centers LSI Logic Corporation Fort Collins New Jersey Canada Corporate Headquarters 2001 Danfield Court Red Bank Ontario Fort Collins, CO 80525 1551 McCarthy Blvd 125 Half Mile Road Ottawa Tel: 970.223.5100 Milpitas CA 95035 Suite 200 260 Hearst Way Tel: 408.433.8000...
  • Page 122 Sales Offices and Design Resource Centers (Continued) Korea Seoul LSI Logic Corporation of Korea Ltd 10th Fl., Haesung 1 Bldg. 942, Daechi-dong, Kangnam-ku, Seoul, 135-283 Tel: 82.2.528.3400 Fax: 82.2.528.2250 The Netherlands Eindhoven LSI Logic Europe Ltd World Trade Center Eindhoven Building ‘Rijder’...
  • Page 123 Switzerland Tel: 44.1793.849933 Bangalore, India 560078 Xicheng District ♦ Brugg Fax: 44.1793.859555 Tel: 91.80.664.5530 Beijing 100045, China LSI Logic Sulzer AG Tel: 86.10.6804.2534 to 38 Fax: 91.80.664.9748 Mattenstrasse 6a Fax: 86.10.6804.2521 ♦ CH 2555 Brugg Sales Offices with Israel Tel: 41.32.3743232...

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