Holtek HT82B60R Manual

I/o mcu with usb interface

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Features
·
Operating voltage:
f
=6M/12MHz: 3.3V~5.5V
SYS
·
Low voltage reset function
·
42 bidirectional I/O lines (max.)
·
8-bit programmable timer/event counter with
overflow interrupt
·
16-bit programmable timer/event counter and
overflow interrupts
·
Watchdog Timer
·
PS2 and USB modes supported
·
USB 2.0 low speed function
·
4 endpoints supported -- endpoint 0 included
·
8192´16 program memory
·
216´8 data memory RAM
·
Integrated 1.5kW resistor between V33O and
USBPDN pins for USB applications
General Description
The HT82B60R is a high performance, RISC architec-
ture microcontroller device specifically designed for
multiple I/O control product applications.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, integrated USB interface, serial in-
terfaces, LCD drive capability, power down and
wake-up functions, watchdog timer etc, make the de-
vice extremely suitable for use in computer peripheral
product applications as well as many other applications
such as industrial control, consumer products, subsys-
tem controllers, etc.
Rev. 1.10
I/O MCU with USB Interface
·
Fully integrated 6MHz or 12MHz oscillator
·
All I/O pins have wake-up functions
·
Power-down function and wake-up feature reduce
power consumption
·
Serial Interface Module -- I
·
4 COM lines for LCD display driving
·
External interrupt pin
·
8-level subroutine nesting
·
Up to 0.33ms instruction cycle with 12MHz system
clock at V
=5V
DD
·
Bit manipulation instruction
·
15-bit table read instruction
·
63 powerful instructions
·
All instructions in one or two machine cycles
·
20/28/48-pin SSOP, 32-pin QFN and
48-pin LQFP packages
These wide range of functions, together with a fully inte-
grated 6MHz or 12MHz oscillator, ensure that products
can be implemented with a minimum of external compo-
nents and smaller circuit board areas, providing users
with the benefits of lower overall product costs.
1
HT82B60R
2
C and SPI functions
February 1, 2011

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Summary of Contents for Holtek HT82B60R

  • Page 1 USBPDN pins for USB applications 48-pin LQFP packages General Description The HT82B60R is a high performance, RISC architec- These wide range of functions, together with a fully inte- ture microcontroller device specifically designed for grated 6MHz or 12MHz oscillator, ensure that products multiple I/O control product applications.
  • Page 2: Block Diagram

    HT82B60R Block Diagram Pin Assignment H T 8 2 B 6 0 R 3 2 Q F N - A H T 8 2 B 6 0 R 2 0 S S O P - A H T 8 2 B 6 0 R / H T 8 2 B 6 0 A...
  • Page 3 HT82B60R Pin Description Pin Name Options Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by a configuration option. Software instructions de- PA0~PA5 Pull-high termine if the pin is a CMOS output or NMOS, PMOS or Schmitt...
  • Page 4 HT82B60R D.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Operating Voltage ¾ ¾ =6MHz or 12MHz (Integrated Oscillator) ¾ No load, f =6MHz Operating Current ¾ No load, f =12MHz No load, system HALT, USB mode, USR.5=1 USR.4=0,...
  • Page 5 HT82B60R A.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ RC Clock with 8-bit Prescaler Register RCSYS Watchdog Time-out Period ¾ ¾ ¾ ¾ 1024 RCSYS (System Clock) ¾ ¾ ¾ USBPDP, USBPDN Rising & Falling Time ¾...
  • Page 6: System Architecture

    A key factor in the high-performance features of the functions. In this way, one T1~T4 clock cycle forms one Holtek range of microcontrollers is attributed to the inter- instruction cycle. Although the fetching and execution of nal system architecture. The range of devices take ad-...
  • Page 7 HT82B60R When executing instructions requiring jumps to After a device reset, the Stack Pointer will point to the non-consecutive addresses such as a jump instruction, top of the stack. a subroutine call, interrupt or reset, etc., the If the stack is full and an enabled interrupt takes place,...
  • Page 8: Program Memory

    HT82B60R · · Logic operations: AND, OR, XOR, ANDM, ORM, Location 008H XORM, CPL, CPLA This area is reserved for the Timer/Event Counter 0 in- terrupt service program. If a timer interrupt results · Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,...
  • Page 9 HT82B60R · option has disabled TBHP, the instruction ²TABRDC Table location Any location in the program memory can be used as [m]² reads the Program Memory data as defined by look-up tables. There are three methods to read the TBLP only in the current Program Memory page.
  • Page 10: Data Memory

    HT82B60R tempreg1 db ; temporary register #1 tempreg2 db ; temporary register #2 mov a,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or present page tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempregl ;...
  • Page 11: Special Function Registers

    HT82B60R Special Purpose Data Memory Special Function Registers This area of Data Memory is where registers, necessary To ensure successful operation of the microcontroller, for the correct operation of the microcontroller, are certain internal registers are implemented in the Data stored.
  • Page 12 HT82B60R data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ¢code¢ start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ;...
  • Page 13 HT82B60R S T A T U S R e g i s t e r A r i t h m e t i c / L o g i c O p e r a t i o n F l a g s...
  • Page 14: Input/Output Ports

    Note that some pins can only be Input/Output Ports setup nibble wide whereas other can be bit selected to Holtek microcontrollers offer considerable flexibility on have a wake-up function. their I/O ports. With the input or output designation of ev-...
  • Page 15 HT82B60R must select the timer mode, which has an internal will in fact only read the status of the output data latch clock source, to prevent the input pin from interfering and not the actual logic status of the output pin.
  • Page 16: Timer/Event Counters

    HT82B60R PCC, PDC, PEC and PFC port control register, are then Depending upon the condition of the T0E or T1E bit in programmed to setup some pins as outputs, these out- the Timer Control Register, each high to low, or low to...
  • Page 17 HT82B60R 8-bit Timer/Event Counter 0 Structure 16-bit Timer/Event Counter 1 Structure T M R 0 C R e g i s t e r Timer/Event Counter 0 Control Register T M R 1 C R e g i s t e r Timer/Event Counter 1 Control Register Rev.
  • Page 18 /4 is used as the inter- Timer Control Register - TMR0C/TMR1C nal clock for the Timer/Event Counters. After the other The flexible features of the Holtek microcontroller bits in the Timer Control Register have been setup, the Timer/Event Counters enable them to operate in three...
  • Page 19 HT82B60R In this mode, the external timer pin, TMR0 or TMR1, is In this mode the internal clock, f /4 is used as the inter- used as the Timer/Event Counter clock source, however nal clock for the Timer/Event Counters. After the other it is not divided by the internal prescaler.
  • Page 20 HT82B60R ensuring that the Timer/Event Counter Interrupt Enable Care must be taken to ensure that the timers are prop- bit in the Interrupt Control Register, INTC0, is reset to erly initialised before using them for the first time. The zero.
  • Page 21 HT82B60R org 04h ; USB interrupt vector reti org 08h ; Timer/Event Counter interrupt vector jmp tmr0int ; jump here when Timer0 overflows org 20h ; main program ;internal Timer/Event Counter 0 interrupt routine Tmr0int: ; Timer/Event Counter 0 main program placed here...
  • Page 22 HT82B60R Interrupt Structure Interrupt Priority When the interrupt is enabled, the stack is not full and the USB interrupt is active, a subroutine call to location Interrupts, occurring in the interval between the rising 04H will occur. The interrupt request flag, USBF, and the edges of two consecutive T2 pulses, will be serviced on EMI bit will be cleared to disable other interrupts.
  • Page 23 HT82B60R I N T C 0 R e g i s t e r INTC0 Register I N T C 1 R e g i s t e r INTC0 Register Rev. 1.10 February 1, 2011...
  • Page 24 HT82B60R SPI/I C Interface Interrupt Only the Program Counter is pushed onto the stack. If the contents of the accumulator or status register are al- For an SPI/I C interrupt to occur, the global interrupt en- tered by the interrupt service program, which may cor-...
  • Page 25 ²0² and the TO flag will be set to ²1². Refer to the A.C. More information regarding external reset circuits is Characteristics for t details. located in Application Note HA0075E on the Holtek website. · RES Pin Reset This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch.
  • Page 26 HT82B60R Reset Initial Conditions The following table indicates the way in which the vari- ous components of the microcontroller are affected after The different types of reset described affect the reset a power-on reset occurs. flags in different ways. These flags, known as PDF and...
  • Page 27 HT82B60R WDT Time-out RES Reset Reset RES Reset USB Reset USB Reset Register (Normal (Normal Time-out (Power-on) (HALT) (Normal) (HALT) Operation) Operation) (HALT)* 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111...
  • Page 28 If the configuration options have enabled the Watchdog Timer internal oscillator then this will continue to run All of the Holtek microcontrollers have the ability to enter when in the Power Down Mode and will thus consume a Power Down Mode. When the device enters this mode, some power.
  • Page 29: Watchdog Timer

    HT82B60R Each pin on all I/O ports can be setup via an individual Watchdog Timer configuration option to permit a negative transition on the pin to wake-up the system. When a I/O ports pin The WDT clock source is implemented by a dedicated...
  • Page 30 HT82B60R Bit No. Label Function Watchdog Timer division ratio selection bits Bit 2,1,0 = 000, division ratio = 1:1 Bit 2,1,0 = 001, division ratio = 1:2 WDTS0 Bit 2,1,0 = 010, division ratio = 1:4 WDTS1 Bit 2,1,0 = 011, division ratio = 1:8...
  • Page 31: Usb Interface

    USB interface. Both the USBPDN and AD6~AD0 USB device address USBPDP is driven by the SIE of the HT82B60R. The AWR (42H) Register user can only write or read the USB data through the corresponding FIFO. Both the MODE_CTRL 0~1 de- fault is ²0².
  • Page 32 HT82B60R The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus, PS2 or USB. The endpoint request flags, EP0IF, EP1IF, EP2IF and EP3IF, are used to indicate which endpoints are accessed.
  • Page 33 HT82B60R STALL and PIPE, PIPE_CTRL, Endpt_EN Registers The PIPE register represents whether the corresponding endpoint is accessed by the host or not. After an ACT_EN sig- nal has been sent out, the MCU can check which endpoint had been accessed. This register is set only after the a time when the host is accessing the corresponding endpoint.
  • Page 34 HT82B60R The SIES Register is used to indicate the present signal state in which the SIE receives and also defines whether the SIE has to change the device address automatically. Bit No. Function Read/Write Register Address Adr_set F0_ERR 01000001B ¾...
  • Page 35 HT82B60R The MISC register combines a command and status to control desired endpoint FIFO action and to show the status of the desired endpoint FIFO. The MISC will be cleared by the USB reset signal. Bit No. Label Function After setting the other status of the desired one in the MISC, endpoint FIFO can be requested by setting this bit to ²1².
  • Page 36: Lcd Driver

    HT82B60R Register Bits Read/Write Functions TBHP Store current table read bit12~bit8 data TBHP Register LCD Driver The devices have the capability of driving external LCD The LCDEN bit in the LCDC register is the overall mas- panels. The common pins for LCD driving, COM0~ ter control for the LCD Driver, however this bit is used in COM3, are pin shared with certain pin on the PC port.
  • Page 37 HT82B60R L C D C R e g i s t e r LCDC Register Serial Interface Function The device contains a Serial Interface Function, which The communication is full duplex and operates as a includes both the four line SPI interface and the two line...
  • Page 38 HT82B60R The SPI function in this device offers the following fea- the SIMCTL0 register will have no effect. Another two tures: SIM configuration options determine if the CSEN and WCOL bits are to be used. ¨ Full duplex synchronous data transfer ¨...
  • Page 39 HT82B60R The SIMDR register is used to store the data being trans- SPI Master/Slave Clock SIM0 SIM1 SIM2 mitted and received. The same register is used by both Control and I2C Enable the SPI and I C functions. Before the microcontroller...
  • Page 40 HT82B60R may be generated. The CKPOL bit determines the device and one as the slave device. Both master and base condition of the clock line, if the bit is high then slave can transmit and receive data, however, it is the the SCK line will be low when the clock is inactive.
  • Page 41 HT82B60R S I M C T L 0 R e g i s t e r C Control Register - SIMCTL0 SPI/I S I M C T L 1 R e g i s t e r C Control Register - SIMCTL1...
  • Page 42 HT82B60R SPI Master Mode Timing SPI Slave Mode Timing (CKEG=0) SPI Slave Mode Timing (CKEG=1) Rev. 1.10 February 1, 2011...
  • Page 43 HT82B60R SPI Transfer Control Flowchart C Block Diagram Rev. 1.10 February 1, 2011...
  • Page 44 HT82B60R ¨ ¨ SIMEN HASS The SIMEN bit is the overall on/off control for the I The HASS flag is the address match flag. This flag interface. When the SIMEN bit is cleared to zero to is used to determine if the slave device address is...
  • Page 45 HT82B60R As an I C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the in- terrupt source has come from a matching slave ad- dress or from the completion of a data byte transfer.
  • Page 46 HT82B60R C Communication Timing Diagram C Bus ISR Flow Chart Rev. 1.10 February 1, 2011...
  • Page 47 HT82B60R · Data Byte Peripheral Clock Output The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its The Peripheral Clock Output allows the device to supply slave address. The order of serial bit transmission is external hardware with a clock signal synchronised to the MSB first and the LSB last.
  • Page 48: Application Circuits

    HT82B60R Application Circuits H T 8 2 B 6 0 R Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES high.
  • Page 49: Instruction Set

    For easier understanding of the various instruction The standard logical operations such as AND, OR, XOR codes, they have been subdivided into several func- and CPL all have their own instruction within the Holtek tional groupings. microcontroller instruction set. As with the case of most...
  • Page 50 In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² in- ory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for struction for Power-down operations and instructions to...
  • Page 51 HT82B60R Mnemonic Description Cycles Flag Affected Rotate RRA [m] Rotate Data Memory right with result in ACC None Note RR [m] Rotate Data Memory right None RRCA [m] Rotate Data Memory right through Carry with result in ACC Note RRC [m]...
  • Page 52: Instruction Definition

    HT82B60R Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ¬ ACC + [m] + C...
  • Page 53 HT82B60R CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then in- crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address.
  • Page 54 HT82B60R CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ¬ [m] Operation Affected flag(s) CPLA [m]...
  • Page 55 HT82B60R INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. [m] ¬ [m] + 1 Operation Affected flag(s) INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu- lator.
  • Page 56 HT82B60R OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²OR² x Operation Affected flag(s)
  • Page 57 HT82B60R RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0.
  • Page 58 HT82B60R SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
  • Page 59 HT82B60R SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.
  • Page 60 HT82B60R SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 « [m].7 ~ [m].4 Operation Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
  • Page 61 HT82B60R TABRDC [m] Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM code TBHP is enabled) Description The low byte of ROM code addressed by the table pointers (TBLP and TBHP) is moved to the specified data memory and the high byte transferred to TBLH directly.
  • Page 62: Package Information

    HT82B60R Package Information 20-pin SSOP (150mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. ¾ 0.228 0.244 ¾ 0.150 0.158 ¾ 0.008 0.012 ¾ 0.335 0.347 C¢ ¾ 0.049 0.065 ¾ ¾ 0.025 ¾ 0.004 0.010 ¾ 0.015 0.050 ¾...
  • Page 63 HT82B60R 28-pin SSOP (150mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. ¾ 0.228 0.244 ¾ 0.150 0.157 ¾ 0.008 0.012 ¾ C¢ 0.386 0.394 ¾ 0.054 0.060 ¾ ¾ 0.025 ¾ 0.004 0.010 ¾ 0.022 0.028 ¾ 0.007 0.010...
  • Page 64 HT82B60R 48-pin SSOP (300mil) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. ¾ 0.395 0.420 ¾ 0.291 0.299 ¾ 0.008 0.012 ¾ C¢ 0.613 0.637 ¾ 0.085 0.099 ¾ ¾ 0.025 ¾ 0.004 0.010 ¾ 0.025 0.035 ¾ 0.004 0.012...
  • Page 65 HT82B60R SAW Type 32-pin (5mm´5mm) QFN Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. ¾ 0.028 0.031 ¾ 0.000 0.002 ¾ ¾ 0.008 ¾ 0.007 0.012 ¾ ¾ 0.197 ¾ ¾ 0.197 ¾ ¾ 0.020 ¾ 0.049 0.128 ¾...
  • Page 66 HT82B60R 48-pin LQFP (7mm´7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. ¾ 0.350 0.358 ¾ 0.272 0.280 ¾ 0.350 0.358 ¾ 0.272 0.280 ¾ ¾ 0.020 ¾ ¾ 0.008 ¾ 0.053 0.057 ¾ ¾ 0.063 ¾ ¾ 0.004 ¾...
  • Page 67 HT82B60R Product Tape and Reel Specifications Reel Dimensions SSOP 20S (150mil), SSOP 28S (150mil) Symbol Description Dimensions in mm Reel Outer Diameter 330.0±1.0 Reel Inner Diameter 100.0±1.5 +0.5/-0.2 13.0 Spindle Hole Diameter Key Slit Width 2.0±0.5 +0.3/-0.2 16.8 Space Between Flange Reel Thickness 22.2±0.2...
  • Page 68 HT82B60R Carrier Tape Dimensions SSOP 20S (150mil) Symbol Description Dimensions in mm +0.3/-0.1 Carrier Tape Width 16.0 Cavity Pitch 8.0±0.1 Perforation Position 1.75±0.10 Cavity to Perforation (Width Direction) 7.5±0.1 +0.1/-0.0 Perforation Diameter +0.25/-0.00 Cavity Hole Diameter 1.50 Perforation Pitch 4.0±0.1 Cavity to Perforation (Length Direction) 2.0±0.1...
  • Page 69 HT82B60R SSOP 48W Symbol Description Dimensions in mm Carrier Tape Width 32.0±0.3 Cavity Pitch 16.0±0.1 Perforation Position 1.75±0.10 Cavity to Perforation (Width Direction) 14.2±0.1 Perforation Diameter 2 Min. +0.25/-0.00 Cavity Hole Diameter 1.50 Perforation Pitch 4.0±0.1 Cavity to Perforation (Length Direction) 2.0±0.1...
  • Page 70 Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as- sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used...

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