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LSI L80225 Technical Manual

10/100 mbpstx/10bt ethernet physical layer device phy
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L80225 10/100 MbpsTX/10BT
Ethernet Physical Layer Device
(PHY)
Technical Manual
Features
•
Single Chip 100Base-TX /10Base-T
physical layer solution
•
Dual Speed - 10/100 Mbps
•
Half and Full Duplex
•
MII interface to Ethernet Controller
•
MI interface for configuration & status
•
Optional Repeater Interface
•
AutoNegotiation: 10/100, Full/Half
Duplex
•
Meets all applicable IEEE 802.3
standards
•
Advertisement control through pins
•
Adaptive Equalizer
- - - - - - - - - - - - - - - - - - - - - 2
- - - - - - - - - - - - - - - - - - 4
- - - - - - - - - - - - - - - - - - - 8
Description- - - - - - - - - - - - - - -43
MD400182/B
April, 2002
Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
Contents
- - - - - - - - - - - - - 9
Note:
Check for the latest revision of this document before start-
ing any designs. This document is available on the Web, at
www.lsilogic.com
•
On-chip wave shaping - no external filters
required
•
Baseline Wander Correction
•
LED outputs
-
Link
-
Activity
-
Collision
-
Full Duplex
-
10/100
•
Few external components
•
3.3 V supply with 5 V tolerant I/O
•
44 PLCC
- - - - - - - - - - - - - - - - - - - 65
- - - - - - - - - - - - - - - - - 84
- - - - - - - - - - - - 51
- - - - - - - - - - - - - - 84
- - - - - - - - - - - 87
1 of 88
®

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Summary of Contents for LSI L80225

  • Page 1: Table Of Contents

    - - - - - - - - - - - 87 Note: Check for the latest revision of this document before start- ing any designs. This document is available on the Web, at www.lsilogic.com MD400182/B April, 2002 1 of 88 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.

  • Page 2: Description

    Description The L80225 is a highly integrated analog interface IC for twisted pair Ethernet applications. The L80225 can be configured for either (100Base-TX) or 10 Mbps (10Base- T) Ethernet operation. The L80225 consists of 4B5B/Manchester encoder/decoder, scrambler/descrambler, transmitter with wave shaping and output driver,...
  • Page 3 REXT LA_LED/(MDA3) RESET GND3 OSCIN VDD2 GND4 L80225 SPEED TX_EN 44 Pin PLCC TX_ER Top View MDIO TXD3 TXD2 TXD1 RX_DV TXD0 RX_ER TX_CLK Description 3 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.

  • Page 4: Pin Description

    TX_CLK when TX_EN is asserted. 4 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 5 During powerup or reset, this pin is high impedance and the value on this pin is latched in as the physical device address MDA2 for the MI serial port. Pin Description 5 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 6 ANEG = 0. When ANEG = 1, this pin controls the Half/Full Duplex advertisement abilities. 1 = Full Duplex 0 = Half Duplex 6 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 7 AutoNegotiate and Advertise 10/100 M Half Duplex only RESET RESET Input Pullup 1 = Normal Operation 0 = Device Reset Pin Description 7 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.

  • Page 8: Block Diagram

    2 Block Diagram Figure 1 Block Diagram REXT 100BASETX Transmitter OSCIN Oscillator Switched TPO+ 4B5B MLT3 Scrambler Current Encoder Encoder Filter TPO− RESET Sources RX_EN Clock RPTR Generator ANEG DPLX 10BaseT Transmitter SPEED Manchester − Encoder Filter TX_CLK TXD[3:0] Clock TX_EN Generator TX_ER...

  • Page 9: Functional Description

    3 Functional Description 3.1 General The L80225 is a complete 100/10 Mbps Ethernet Media Interface IC. The L80225 has nine main sections: controller interface, encoder, decoder, scrambler, descrambler, clock and data recovery, twisted pair transmitter, twisted pair receiver, and MI serial port. A block diagram is shown in...
  • Page 10 [ DATA ] Encoding [ 1 1 ] With No MID Bit SOI = Transition 10 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 11 2. 1st SFD nibble received. 3. 1st data nibble received. 4. D0 thru D7 are the first 8 bits of the data field. Functional Description 11 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 12 Each block plus the operating modes are described in more detail in the following sections. Since the L80225 can operate as either a 100Base- TX or a 10Base-T device, each of the following sections describes the performance of the respective section in both the 100 and 10 Mbps modes.
  • Page 13 Figure 3. The L80225 meets all the MII requirements outlined in IEEE 802.3. The L80225 can directly connect, without any external logic, to any Ethernet controllers or other devices which also complies with the IEEE 802.3 MII specifications. The MII frame format is shown in...
  • Page 14 RXD[3:0]. The collision output, COL, is asserted whenever the collision condition is detected. 14 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 15 TP output is high impedance. If the MI address lines, MDA[3:0], are pulled high during reset or powerup, the L80225 powers up and resets with the MII disabled. Otherwise, the L80225 powers up and resets with the MII enabled.
  • Page 16 IEEE 802.3. This guarantees that a transition always occurs in the middle of the bit cell. The Manchester encoder on the L80225 converts the 10 Mbps NRZ data from the controller interface into a Manchester Encoded data stream for the TP transmitter and adds a start of idle pulse (SOI) at the end of the packet as specified in IEEE 802.3 and shown in...
  • Page 17 Data F 11101 1111 Idle 11111 0000 SSD #1 11000 0101 SSD #2 10001 0101 ESD #1 01101 0000 ESD #2 00111 0000 Functional Description 17 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 18 5B nibbles to the 4B code words is specified in IEEE 802.3 and shown in Table 2. The 4B45 decoder on the L80225 takes the 5B code words from the descrambler, converts them into 4B nibbles per Table and sends the 4B nibbles to the controller interface.
  • Page 19 Mbps mode. As mentioned in the Manchester Decoder section, the data recovery process inherently performs decoding of Manchester encoded data from the TP inputs. Functional Description 19 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 20 3.7.1 100 Mbps 100Base-TX requires scrambling to reduce the radiated emissions on the twisted pair. The L80225 scrambler takes the encoded data from the 4B5B encoder, scrambles it per the IEEE 802.3 specifications, and sends it to the TP transmitter.
  • Page 21 DAC at high speed by the clock generator. In this way, the waveform generator preshapes the Functional Description 21 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 22 The TX receiver consists of an adaptive equalizer, baseline wander correction circuit, comparators, and MLT-3 decoder. The TP inputs first 22 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 23 100 Mbps TP squelch is one of the criteria used to determine link integrity. The squelch comparators compare the TP inputs against fixed positive and negative thresholds, called squelch levels. Functional Description 23 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 24 If the data is invalid, the receiver is in the squelched state. If the input voltage 24 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 25 The collision function is disabled if the device is in the Full Duplex mode or is in the Link Fail state, or if the device is in the diagnostic loopback mode. Functional Description 25 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 26 Between packets, the receiver will be detecting the idle pattern, which is 5B /I/ symbols. While in the idle state, CRS and RX_DV are deasserted. 26 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 27 3.1 V Slope 0.5 V/ns 585 mV 585 mV sin (π ∗ t/PW) 585 mV sin [2 π (t − PW2)/PW] PW/4 3PW/4 Functional Description 27 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 28 RX_ER is asserted for the nibble associated with the first /I/ symbol detected and then CRS and RX_DV are deasserted. 28 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 29 CRS and RX_DV are deasserted. 3.14 Link Integrity & Autonegotiation 3.14.1 General The L80225 can be configured to implement either the standard link integrity algorithms or the AutoNegotiation algorithm. The standard link integrity algorithms are used solely to establish an active link to and from a remote device.
  • Page 30 FLP's, to pass up to 16 bits of signaling data back and forth between the L80225 and a remote device. The transmit FLP pulses meet the template specified in IEEE 802.3 and shown in...
  • Page 31 L80225 then configures itself for either 10 or 100 Mbps mode and either Full or Half Duplex modes (depending on the outcome of the negotiation process), and it switches to either the 100Base-TX or 10Base-T link integrity algorithms (depending on which mode was enabled by AutoNegotiation).
  • Page 32 0 ≤ t ≤ 0.25 BT and 2.25 ≤ t ≤ 2.5 BT −3.1 V 2.5 BT 4.5 BT 32 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 33 If either 3 consecutive link pulses or one SOI pulse indicates incorrect polarity on the TP receive input, the polarity is internally determined to be incorrect. The L80225 will automatically correct for the reverse polarity. 3.17 Full Duplex Mode 3.17.1 100 Mbps Full Duplex mode allows transmission and reception to occur simultaneously.
  • Page 34 MI serial port Control register or by appropriately asserting the SPEED pin assuming AutoNegotiation is not enabled. 34 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 35 A diagnostic loopback mode can also be selected by setting the loopback bit in the MI serial port Control register. When diagnostic loopback is Functional Description 35 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 36 50 ms after the reset was initiated. 3.21 Oscillator The L80225 requires a 25 MHz reference frequency for internal signal generation. This 25 MHz reference frequency is generated by either connecting an external 25 MHz crystal between OSCIN and GND or by applying an external 25 MHz clock to OSCIN.
  • Page 37 10 Mb Mode Enabled (High), or 100 Mb Mode Enabled (Low) 3.23 Repeater Mode The L80225 has one predefined repeater mode which can be enabled by asserting the RPTR pin. When this repeater mode is enabled with the RPTR pin, the device operation is altered as follows: (1) TX_EN to CRS loopback is disabled.
  • Page 38 After R/LT bits are read, they are updated to their current value. R/LT bits can 38 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 39 01 for the serial port cycle to continue. The next 2 bits are Functional Description 39 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 40 REGAD[4:0]=11111) come from the specific data register designated by the register address bits REGAD[4:0]. 3.24.5 Register Structure The L80225 has six internal 16 bit registers. A map of the registers is shown in Table The L80225 supports only the six registers mandated by the IEEE 802.3 specification.
  • Page 41 Figure 9 MI Serial Port Frame Timing Diagram WRITE Cycle MDIO D15 D14 D13 D12 D11 D10 D9 D1 D0 ST[1:0] OP[1:0] PHYAD[4:0] REGAD[4:0] TA[1:0] DATA[15:0] WRITE Bits PHY Clocks In Data on Rising Edges of MDC READ Cycle MDIO D15 D14 D13 D12 D11 D7 D6 ST[1:0] OP[1:0]...
  • Page 42 Interrupt MDIO High-Z of Read Cycle Pulse Pulled High Externally MDIO High-Z Pulled High Externally 42 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.

  • Page 43: Register Description

    These 16 bits contain data to/from one of the eleven reg- isters selected by register address bits REGAD[4:0]. IDLE is shifted in first Register Description 43 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 44 1. If MDA[3:0] not = 1111, then the MII_DIS default value is changed to 0. x.15 Bit Is Shifted First 44 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 45 Interrupt Detect bit 18.15 or AutoNegotiation Remote Fault bit 5.13 is set. 0 = No Remote Fault CAP_ANEG AutoNegotiation 1 = Capable of AutoNegotiation Operation Capable Register Description 45 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 46 OUI9 OUI10 OUI11 OUI12 OUI13 OUI14 OUI15 OUI16 OUI17 OUI18 x.15 Bit Is Shifted First 46 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 47 Manufacturer's Part Number PART4 PART3 PART2 PART1 PART0 REV3 Manufacturer's Revision Number – REV2 – REV1 – REV0 – x.15 Bit Is Shifted First Register Description 47 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 48 0 = Not Capable 1. Next Page is currently not supported. x.15 Bit Is Shifted First 48 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 49 0 = Not Capable Reserved thru CSMA CSMA 802.3 1 = Capable of 802.3 CSMA Operation Capable 0 = Not Capable x.15 Bit Is Shifted First Register Description 49 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 50 Reserved for factory use R/LT 18.4 18.3 Reserved for factory use thru 18.0 x.15 Bit Is Shifted First 50 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.

  • Page 51: Application Information

    5 Application Information 5.1 Example Schematics A typical example schematic of the L80225 used in an adapter card application is shown in Figure 11, a hub application is shown in Figure 12, and an external PHY application is shown in Figure 5.2 TP Transmit Interface...
  • Page 52 RJ45 to chassis ground through 75 Ohm resistors and a 0.01 µF capacitor, as shown in Figure Figure 12, and Figure 52 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 53 Optional LA_LED TPI− C_LED FD_LED L_LED REXT Ω OSCIN 10 K 25 MHz SPEED PINSTRAP DPLX to VDD or GND ANEG GND [6:1] Application Information 53 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 54 SPEED PINSTRAP DPLX to VDD or GND ANEG 25 MHz CSCIN System Clock GND [6:1] 54 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 55 TPI− C_LED FD_LED L_LED REXT Ω OSCIN 10 K 25 MHz System Clock SPEED PINSTRAP DPLX to VDD or GND ANEG GND [6:1] Application Information 55 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 56 = 32.6 mA (100 Mbps, STP) = 100 mA (10 Mbps, UTP) = 81.6 mA (10 Mbps, STP) 56 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 57 If a nonstandard controller or other digital device is used to interface to the L80225, there might be a need to clock TXD[3:0] into the L80225 on the edges of an external master clock. The master clock, in...
  • Page 58 L80225. This can be done by using OSCIN as the master clock input; since OSCIN generates TX_CLK inside the L80225, data on TXD[3:0] can be clocked into the L80225 on edges of output clock TX_CLK or input clock OSCIN. In the case where OSCIN is used as the input clock, a crystal is no longer needed on OSCIN, and TX_CLK can be left open or used for some other purpose.
  • Page 59 RX_EN is deasserted, RX_CLK, RXD[3:0], RX_DV, RX_ER, and COL are placed in high impedance. RX_EN can be used to "wire OR" the outputs of many L80225 devices in multiport applications where only one device may be receiving at a time, like a repeater. By monitoring CRS from each individual port, the repeater can assert only the one RX_EN to that L80225 device which is receiving data.
  • Page 60 The MII signal count to a repeater core will be 16 multiplied by the number of ports, which can be quite large. The signal count between the L80225 and repeater core can be reduced by 8 per device by sharing the receive output pins and using RX_EN to enable only that port where CRS is asserted.
  • Page 61 5.8 Serial Port 5.8.1 General The L80225 has a MI serial port to access the device’s configuration inputs and read out the status outputs. Any external device that has a IEEE 802.3 compliant MI interface can connect directly to the L80225...
  • Page 62 Link, Full Duplex, and Collision LED pins to be used as digital outputs under normal conditions. Note that the MDA[3:0] addresses are inverted inside the L80225 before going to the MI serial port block. This means that the MDA[3:0] pins would have to be pin strapped to 1111 externally in order to successfully match the MI physical address bits PHYAD[4:0]=00000 internally.
  • Page 63 5.9 Oscillator The L80225 requires a 25 MHz reference frequency for internal signal generation. This 25 MHz reference frequency can be generated by either connecting an external 25 MHz crystal between OSCIN and GND or by applying an external 25 MHz clock to OSCIN.
  • Page 64 50 mVpp of each other, and (3) All GNDs should be within 50 mVpp of each other. 64 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.

  • Page 65: Specifications

    Volt All except OSCIN, MDA[3:0], VDD-1.0 Volt MDA[3:0] Volt OSCIN Input High Voltage Volt All except OSCIN, MDA[3:0], VDD -0.5 Volt MDA[3:0] Volt OSCIN Specifications 65 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 66 1. IGND includes current flowing into GND from the external resistors and transformer on TPO as shown in Figure 66 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 67 10 Mbps, NLP and FLP Link Pulse Voltage Template TP Differential Output 10 Mbps. Measured on secondary Idle Voltage side of Xfmr in Figure 11. Specifications 67 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 68 0.25 GND. Range TP Input Differential Volt Voltage Range TP Input Resistance TP Input Capacitance 68 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 69 Clock applied to OSCIN OSCIN High Time Clock applied to OSCIN OSCIN Low Time Clock applied to OSCIN OSCIN to TX_CLK 100 Mbps Delay 10 Mbps Specifications 69 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 70 TX_ER Setup Time Note 1 TX_ER Hold Time Transmit Propagation Delay 100 Mbps, MII 10 Mbps 70 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 71 Figure 17 Transmit Timing - 100 Mbps MII 100 Mbps TX_CLK TX_EN TXD[3:0] TX_ER TPO± IDLE IDLE /J/K/ DATA /T/R/ IDLE FXO± LA_LED Specifications 71 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 72 End Of Packet To RX_DV 100 Mbps Deassert Delay 1000 10 Mbps. relative to start of SOI pulse 72 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 73 RX_CLK, RXD, CRC, RX_DV, RX_ER Output Rise and Fall Times RX_EN Deassert to Rcv MII Output HI-Z Delay RX_EN Assert to Rcv MII Out- put Active Delay Specifications 73 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 74 MII 100 Mbps TPI± DATA FXI± RX_CLK RX_DV RXD[3:0] DATA DATA DATA DATA DATA DATA DATA 74 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 75 Receive Timing, End of Packet - 10 Mbps MII 10 Mbps TPI± DATA DATA DATA DATA DATA RX_CLK RX_DV RXD[3:0] DATA DATA DATA DATA DATA DATA DATA Specifications 75 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 76 C_LED Collision Test Assert Time 5120 Collision Test Deassert Time COL Rise and Fall Time 76 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 77 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA FXO± TPI± DATA DATA DATA DATA C_LED MII 10 Mbps TPO± TPI± C_LED Specifications 77 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 78 DATA FXO± C_LED MII 10 Mbps TPI± TPO± C_LED Figure 26 Collision Test Timing TX_EN 78 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 79 FLP Receive Link Pulse Maxi- data_detect_max_timer mum Period Required For Data Pulse Detection FLP Receive Link Pulses Link Required To Detect Valid FLP Pulses Burst Specifications 79 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 80 Figure 27 NLP Link Pulse Timing a. Transmit NLP TPO± b. Receive NLP TPI± PLED 80 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 81 Refer to Figure 29 for Timing Diagram. Limit Sym. Parameter Unit Conditions Jabber Activation Delay Time 10 Mbps Jabber Deactivation Delay Time 10 Mbps Specifications 81 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 82 MDIO Active To HI-Z Delay Read-Write bit transition Frame Delimiter (Idle) Clocks # of consecutive MDC clocks with MDIO=1 82 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 83 Figure 30 MI Serial Port Timing MDIO REGAD0 (READ) MDIO REGAD0 (WRITE) Specifications 83 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.

  • Page 84: Ordering Information

    Link Pass, 1, has been changed to 1 = 10 Mbit Mode Detected • Pin # 23; I Pulldown has been changed to I. 84 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 85 Table 12 has been added to the Data Sheet page Table 14 TP Transformer Sources • Vendor BEL, Part Number is now, S558-5999-J9, 558-5999-46 Revision History 85 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 86 Figure 27 in previous version of document.) • Updated all section, table, and figure cross-references throughout the document. 86 of 88 L80225 10/100 Mbps Ethernet Physical Layer Device - Technical Manual April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.

  • Page 87: Surface Mount Packages

    3. Formed leads shall be planar with respect to one another within 0.004 inches. Important: This drawing may not be the latest version. Surface Mount Packages 87 of 88 April, 2002 Copyright © 1999-2002 by LSI Logic Corporation. All rights reserved.
  • Page 88 Fax: 81.3.5463.7820 Visit us at our web site: http://www.lsilogic.com ISO 9000 Certified The LSI Logic logo design is a registered trademark of LSI LSI Logic Corporation reserves the right to make changes Logic Corporation. All other brand and product names may to any products and services herein at any time without be trademarks of their respective companies.

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