Kenwood TS-440S Service Manual page 15

4) Speech processor
IC4 in the IF u nit functio ns as the first stage mic rophone am­
plifier or a u dio speech processo r . When the processor switch
is off, IC 4 f u n ctions as a 20 d B micropho n e am plifier. Whe n
the processor switch is on, IC 4 f u n ctio n s as an u p to 40 d B
MIC
4. PLL Circuits
Theory of PLL circ u it o perations
The TS -440 PLL circuit u s e s a refe rence freq uency o f 3 6 MHz
a n d consists of five PLL loops covering the range of freq u e n­
cies from 30 kHz to 30 MHz in 1 0 Hz ste p s . The P L L circuit
has an IF shift f u n ction which is implemented by i n s e rtin g
ca rrier frequencies between PLL loops . The PLL l o o p s inclu de
a ca rrier circ uit PLL loop a n d a n H ET ci rcuit P L L loop which
g e n erates a constant freq u e n cy of 36. 22 MHz . F r e q u e n cy
division for these PLL loops is controlled by the mic roproces­
sor. In all PLL loops phase compa rison is made using the refer­
ence freq u e n cy fsrn (frequency control using a single crystal
oscillator) .
Fig u re 1 2 i s the P L L circuit block diagram.
The refere n c e freq u e n cy (fsrn) is g e n e rated by a 36 MHz
c rystal oscillator a n d 0 2 1 ( 2 S C 2787) . R efere n c e freq u e n cy
sig n als a re fed into the main loop ' s IC 1 1 ( S N 1 69 1 3P) via a
buffer consisting 0 2 2 a n d 0 2 3 ( 2 S C 2668). The sig nal is also
fed into IC 1 3 (S N74S 1 1 2) via a b uffe r consisting of 024
( 2 S C 2668). In IC 1 3, the sig n als a re freq u e n cy divided to
g e n e rate a 9 MHz sig n al. The 9 MHz sig nal is used as the
reference fre q u e n cy sig n als for the P L L loops .
CIRCUIT DESCRIPTION
PROCESSOR OFF G AI N
0 N MAX GAIN 40dB
IC4: JJPC1158H2
COMP. LEVEL
ALC
041 DTCI 14ES
r ----,
I
I
...
I
Fig . 1 1
•
g ain amp lifier with A LC . When the processor s witch is o n,
8 VDC is s u p plied to the base of the g ain adju stment switch­
ing transisto r, 04 1 , d riving the feed back amp lifier.
20dB
SSB M IC GAIN
V R6
P L L 5
P L L 5 consists of IC 1 8 ( M N6 1 4 7) a n d its associated loop
compo n e nts . VC 0 5, 0 36 (2SK 1 9 2A), is locked at a fre­
q u e n cy of 36 . 2 2 MHz . The 9 MHz refe rence freq u e n cy
sig nal is supplied to pin 3 of IC 1 8, whe re the sig nal is divid­
ed by 1 800 ( 4 5 0 in FM mode) to g e n e rate a 5 kHz ( 2 0
kHz in F M mode) sig nal u s e d f o r comparison . VC 0 5 ' s out­
put sig n a l is s u p plied to IC 1 8 pin 1 6 via 0 37 ( 2S C 266 8),
where the sig n als a re fre q u e n cy divided by 7244 ( 1 8 1 1
in F M mode). The phase of the sig nal is the n compared
with that of the 5 kHz ( 2 0 kHz in F M mode) sig nal by the
phase compa rato r a n d the VC 0 5 oscillation freq u e n cy is
locked . F r e q u e n cy division d ata is s u p plied by digit a l u nit
(DAO to D A 3 a n d C K 4) .
As described a bove, the dividing ratio used varies depend­
ing o n which mode the TS -440 is in, FM mode o r S S B .
This is beca u s e the a p p a rent time c o n stant is i n c reased
without cha n ging the active L PF constant so that the PLL
sig n als c a n b e mod ulated e a sily a n d r e d u cing distortio n
d u ring F M t r a n smissio n . In m o d e s other tha n F M, the
amount of fre q u e n cy shift d u e to mechanical vibrations
is red u ced because the apparent time constant is reduced .
The output from PLL5 g oes through buffer 0 3 8 (2SC 2668)
a n d L PFs, a n d is used as the H ET sig n a l in the R F u nit.
JS-440S
IF UN IT
P RS BV
1 5