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Summary of Contents for AHA StarLite AHA3431
- Page 1 Product Specification AHA3431 StarLite 40 MBytes/sec Simultaneous Compressor/Decompressor IC, 3.3V 2365 NE Hopkins Court Pullman, WA 99163-5601 tel: 509.334.1000 fax: 509.334.9000 e-mail: sales@aha.com www.aha.com advancedhardwarearchitectures PS3431-0500...
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Page 2: Table Of Contents
Advanced Hardware Architectures, Inc. Table of Contents 1.0 Introduction ................1 1.1 Conventions, Notations and Definitions. - Page 3 Advanced Hardware Architectures, Inc. 4.18 Decompression Line Length, Address 0x1C, 0x1D - Read/Write ....... . 25 4.19 Compression Record Count, Address 0x20, 0x21 - Read/Write .
- Page 4 Advanced Hardware Architectures, Inc. Figures Figure 1: Functional Block Diagram ............. . 2 Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”) .
- Page 5 Advanced Hardware Architectures, Inc. Tables Table 1: Data Bus and FIFO Sizes Supported by AHA3431 ......... . . 2 Table 2: AHA3431 Connection to Host Microprocessors.
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Page 6: Introduction
Advanced Hardware Architectures, Inc. INTRODUCTION least significant bit. For example, VOD[7:0] indicates signal names VOD7 through VOD0. – A logical “AND” function of two signals is AHA3431 is a lossless compression expressed with an “&” between variables. coprocessor IC for hardcopy systems on many –... -
Page 7: Functional Overview
Advanced Hardware Architectures, Inc. Figure 1: Functional Block Diagram DATA PORT CONTROL (From Scanner) VIREQN COEORN VID[7:0] PORT COEOTN FIFO FIFO COMPRESSOR VIACKN 16x32 16x32 D[31:0] DATA PORT DRIVEN (To Printer) VOEOTN VOEORN FIFO FIFO DECOMPRESSOR VOREQN PORT 16x32 16x32 VOD[7:0] VOACKN AHA3431... -
Page 8: System Configuration
All register accesses to AHA3431 are For additional notes on interfacing to various performed on the 8-bit PD bus. The PD bus is the microprocessors, refer to AHA Application Note lowest byte of the 32-bit microprocessor bus. (ANDC16), Designer’s Guide for StarLite... -
Page 9: Figure 2: Microprocessor Port Write (Procmode[1:0]="01")
Advanced Hardware Architectures, Inc. Table 3: Microprocessor Port Configuration PROCMODE[1:0] CYCLE LENGTH EXAMPLE PROCESSOR Active high write fixed i960 Active low write fixed Active high write variable Active low write variable 68xxx, MIPS R3000 Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”) CLOCK PA[5:0] PD[7:0]... -
Page 10: Figure 4: Microprocessor Port Write (Procmode[1:0]="11")
Advanced Hardware Architectures, Inc. Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”) CLOCK PA[5:0] PD[7:0] RDYN Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”) CLOCK PA[5:0] PD[7:0] RDYN PS3431-0500 Page 5 of 50... -
Page 11: Functional Description
Advanced Hardware Architectures, Inc. FUNCTIONAL DESCRIPTION DMA MODE On the rising edge of CLOCK when the strobe This section describes the various data ports, condition is met, the port with the active special handling, data formats and clocking acknowledge either strobes data into or out of the structure. -
Page 12: Figure 6: Dma Mode Timing For Single Word Writes, Strobe Condition Of Dsc=100
Advanced Hardware Architectures, Inc. Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100 CLOCK ACKN DRIVEN Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100 CLOCK ACKN DRIVEN Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=100 CLOCK ACKN... -
Page 13: Figure 9: Dma Mode Timing For Four Word Burst Read, One Wait State, Strobe Condition Of Dsc=100
Advanced Hardware Architectures, Inc. Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=100 CLOCK ACKN DRIVEN Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=100 CLOCK ACKN DRIVEN... -
Page 14: Pad Word Handling In Burst Mode
Input FIFO Threshold and Output FIFO Threshold programming threshold values. Refer to Section 4.0 registers. By requesting only when a FIFO can of AHA Application Note (ANDC16), Designer’s sustain a certain burst size, the bus is used more Guide for StarLite Family Products for a more efficiently. -
Page 15: Request During An End-Of-Record
Advanced Hardware Architectures, Inc. Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO) CLOCK CIACKN CIREQN Threshold Counter Note: CIREQN deasserted when threshold counter exceeds IFT=4, but additional words are reading as long as ACKN is asserted. Figure 13: Request vs. -
Page 16: Data Format
Advanced Hardware Architectures, Inc. DATA FORMAT 3.6.2 COMPRESSION OUTPUT AND PAD BYTES The width of the D bus is selected with the If a record ends on a byte other than the last byte WIDE bit in System Configuration 0. If WIDE=1, in a word, the final word contains 1, 2 or 3 pad bytes. -
Page 17: Video Interfaces
Advanced Hardware Architectures, Inc. Figure 14: Timing Diagram, Video Input CLOCK VIREQN VIACKN don’t don’t VID[7:0] don’t care care care VIDEO INTERFACES VOD[7:0] is valid. An 8-bit word is read each clock when both VOREQN and VOACKN are sampled low on a rising edge of CLOCK. Pad bytes at an end 3.7.1 VIDEO INPUT of record are discarded by the video output port and... -
Page 18: Algorithm
DCOMP is set to zero and DEMP is set to one. The bitonal images. For some comparison data refer to contents of the dictionary are preserved when Compression the AHA Application Note (ANDC13), DCOMP is changed. However, when DPASS is Performance: StarLite : ENCODEB2 on changed, the contents are lost. -
Page 19: Interrupts
Advanced Hardware Architectures, Inc. The lower 3 bytes of both the Compression the compressor. Bit order control allows reversal of Record Length and the Decompression Length the data bits within each byte of data. For example, registers are prearmable. They may be changed and reverse order means bit-7 is swapped with bit-0, bit- the new values loaded into the respective counter at 6 is swapped with bit-1, etc.. -
Page 20: Register Descriptions
Advanced Hardware Architectures, Inc. REGISTER DESCRIPTIONS The microprocessor configures, controls and monitors IC operation through the use of the registers defined in this section. The bits labeled “ ” are reserved and must be set to zero when writing to registers unless otherwise noted. - Page 21 Advanced Hardware Architectures, Inc. DEFAULT ADDRESS R/W DESCRIPTION FUNCTION AFTER PREARM RSTN Pause on Record Boundaries, Enable Decompression Engine, Decompression 0x18 R/W Decompression Control 0x04 Engine Empty Status, Dictionary Reset, Enable Pass-Through Mode 0x1A R/W Decompression Reserved 1 Reserved 0x00 Line Length Register Lower 0x1C R/W Decompression Line Length 0...
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Page 22: System Configuration 0, Address 0X00 - Read/Write
Advanced Hardware Architectures, Inc. SYSTEM CONFIGURATION 0, ADDRESS 0x00 - READ/WRITE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address REVERSE DECOMP COMP 0x00 WIDE BYTE After reset, its contents are undefined. It must be written before any input or output data movement may be performed. -
Page 23: Input Fifo Thresholds, Address 0X02 - Read/Write
Advanced Hardware Architectures, Inc. VDOE - VDO Port Enable. When this bit is set, the data from the decompression output FIFO goes to the VDO port. When the bit is clear, the decompressed data is read by DMA on the D bus. VDIE - VDI Port Enable. -
Page 24: Decompression Ports Status, Address 0X05 - Read Only
Advanced Hardware Architectures, Inc. CEOR - Compression output end of record. This bit is active when the output FIFO contains the end-of- record code. After reset this bit contains a zero. res - Bits must always be written with zeros. CIEMP - Compression input empty. -
Page 25: Port Control, Address 0X06 - Read/Write
Advanced Hardware Architectures, Inc. PORT CONTROL, ADDRESS 0x06 - READ/WRITE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address 0x06 DORST DIRST CORST CIRST This register is initialized to 0x0F after reset. CIRST - Compression input reset. Setting this bit to a one resets the CI FIFO and clears state machines on the compression input port. -
Page 26: Interrupt Mask 1, Address 0X09 - Read/Write
Advanced Hardware Architectures, Inc. COUF - Compression Output FIFO underflow. This interrupt is generated when a read from an empty CO FIFO is performed. Once this interrupt is set, the CO FIFO must be reset with the CORST bit. The microprocessor must write a one to this bit to clear this interrupt. COREQN is inactive while the interrupt is set. -
Page 27: Decompression Record Length, Address 0X0C, 0X0D, 0X0E, 0X0F - Read/Write
Advanced Hardware Architectures, Inc. 4.11 DECOMPRESSION RECORD LENGTH, ADDRESS 0x0C, 0x0D, 0x0E, 0x0F - READ/WRITE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address 0x0C DRLEN[7:0] 0x0D DRLEN[15:8] 0x0E DRLEN[23:16] 0x0F DRLEN[31:24] These registers are initialized to 0xFF after reset. DRLEN[31:0]-Decompression Record Length. -
Page 28: Compression Control, Address 0X14 - Read/Write
Advanced Hardware Architectures, Inc. 4.13 COMPRESSION CONTROL, ADDRESS 0x14 - READ/WRITE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address 0x14 CPREARM CPOT CPASS CEMP COMP CPOR This register is initialized to 0x04 after reset. CPOR - Compression Pause on record boundaries. When this bit is set to one, the compressor stops taking data from the input FIFO once a record boundary is found. -
Page 29: Compression Line Length, Address 0X16, 0X17 - Read/Write
Advanced Hardware Architectures, Inc. 4.15 COMPRESSION LINE LENGTH, ADDRESS 0x16, 0x17 - READ/WRITE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address 0x16 LINE[7:0] 0x17 LINE[10:8] This register contains information necessary for the compression operation. It must be set prior to any compression operation. -
Page 30: Decompression Reserved, Address 0X1A - Read/Write
Advanced Hardware Architectures, Inc. 4.17 DECOMPRESSION RESERVED, ADDRESS 0x1A - READ/WRITE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address 0x1A This register is used for production testing only. Must be written with zero if at all. Initialized to 0x00 after reset. -
Page 31: Interrupt Mask 2, Address 0X29 - Read/Write
Advanced Hardware Architectures, Inc. 4.21 INTERRUPT MASK 2, ADDRESS 0x29 - READ/WRITE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address 0x29 DEOTM CEOTM This register is initialized to 0xFF after reset. CEOTM - Compression End-of-Transfer Interrupt Mask. When set to a one, prevents Compression End- of-Transfer from causing INTRN to go active. -
Page 32: Pattern, Address 0X35 - Read/Write
Advanced Hardware Architectures, Inc. 4.25 PATTERN, ADDRESS 0x35 - READ/WRITE bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address 0x35 PATTERN[7:0] This register is undefined after reset. PATTERN[7:0]-Pattern is the 8-bit data used to generate blank bands or records. If DBLANK is set, the part outputs this register value repeatedly for the entire record (or band). -
Page 33: Microprocessor Interface
Advanced Hardware Architectures, Inc. MICROPROCESSOR INTERFACE MICROPROCESSOR INTERFACE SIGNAL TYPE DESCRIPTION PD[7:0] Processor Data. Data for all microprocessor reads and writes of registers within AHA3431 are performed on this bus. This bus may be tied to the Data bus, D[31:0], provided microprocessor accesses do not occur at the same time as DMA accesses. -
Page 34: Data Interface
Advanced Hardware Architectures, Inc. DATA INTERFACE DATA INTERFACE SIGNAL TYPE DESCRIPTION D[31:0] Data for all channels is transmitted on this bus. The ACKN is used to distinguish between the four channels. Data being written to AHA3431 is latched on the rising edge of CLOCK when the strobe condition is met. Data setup and hold times are relative to CLOCK. -
Page 35: Video Interface
Advanced Hardware Architectures, Inc. VIDEO INTERFACE VIDEO INTERFACE SIGNAL TYPE DESCRIPTION VIREQN Video Input Request. Active low output indicating that the VDI port is ready to accept another byte on VID[7:0]. VIACKN Video Input Acknowledge. Active low input indicating that VID[7:0] is being driven with a valid byte. -
Page 36: Pinout
Advanced Hardware Architectures, Inc. PINOUT SIGNAL SIGNAL SIGNAL VID[4] VOD[7] VID[3] COEORN VID[2] VID[1] CLOCK VID[0] VOACKN INTRN TEST0 PA[0] PA[1] DRIVEN PA[2] D[15] PA[3] DOACKN D[16] COACKN D[17] PA[5] DIACKN D[18] CIACKN D[19] PA[4] D[20] COEOTN D[21] VOEOTN DOREQN D[22] PROCMODE[1] COREQN... -
Page 37: Figure 16: Pinout
Advanced Hardware Architectures, Inc. Figure 16: Pinout PA[5] D[24] PA[4] D[23] COEOTN D[22] VOEOTN D[21] PROCMODE[1] D[20] PROCMODE[0] D[19] D[18] D[17] D[16] D[15] RSTN PD[7] PD[6] PD[5] CLOCK PD[4] AHA3431 StarLite PD[3] PD[2] PD[1] TEST1 PD[0] D[14] D[13] D[12] RDYN VIACKN VID[7] D[11]... -
Page 38: Dc Electrical Specifications
Advanced Hardware Architectures, Inc. DC ELECTRICAL SPECIFICATIONS OPERATING CONDITIONS OPERATING CONDITIONS SYMBOL PARAMETER UNITS NOTES Supply voltage Supply current (active) Supply current (typical) 1, 4 Supply current (static) 2, 4 ° C Ambient temperature Input low voltage Vss-0.3 Input high voltage Vdd+0.3 µA Input leakage current... -
Page 39: Ac Electrical Specifications
Advanced Hardware Architectures, Inc. AC ELECTRICAL SPECIFICATIONS Notes: Production test condition is 50 pF. All timings are referenced to 1.4 volts. Figure 17: Data Interface Timing CLOCK ACKN, Valid REQN D, COEORN, Valid 0 Valid 1 COEOTN Table 6: Data Port Timing Requirements NUMBER PARAMETER UNITS... -
Page 40: Figure 19: Request Deasserts At Eor, Strobe Condition Of Dsc=0-3, 6-7; Erc=1
Advanced Hardware Architectures, Inc. Figure 19: Request Deasserts at EOR, Strobe Condition of DSC=0-3, 6-7; ERC=1 CLOCK ACKN REQN EOR-1 Figure 20: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=0 CLOCK ACKN REQN EOR-1 Figure 21: Request Deasserts at EOR, Strobe Condition of DSC=4 or 5; ERC=1 CLOCK ACKN REQN... -
Page 41: Figure 22: Output Enable Timing
Advanced Hardware Architectures, Inc. Table 7: Request vs. EOR Timing NUMBER PARAMETER UNITS ACKN, SD to REQN ERC=0 CLOCK to REQN ERC=0 CLOCK to REQN DSC=0-3, 6, 7; ERC=1 CLOCK to REQN DSC=4, 5; ERC=0 CLOCK to REQN DSC=4, 5; ERC=1 Figure 22: Output Enable Timing CLOCK ACKN... -
Page 42: Figure 24: Video Output Port Timing
Advanced Hardware Architectures, Inc. Figure 24: Video Output Port Timing CLOCK VOREQN VOACKN VOD[7:0] VOEORN, VOEOTN Table 10: Video Output Port Timing Requirements NUMBER PARAMETER UNITS VOREQN delay VOREQN hold VOACKN setup VOACKN hold VOD delay VOD hold VOEORN, VOEOTN hold VOEORN, VOEOTN delay Figure 25: Microprocessor Interface Timing (PROCMODE[1]=0) CLOCK... -
Page 43: Figure 26: Microprocessor Interface Timing (Procmode[1]=1)
Advanced Hardware Architectures, Inc. Figure 26: Microprocessor Interface Timing (PROCMODE[1]=1) CLOCK RDYN READ tristate Valid WRITE Valid Table 11: Microprocessor Interface Timing Requirements NUMBER PARAMETER UNITS PA setup time PA hold time CSN setup time CSN hold time CSN to valid RDYN RDYN valid delay RDYN drive disable DIR setup time... -
Page 44: Figure 27: Interrupt Timing
Advanced Hardware Architectures, Inc. Figure 27: Interrupt Timing CLOCK INTRN Table 12: Interrupt Timing Requirements NUMBER PARAMETER UNITS INTRN delay time INTRN hold time Figure 28: Clock Timing 2.0V 1.4V 0.8V Table 13: Clock Timing Requirements NUMBER PARAMETER UNITS CLOCK rise time CLOCK fall time CLOCK high time CLOCK low time... -
Page 45: Package Specifications
Advanced Hardware Architectures, Inc. PACKAGE SPECIFICATIONS A2 A DETAIL A E1 E (LCA) (LCB) JEDEC outline is MO-108 Page 40 of 50 PS3431-0500... -
Page 46: Ordering Information
Advanced Hardware Architectures, Inc. PLASTIC QUAD FLAT PACK PACKAGE DIMENSIONS NUMBER OF PIN AND SPECIFICATION DIMENSION SYMBOL (LCA) (LCB) 4.07 0.25 0.33 3.37 30.95 31.2 31.45 27.99 28.12 30.95 31.2 31.45 27.99 28.12 0.73 0.88 1.03 0.35 10.0 ORDERING INFORMATION 10.1 AVAILABLE PARTS PART NUMBER DESCRIPTION... -
Page 47: Related Technical Publications
AHA Product Specification – AHA3411 StarLite 16 MBytes/sec Simultaneous PS3411 Compressor/Decompressor IC ABDC18 AHA Application Brief – AHA3410C, AHA3411 and AHA3431 Device Differences ANDC12 AHA Application Note – AHA3410C StarLite Designer’s Guide ANDC13 AHA Application Note – Compression Performance on Bitonal Images ANDC14 AHA Application Note –... -
Page 48: Appendix A:additional Timing Diagrams For Dma Mode Transfers
Advanced Hardware Architectures, Inc. APPENDIX A: ADDITIONAL TIMING DIAGRAMS FOR DMA MODE TRANSFERS Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000 CLOCK ACKN DRIVEN Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000 CLOCK ACKN DRIVEN... -
Page 49: Figure A4: Dma Mode Timing For Four Word Burst Read, One Wait State, Strobe Condition Of Dsc=000
Advanced Hardware Architectures, Inc. Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=000 CLOCK ACKN DRIVEN Figure A5: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=000 CLOCK ACKN DRIVEN... -
Page 50: Figure A7: Dma Mode Timing For Single Word Writes, Strobe Condition Of Dsc=010
Advanced Hardware Architectures, Inc. Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010 CLOCK ACKN DRIVEN Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010 CLOCK ACKN DRIVEN Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=010 CLOCK CLOCK... -
Page 51: Figure A10:Dma Mode Timing For Four Word Burst Read, One Wait State, Strobe Condition Of Dsc=010
Advanced Hardware Architectures, Inc. Figure A10: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=010 CLOCK ACKN DRIVEN Figure A11: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=010 CLOCK ACKN DRIVEN... -
Page 52: Figure A13:Dma Mode Timing For Single Word Writes, Strobe Condition Of Dsc=011
Advanced Hardware Architectures, Inc. Figure A13: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011 CLOCK ACKN DRIVEN Figure A14: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011 CLOCK ACKN DRIVEN Figure A15: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011 CLOCK ACKN... -
Page 53: Figure A16:Dma Mode Timing For Four Word Burst Read, One Wait State, Strobe Condition Of Dsc=011
Advanced Hardware Architectures, Inc. Figure A16: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=011 CLOCK ACKN DRIVEN Figure A17: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=011 CLOCK ACKN DRIVEN... -
Page 54: Figure A19:Dma Mode Timing For Single Word Writes, Strobe Condition Of Dsc=111
Advanced Hardware Architectures, Inc. Figure A19: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111 CLOCK ACKN DRIVEN Figure A20: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111 CLOCK ACKN DRIVEN PS3431-0500 Page 49 of 50... -
Page 55: Appendix B:recommended Power Decoupling Capacitor Placement
Advanced Hardware Architectures, Inc. APPENDIX B: RECOMMENDED POWER DECOUPLING CAPACITOR PLACEMENT RECOMMENDED POWER DECOUPLING CAPACITOR PLACEMENT AHA3431 StarLite GUIDELINES FOR LOW NOISE OPERATION: 1) Use of dedicated power and ground planes within a multilayer printed circuit board is highly recommended for high speed designs. 2) Use (8) 0.047uF ceramic leadless chip capacitors placed as shown.
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