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taskit Stamp9G45 Technical Reference

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Stamp9G45
Technical Reference

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Summary of Contents for taskit Stamp9G45

  • Page 1 Stamp9G45 Technical Reference...
  • Page 2 Copyright © 2011 taskit GmbH All rights to this documentation and to the product(s) described herein are reserved by taskit GmbH. This document was written with care, but errors cannot be excluded. Neither the company named above nor the seller assumes legal liability for mistakes, resulting operational errors or the consequences thereof.

  • Page 3: Table Of Contents

    Stamp9G45 Table of Contents 1. Introduction ......................... 1 2. Scope ........................... 2 3. Overview of Technical Characteristics ................ 3 3.1. CPU ........................3 3.2. Memory ......................3 3.3. Interfaces and external signals ................. 3 3.4. Miscellaneous ....................4 3.5. Power Supply ....................4 3.6.
  • Page 4 A. Peripheral Color Codes ..................... 25 B. Peripheral Identifiers ....................26 C. Address Map (Physical Address Space) ..............27 D. Stamp9G45 Pin Assignment ..................29 E. Stamp9G45 Electrical Characteristics ..............32 F. Stamp9G45 Clock Characteristics ................33 G. Stamp9G45 Environmental Ratings ................34 H.
  • Page 5 Stamp9G45 List of Figures 5.1. Buffered Memory Bus (PIOC) 1.8V - 3.3V ............. 24 H.1. Stamp9G45 Dimensions ..................35 I.1. Starterkit FX8 ......................36 I.2. Starterkit Buffer ...................... 37 I.3. Starterkit Memory ....................38 I.4. Starterkit Serial ...................... 39 I.5. Starterkit Ethernet ....................40...
  • Page 6 Stamp9G45 List of Tables 4.1. Bus Matrix Masters ....................7 4.2. Bus Matrix Slaves ....................7 4.3. AT91SAM9G45 Clocks .................... 10 4.4. AC97 I/O Lines ....................... 18 4.5. LCDC palette entry ....................19 4.6. LCDC 24 bit memory organization ................ 19 B.1.

  • Page 7: Introduction

    Introduction 1. Introduction The Stamp9G45 is intended to be used as a small size "intelligent" CPU module as well as a universal Linux CPU card. It can be used anywhere where restricted energy and space requirements play a role. The design of the Stamp9G45 is limited to the processors core needs like DDRAM and Flash, thus giving the customer a wide-ranged choice of configurations of the peripherals and environment.

  • Page 8: Scope

    Scope 2. Scope This document describes the most important hardware features of the Stamp9G45. It includes all informations necessary to develop a customer specific hardware for the Stamp9G45. The Operating System Linux is described in a further document. The manual comprises only a brief description of the AT91SAM9G45 processor, as this is already described in depth in the manual of the manufacturer Atmel.

  • Page 9: Overview Of Technical Characteristics

    Overview of Technical Characteristics 3. Overview of Technical Characteristics 3.1. CPU Atmel AT91SAM9G45 Embedded Processor featuring an ARM926EJ-S™ ARM® Thumb® Core • CPU Clock 400 MHz • 32KB Instruction Cache • 32KB Data Cache • Memory Management Unit (MMU) • 3.3V Supply Voltage, 1.8V Memory Bus Voltage, 1.0V Core Voltage 3.2.

  • Page 10: Miscellaneous

    • Analog-to-Digital Converter • 16-Bit parallel CPU-Bus Some of the various functions are realized by multiplexing connector pins; therefore not all functions may be used at the same time (see Appendix D, Stamp9G45 Pin Assignment)). 3.4. Miscellaneous • Three 16-Bit Timer/Counter •...

  • Page 11: Hardware Description

    2x 100-pin fine pitch low profile Hirose ® FX8 connectors The size of the Stamp9G45's PCB is only 53.6x38x6.0 mm fitting it in even the smallest design. While having implemented the sensible CPU, DDRAM and Flash design it still...

  • Page 12: Lpddr-Sdram

    4.3.3. EEPROM The Stamp9G45 is equipped with a 128 bytes EEPROM, connected to the Dallas™ 1 wire bus. EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is non-volatile memory, which is used to store small amounts of data like calibration or configuration data.

  • Page 13: Bus Matrix

    Hardware Description 4.4. Bus Matrix The bus matrix of AT91SAM-controllers allows many master and slave devices to be connected independently of each other. Each master has a decoder and can be defined specially for each master. This allows concurrent access of masters to their slaves (provided the slave is available).

  • Page 14: Battery Backup

    4.8. Serial Number Every Stamp9G45 has a unique 48-bit hardware serial number chip which can be used by application software. The chip is a Dallas® one-wire-chip. A Linux driver is provided.

  • Page 15: Clock Generation

    Hardware Description port may be configured for general purpose I/O or assigned to a function of an integrated peripheral device. In doing so multiplexing with multiple integrated devices is possible. That means a pin may be used as GPIO or only as one of the peripheral functions. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.

  • Page 16: Programmable Clocks

    The programmable clocks can be individually programmed to derive their input from SLCK, PLLA, PLLB and Main Clock. Each PCK has a divider of 2, 4, 8, 16, 32 or 64. The Stamp9G45 features two programmable clocks PCK0, PCK1. 4.11. Power Management Controller (PMC) 4.11.1.

  • Page 17: Power Management

    Hardware Description • PLLB • Programmable Clocks The Main Oscillator frequency can be measured by using the PMC Main Clock Frequency register. The SLCK is used as reference for the measurement. 4.11.2. Power Management Using power management can dramatically reduce the power consumption of an Embedded Device.

  • Page 18: Timer Counter (Tc)

    4.13. Timer Counter (TC) The Stamp9G45 features two blocks of timer counters with three counters each. Due to multiplexing four timer counters may be used with external signals. The TC consists of three independent 16-bit Timer/Counter units. They may be cascaded to form a 32-bit or 48-bit timer/counter.

  • Page 19: Peripheral Dma Controller (Pdc)

    Hardware Description 4.18. Peripheral DMA Controller (PDC) The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The PDC contains unidirectional and bidirectional channels. The full-duplex peripherals feature unidirectional channels used in pairs (transmit only or receive only).

  • Page 20: Two-Wire Interface (Twi)

    In the current revision of the AT91SAM9G45 USB High speed is not working. It will work in the processor's next revision, which is expected in august 2011. The Stamp9G45 integrates two USB host ports supporting speeds up to 480 MBit/s. USB Host Port A is connected directly to the transceiver, USB Host Port B is multiplexed with the USB device port.

  • Page 21: Usb Device Port (Udp)

    In the current revision of the AT91SAM9G45 USB High speed is not working. It will work in the processor's next revision, which is expected in august 2011. The Stamp9G45 integrates one USB device port supporting speeds up to 480 MBit/s. It is multiplexed with the USB Host Port B.
  • Page 22 Hardware Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.

  • Page 23: Synchronous Peripheral Interface (Spi)

    • Slave Select (NSS): This control line allows slaves to be turned on and off by hardware. Each SPI Controller has a dedicated receive and transmit DMA channel. 4.28. Synchronous Serial Controller (SSC) The Stamp9G45 has one SSC interface available, depending on the multiplexing of the pins.

  • Page 24: Ac97 Controller (Ac97C)

    Hardware Description The SSC supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC has separated receive and transmit channels. Each channel has a data, a clock and a frame synchronization signal (RD, RK, RF, resp.

  • Page 25: Lcdc Initialisation And Lcd Power Sequencing

    Hardware Description The LCD controller relies on a relatively simple frame buffer concept, which means that all graphics and character functions have to be implemented in software: character sets and graphic primitives are not integrated in the controller. 4.31.1. LCDC Initialisation and LCD Power Sequencing LCD cells (pixels) should not be subjected to DC power for prolonged periods of time, as chemical decomposition might take place.

  • Page 26: Touch Screen Adc Controller (Tsadcc)

    4.32. Touch Screen ADC Controller (TSADCC) The Stamp9G45 has additional to touch panel support three ADC channels available. The Touch Screen ADC Controller is a 10-bit Analog-to-Digital Converter supporting resistive touch screen panels. It can be used as Touch Screen Controller, ADC or both supporting eight lines maximum.

  • Page 27: Design Considerations

    Design Considerations 5. Design Considerations 5.1. Ethernet Controller (EMAC) The emac needs an aditional PHY design. The emac supports both, MII and RMII interface. Please take care of the specific layout requirements of the Ethernet port when designing a base board. The two signals of the transmitter pair (ETX+ and ETX-) should be routed in parallel (constant distance, e.g.

  • Page 28: Usb Device Controller (Udp)

    The are preferably routed closely in parallel to the USB connector. 5.3. Memory Bus On the Stamp9G45 the memory bus is driven with 1.8V. This affects the voltages of PIOC- controller pins, they are 1.8V as well. Not affected are the ADC-Channels, which have their...
  • Page 29 Design Considerations own ADV . The V pins on the module are pin one and two of the bus interface. If pins of PIOC or the memory bus are in use on the customer's design it is highly recommended to implement buffers on both memory bus and PIOC pins. The memory bus is used inside of the module.
  • Page 30 Design Considerations...

  • Page 31: Peripheral Color Codes

    Peripheral Color Codes Appendix A. Peripheral Color Codes This table matches the color used to identify various peripherals in tables. Power Supply/Ground USART Debug UART TWI (I C-Bus) SD-Card/MMC USB Host USB Device Reserved Synhcronous Serial Controller (SSC) JTAG Control Ethernet Genral Purpose I/O Port Programmable Clock Output...

  • Page 32: Peripheral Identifiers

    Peripheral Identifiers Appendix B. Peripheral Identifiers Mnemonic Peripheral Name External Interrupt Advanced Interrupt Controller SYSC System Controller Interrupt PIOA Parallel I/O Controller A PIOB Parallel I/O Controller B PIOC Parallel I/O Controller C PIOD/PIOE Parallel I/O Controller D/E TRNG True Random Number Generator USART 0 USART 1 USART 2...

  • Page 33: Address Map (Physical Address Space)

    Address Map (Physical Address Space) Appendix C. Address Map (Physical Address Space) After the execution of the remap command the 4 GB physical address space is separated as shown in the following table. Accessing these addresses directly is only possible if the MMU (memory management unit) is deactivated.
  • Page 34 Address Map (Physical Address Space) Address (Hex) Mnemonic Function FFFB 4000 Image Sensor Interface FFFB 8000 Pulse Width Modulator FFFB C000 EMAC Ethernet Controller FFFC C000 TRNG True Random Number Generator FFFD 0000 MCI_1 Multimedia Card / SD-Card Interface #1 FFFD 4000 TC3, TC4, TC5 3 Timer Counter, 16-Bit...

  • Page 35: Stamp9G45 Pin Assignment

    Stamp9G45 Pin Assignment Appendix D. Stamp9G45 Pin Assignment GPIO Periph. A Periph. B Add.   Add. Periph. B Periph. A GPIO Function Function VMEM   VMEM EBI1 A0/NBS0   EBI1 A1/EBI1_NBS2/NWR2 EBI1 A2   EBI1 A3 EBI1 A4   EBI1 A5 EBI1 A6  ...
  • Page 36 Stamp9G45 Pin Assignment GPIO Periph. A Periph. B Add.   Add. Periph. B Periph. A GPIO Function Function EBI1 D12   EBI1 D13 EBI1 D14   EBI1 D15   PB20 ISI_D0           ISI_D1 PB21 PB22 ISI_D2  ...
  • Page 37 Stamp9G45 Pin Assignment GPIO Periph. A Periph. B Add.   Add. Periph. B Periph. A GPIO Function Function PE26 LCDD19           LCDD20 PE27 PE28 LCDD21           LCDD22 PE29 PE30 LCDD23    ...

  • Page 38: Stamp9G45 Electrical Characteristics

    Stamp9G45 Electrical Characteristics Appendix E. Stamp9G45 Electrical Characteristics Ambient temperature 25℃, unless otherwise indicated Symbol Description Parameter Min. Typ. Unit Operating Voltage Memory Bus Voltage 1.65 1.95 Reset Treshhold Duration Reset Pulse High-Level Input 3.3V + 0.3 V Voltage (PIOC4 PIOC31) 1.26...

  • Page 39: Stamp9G45 Clock Characteristics

    Stamp9G45 Clock Characteristics Appendix F. Stamp9G45 Clock Characteristics Symbol Description Dependency Tolerance Typical Unit Value MAINCK Main Oscillator frequency 12.000 SLCK Slow Clock 32.768 PLLACK PLLA Clock MAINCK 800.000 Processor Clock PLLACK 400.000 Master Clock 133.000 DDCK DDRAM Clock 266.000 Baudrate Clock 1.5%...

  • Page 40: Stamp9G45 Environmental Ratings

    Stamp9G45 Environmental Ratings Appendix G. Stamp9G45 Environmental Ratings Symbol Description Parameter Operating Storage Unit Min. Max. Min. Max. Ambient temperature ℃ Relative Humidity no condensation Absolute Humidity <= Humidity@T = 60℃, 90%RH Corrosive Gas not admissible Table G.1. Environmental Ratings...

  • Page 41: Stamp9G45 Dimensions

    Stamp9G45 Dimensions Appendix H. Stamp9G45 Dimensions Figure H.1. Stamp9G45 Dimensions...

  • Page 42: Starterkit Schematics

    Starterkit Schematics Appendix I. Starterkit Schematics...
  • Page 43 Starterkit Schematics...
  • Page 44 Starterkit Schematics...
  • Page 45 Starterkit Schematics...
  • Page 46 Starterkit Schematics...
  • Page 47 Starterkit Schematics...

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