Crystal CS4231A Manual

Parallel interface, multimedia audio codec

Hide thumbs

Table Of Contents

Table of Contents

Quick Links

Semiconductor Corporation

Parallel Interface, Multimedia Audio Codec

Features

•

Windows Sound System

Compatible Codec

•

ADPCM Compression/Decompression

•

Extensive Software Support

•

MPC Level 2 Compatible Mixer

•

Dual DMA Registers support Full

Duplex Operation

•

On-Chip FIFOs for higher performance

•

Selectable Serial Audio Data Port

•

Pin Compatible with CS4231/CS4248

VD1

VD2

D<7:0>

A<1:0>

IRQ

DBDIR

DBEN

Parallel

Bus

Interface

PDRQ

CDRQ

PDAK

CDAK

XCTL1

XCTL0

PDWN

DGND1 DGND2

Preliminary Product Information

Crystal Semiconductor Corporation

P.O. Box 17847, Austin, TX 78760

(512) 445-7222 Fax: (512) 445-7581

VD3

VD4

SDOUT SDIN SCLK FSYNC

Audio Data Serial Port

I16

Linear

µ -law

FIFO

A-law

ADPCM

Samples

I8 or I28

Optional

Dither

I10

Linear

µ-law

FIFO

I 16

A-law

Samples

ADPCM

16 Bit Timer

I20,I21

DGND3/4/7/8

TEST

XTAL1I

This document contains information for a new product. Crystal

Semiconductor reserves the right to modify this product without notice.

General Description

The CS4231A includes stereo 16-bit audio converters

and complete on-chip filtering for record and playback

of 16-bit audio data. In addition, analog mixing and

programmable gain and attenuation are included to

provide a complete audio subsystem. A selectable se-

rial port can pass audio data to and from DSPs or

ASICs. Crystal-developed high-performance software

drivers for various operating systems are available that

support all the CS4231A features including full duplex

transfers. The CS4231A is a pin compatible upgrade to

the CS4231 and CS4248.

ORDERING INFORMATION:

CS4231A-KL

CS4231A-KQ

VREF

VREFI

LFILT RFILT

VREF

16-bit

A/D

16-bit

A/D

Loopback

Digital

I13

Attenuation

16-bit

D/A

16-bit

D/A

Oscillators

XTAL1O

XTAL2I

XTAL2O

CS4231A

0 to 70°C

VA1 VA2

20dB Gain

Gain

Mux

Gain

Mix

Gain

I19

Mix

Gain

I18

Mute

I26

Mute

Mix

I26

Gain

MIN

AGND1

AGND2

68-pin PLCC

100-pin TQFP

LMIC

RMIC

LLINE

RLINE

LAUX1

RAUX1

LOUT

MOUT

ROUT

LAUX2

RAUX2

SEPT '94

DS139PP2

Table of Contents

Need help?

Do you have a question about the CS4231A and is the answer not in the manual?

Questions and answers

Summary of Contents for Crystal CS4231A

Page 1 • support all the CS4231A features including full duplex On-Chip FIFOs for higher performance transfers. The CS4231A is a pin compatible upgrade to • the CS4231 and CS4248. Selectable Serial Audio Data Port •...
Page 2: Table Of Contents
CS4231A CS4231A REGISTER MAPPING ......28 TABLE OF CONTENTS: Physical Mapping............28 Index Address Register....(R0)....29 CS4231A TECHNICAL SPECIFICATIONS....3 Index Data Register ..... (R1)....29 GENERAL DESCRIPTION ........11 Status Register......(R2, RO) ..29 Enhanced Functions (MODE 2)......12 Capture I/O Data Register ... (R3, RO) ..30 Mixer Attenuation Control on Line Input ....12...
Page 3: Cs4231A Technical Specifications
CS4231A ANALOG CHARACTERISTICS = 25 °C; VA1, VA2, VD1-VD4 = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD4; 1 kHz Input Sine wave; Conversion Rate = 48 kHz; Measurement Bandwidth is 10 Hz to 20 kHz, 16-bit linear coding.)
Page 4 CS4231A ANALOG CHARACTERISTICS (Continued) Parameter* Symbol Units Analog Output Characteristics - Minimum Attenuation (0dB); unless otherwise specified. DAC Resolution Bits ±0.5 DAC Differential Nonlinearity (Note 1) Dynamic Range -Total All Outputs -Instantaneous Total Harmonic Distortion (Note 3) 0.01 0.02 Signal-to-Intermodulation Distortion...
Page 5 CS4231A AUXILIARY INPUT MIXERS (TA = 25 °C; VA1, VA2, VD1-VD4 = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD1-VD4; 1 kHz Input Sine wave) Parameter Symbol Units Mixer Gain Range Span LINE, AUX1, AUX2 (Note 6) 46.5...
Page 6 CS4231A DIGITAL FILTER CHARACTERISTICS Parameter Symbol Units Passband 0.40xFs Frequency Response -0.5 +0.2 ±0.1 Passband Ripple (0-0.4xFs) Transition Band 0.40xFs 0.60xFs Stop Band 0.60xFs Stop Band Rejection Group Delay 16- and 8-bit formats 10/Fs ADPCM stereo format 14/Fs ADPCM mono format 18/Fs µs...
Page 7 SDIN valid to SCLK falling SDIN hold after SCLK falling Notes: 7. When only one crystal is used, it must be XTAL1. When using two crystals, the high frequency crystal should be on XTAL1 which is designed for higher loop gains.
Page 8 CS4231A FSYNC SF1,0=01,10 FSYNC SF1,0=00 SCLK t s1 sckw SDIN MSB, Left MSB, Left SDOUT Serial Port Timing CDRQ t DRHD t DKSUa CDAK DKHDb t DBDL DBEN t DBDL DBDIR t STW t DHD1 t RDDV D<7:0> 8-Bit Mono DMA Read/Capture Cycle...
Page 9 CS4231A PDRQ t DRHD t DKSUb PDAK t DKHDa t DBDL DBEN DBDIR (high) t STW t DHD2 t WDSU D<7:0> 8-Bit Mono DMA Write/Playback Cycle CDRQ/PDRQ CDAK/PDAK t BWDN RD/ WR RIGHT/HIGH LEFT/LOW D<7:0> BYTE BYTE 8-Bit Stereo or 16-Bit Mono DMA Cycle...
Page 10 CS4231A CDRQ/PDRQ t SUDK1 t SUDK2 CDAK/PDAK t CSSU t CSHD t DBDL DBEN DBDIR t DBDL t RDDV t DHD1 D<7:0> A<1:0> t ADHD t ADSU I/O Read Cycle CDRQ/PDRQ t SUDK1 t SUDK2 CDAK/PDAK t CSHD t CSSU...
Page 11 CS4231A +5V Analog (preferred) Ferrite Bead 2.0Ω If a separate +5V analog supply is available, attach here Supply and remove the 2.0Ω resistor 0.1 µF 1 µF 0.1 µF 0.1 µF 0.1 µF 1 µF + 1 µF + 0.1 µF MOUT 1 µF...
Page 12: General Description
5. ADPCM and Big Endian audio data formats companded, 4-bit ADPCM compressed, and 16- 6. Independent selection of capture and bit Big Endian. The CS4231A is packaged in a playback audio data formats 68-pin PLCC or a 100-pin TQFP. 7. Selectable serial audio data port.
Page 13: Line-Level Inputs Plus Mpc Mixer
The analog output section of the CS4231A pro- possible to minimize noise coupling. vides a stereo line-level output. The other output...
Page 14: Mono Output With Mute Control
The LFILT and RFILT pins must have a 1000 pF NPO capacitor to analog ground. These capaci- There is no provision for the CS4231A to "hold tors, along with an internal resistor, provide a off" or extend a cycle occurring on the parallel single-pole low-pass filter used at the inputs to interface.
Page 15: High Current Data Bus Drivers
CS4231A transparent and have no programming associated nal. The CS4231A will latch data into the PIO with them. register on the rising edge of the WR strobe. The CS4231A CS signal should remain active until When playback is enabled, the playback FIFO after completion of the read or write cycle.
Page 16: Dual Dma Channel Mode
SDIN pin is routed to the DACs. The parallel a Mode Change Enable (MCE, R0). This allows bus on the CS4231A is still used for control in- for proper full duplex control where applications formation such as volume and audio data are independently using playback and capture.
Page 17 CS4231A output clocks will stretch, but will not have any The first format - SPF0, shown in Figure 6, is glitches. This allows the serial port to operate called 64-bit enhanced. This format has 64 through a sample frequency change.
Page 18: Miscellaneous Signals
An interrupt pin, IRQ, is provided to allow for contains 32 SCLKs per frame wherein FSYNC host notification by the CS4231A. Since the in- is high for the left channel and low for the right terrupt is mainly a software function, it is described in more detail under the software sec- channel.
Page 19: Power Down - Pdwn
The standard crystals for audio are: If needed, the DBEN and DBDIR pins can con- trol an external data buffer to the CS4231A. The XTAL1: 24.576 MHz CS4231A contains 16 mA bus drivers so the ex-...
Page 20: Calibration Modes
DACs at some point). Changing from any which a full calibration occurs. While the other calibration mode to No Calibration mode CS4231A is initializing, 80 hex is returned from will take 40 sample periods to complete; how- all reads by the host computer. All writes during ever, subsequent MCE cycles will take 0 sample initialization of the CS4231A will be ignored.
Page 21: Changing Sampling Rate
XTALE Changing Sampling Rate (and the No Calibration mode, I9) provide the The internal states of the CS4231A are synchro- fastest switching time for applications such as nized by the selected sampling frequency defined games that constantly change the sample fre- in the Fs and Playback Data Format register (I8).
Page 22: 16-Bit Signed
Format register (I28). The 16-bit signed format (also called 16-bit 2’s complement) is the standard method of repre- The CS4231A always orders the left channel senting 16-bit digital audio. This format gives data before the right channel. Note that these 96 dB theoretical dynamic range and is the standard for compact disk audio players.
Page 23 CS4231A 32-bit Word Time sample 6 sample 5 sample 4 sample 3 sample 2 sample 1 MONO MONO MONO MONO Figure 12. 8-bit Mono, Unsigned Audio Data 32-bit Word Time sample 3 sample 3 sample 2 sample 2 sample 1...
Page 24 CS4231A 32-bit Word Time sample 8 sample 7 sample 6 sample 5 sample 4 sample 3 sample 2 sample 1 MONO MONO MONO MONO MONO MONO MONO MONO Figure 16. 4-bit Mono, ADPCM Audio Data 32-bit Word Time sample 4 sample 4...
Page 25: Adpcm Compression/Decompression
In MODE 2, the CS4231A also contains Adap- or not sending data in PIO mode. The underrun tive Differential Pulse Code Modulation will be detected by the CS4231A and the adapta- (ADPCM) for improved performance and com- pression ratios over µ-Law or A-Law. The tion will freeze.
Page 26: Playback Dma Registers
When loopback is enabled, it will "freerun" syn- Playback DMA Registers chronous with the sample rate. The digital loopback is shown in the CS4231A Block Dia- The playback DMA registers (I14/15) are used for sending playback data to the DACs in gram on the front cover.
Page 27: Timer Registers
This counter is 16 bits and the exact time CS4231A. When the IEN bit is 0, the interrupt is base, listed in the register description, is deter- masked and the IRQ pin of the CS4231A is mined by the crystal selected.
Page 28: Cs4231A Register Mapping
Left ADC Input Control Table 1. Direct Registers Right ADC Input Control The two address pins of the CS4231A allow ac- Left Aux #1 Input Control cess to four 8-bit registers. Two of these registers Right Aux #1 Input Control...
Page 29: Index Address Register
INIT CS4231A Initialization: This bit is read 0 - Data still valid. Do not overwrite. as 1 when the CS4231A is in a state 1 - Data stale. Ready for next host in which it cannot respond to parallel data write value.
Page 30 CS4231A PU/L Playback Upper/Lower Byte: This bit 0 - Lower or 1/3 ADPCM byte waiting indicates whether the playback data 1 - Upper, any 8-bit mode, or 2/4 needed is for the upper or lower ADPCM byte waiting byte of the channel. In ADPCM it in- dicates, along with PL/R, which one of four ADPCM bytes is needed.
Page 31: Playback I/O Data Register
CS4231A LSS1-LSS0 Left ADC Input Source Select. These During initialization and power down, this regis- bits select the input source for the ter can NOT be written and is always read left ADC channel. 10000000 (80h) 0 - Left Line: LLINE...
Page 32: Right Auxiliary #1 Input Control
CS4231A Right Auxiliary #1 Input Control (I3) Left DAC Output Control (I6) D7 D6 D5 RX1M res res RX1G4 RX1G3 RX1G2 RX1G1 RX1G0 LDM res LDA5 LDA4 LDA3 LDA2 LDA1 LDA0 RX1G4-RX1G0 Right Auxiliary #1, RAUX1, Mix Gain. LDA5-LDA0 Left DAC Attenuator. The least signifi- The least significant bit represents cant bit represents -1.5 dB, with...
Page 33: Fs And Playback Data Format
Mono capture only captures data playback. If only one crystal is sup- from the left channel. In MODE 1, plied in hardware, it must be XTAL1. this bit is used for both playback and CAUTION: C2SL can only be capture.
Page 34: Interface Configuration
1 - Playback Enabled 0 - DMA transfers Capture Enabled. This bit enables the 1 - PIO transfers capture of data. The CS4231A will generate CDRQ and respond to CPIO Capture PIO Enable: This bit deter- CDAK signals when CEN is enabled mines whether the capture data is and CPIO=0.
Page 35: Pin Control
DRQ Status: This bit indicates the 0 - Interrupt disabled current status of the PDRQ and 1 - Interrupt enabled CDRQ pins of the CS4231A. Dither Enable: When set, triangular 0 - CDRQ AND PDRQ are presently pdf dither is added before truncating...
Page 36: Mode And Id
MODE2 MODE 2: Enables the expanded mode Count registers cannot be read. of the CS4231A. Must be set to en- When set for MODE 1 or SDC, this able access to indirect registers register is used for both the Play- 16-31 and their associated features.
Page 37: Alternate Feature Enable I
Crystal Enable. When set, both crystals are always active. When SF1,SF0 Serial Format. Selects the format of clear, only the crystal selected by the serial port when enabled by C2SL, I8, is active with the other SPE. MCE must be set before these crystal powered down.
Page 38 CS4231A Direct Registers: (R0-R3) A1 A0 † INIT CU/L CL/R CRDY PU/L PL/R PRDY Indirect Registers: (I0-I31) IA4-IA0 LSS1 LSS0 LMGE LAG3 LAG2 LAG1 LAG0 RSS1 RSS0 RMGE RAG3 RAG2 RAG1 RAG0 LX1M LX1G4 LX1G3 LX1G2 LX1G1 LX1G0 RX1M RX1G4...
Page 39 CS4231A NOTE: Output level relative to input level assuming OLB=1. AG3 AG2 AG1 AG0 Level Level 0.0 dB 12.0 dB 1.5 dB 10.5 dB 3.0 dB 9.0 dB 4.5 dB 7.5 dB 6.0 dB 4.5 dB 3.0 dB 18.0 dB 1.5 dB...
Page 40: Right Line Input Control
CS4231A Right Line Input Control (I19) RESERVED (I22) res RLG4 RLG3 RLG2 RLG1 RLG0 This register’s initial state after reset is: xxxxxxxx RLG4-RLG0 Right Line, RLINE, Mix Gain. The least significant bit represents 1.5 dB, with Alternate Feature Enable III (I23) 01000 = 0 dB.
Page 41: Alternate Feature Status
CID2 CID1 CID0 V2-V0 Version number. As enhancements are Playback Underrun: This bit, when set, made to the CS4231A, the version indicates that the DAC has run out number is changed so software can of data and a sample has been distinguish between the different ver- missed.
Page 42: Capture Data Format
CS4231A Mono Input Mute. This bit controls the RESERVED (I29) mute function on the mono input, MIN to the mixer. The mono input provides mix for the "beeper" func- This register’s initial state after reset is: xxxxxxxx tion in most personal computers.
Page 43: Grounding And Layout
17 shows the recommended positioning of the decoupling capacitors. The capacitors must be 3. Although optimum performance is on the same layer as, and close to, the CS4231A. achieved using the ground plane shown The vias shown go through to the ground plane in Figure 16, any ground plane scheme layer.
Page 44 CS4231A ≥ 1/8" Digital Ground CS4231A Plane Digital Analog PINS Pins Pins Ground Connection Analog Ground Ferrite Plane Bead CPU & Digital Codec Codec Logic digital analog signals signals & Components Figure 16. Suggested Layout Guideline = vias through to...
Page 45: Adc/Dac Filter Response Plots
A for more details. Figures 18 through 23 show the overall fre- quency response, passband ripple, and transition 11.The TEST pin on the CS4231A must be band for the CS4231A ADCs and DACs. Fig- grounded. This pin is not used or con- ure 24 shows the DACs’...
Page 46 CS4231A -0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -100 -0.8 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency ( × Fs) Input Frequency (×Fs) Figure 21.
Page 47: Pin Descriptions
CS4231A PIN DESCRIPTIONS XCTL1 XCTL0 CDAK TEST CDRQ DGND7 PDAK PDRQ CS4231A DGND3 100-pin XTAL1I TQFP XTAL1O SDOUT DGND4 SCLK XTAL2I FSYNC Top View XTAL2O SDIN PDWN MOUT RFILT DS139PP2...
Page 48 CS4231A DGND1 DGND8 DBEN DGND2 DBDIR CDAK CDRQ XCTL1 67 65 63 61 PDAK PDRQ XCTL0 CS4231A TEST 68-pin DGND3 * NC (V XTAL1I DGND7 PLCC XTAL1O SDOUT SCLK DGND4 FSYNC Top View XTAL2I SDIN XTAL2O PDWN MOUT * NC (V...
Page 49 These signals are used to transfer data to and from the CS4231A. DBEN - Data Bus Enable, Output, Pin 63 (L), Pin 78 (Q). This pin indicates that the bus drivers attached to the CS4231A should be enabled. This signal is active low.
Page 50 DACs for conversion to analog. The serial port supports three serial formats and supports all audio data formats of the CS4231A. The serial audio data is always 16 bits wherein the MSB of the different audio (16, 8, 4 bit) is aligned with zero padding after the LSB.
Page 51 XTAL1I - Crystal #1 Input, Pin 17 (L), Pin 12 (Q). This pin will accept either a crystal with the other pin attached to XTAL1O or an external CMOS clock. XTAL1 must have a crystal or clock source attached for proper operation. The standard crystal frequency is 24.576 MHz although other frequencies can be used.
Page 52 VREFI - Voltage Reference Internal, Input, Pin 33 (L), Pin 38 (Q). Voltage reference used internal to the CS4231A must have a 0.1 µF + 10 µF capacitor with short fat traces to attach to this pin. No other connections should be made to this pin.
Page 53 *NC (V ) - No Connect, Pins 24, 45, 54 (L) These pins are no connects for the CS4231A. When compatibility with the AD1848 is desired, these pins should be connected to the digital power supply. For other compatibility issues, see the Compatibility with AD1848 section of the data sheet.
Page 54: Parameter Definitions
CS4231A PARAMETER DEFINITIONS Resolution The number of bits in the input words to the DACs, and in the output words in the ADCs. Differential Nonlinearity The worst case deviation from the ideal code width. Units in LSB. Total Dynamic Range TDR is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor.
Page 55 The serial audio data port and associated bits - SF1, SF0, SPE - do not exist on the CS4231. The serial audio data port was added to the CS4231A to allow DSP’s and ASIC’s to act as an audio coprocessor to the CS4231A.
Page 56: Package Dimension
CS4231A PACKAGE DIMENSIONS 22.61 25.02 25.27 24.13 24.33 23.62 (0.995) (0.950) (0.958) (0.985) (0.890) (0.930) 4.20 (0.165) Min 5.08 (0.200) Max 1.07 (0.042) Min 0.51 (0.020) 1.067 (0.042) Min 1.42 (0.056) Max 1.219 (0.048) Max x45deg.NOM 2.29 (0.090) Min 0.25 (0.010) R x 45deg.
Page 57: Cdb4231/4248 Data Sheet
General Description • The CDB4231/4248 evaluation board supports all the PC ISA Plug-In Card features of the CS4231A, CS4231, and CS4248. The DMA, IRQ, and base address are all selectable via on- • board jumpers. Four stereo jacks provide MIC in, Serial Audio Data Port Header for AUX1 in, LINE in, and Line/Headphone out.
Page 58 The stereo , Microphone Mic I the CS4231A, CS4231, or CS4248 Parallel Inter- Input, (Figure 2) contains an op-amp buffer with face, Multimedia Audio Codecs in a PC a gain of 18 dB providing a maximum full scale environment.
Page 59 J34, that is connected to the se- equipment containing line-level inputs. It is also rial audio data port on the CS4231A. The even designed to drive headphones directly with ex- pins are connected to ground and the rest of the ceptional quality.
Page 60 CDB4231/4248 The second four addresses are used by the mode, as well as playback on the CS4231 in codec. The default for the evaluation board and full-duplex operation. the software is 530h - no jumpers. The following table lists the available base addresses (along Half Duplex - Single DMA Channel with the associated codec address), with a "1"...
Page 61 ID and assume that the auto-se- Auto-Select register with the proper DMA and lect register needs to be loaded. The auto-select IRQ settings. In 100% WSS mode, the Crystal register only allows certain combinations which software will not allow improper settings for the must be adhered to when using the evaluation DMA and IRQ.
Page 62 CDB4231/4248 The Crystal Windows 3.1 software (version CRYSTAL ENHANCED WSS 2.0 DRIVERS 1.04) supports a "generic hardware" switch that forces the software to use the DMA and IRQ set- Crystal also provides enhanced Windows Sound tings in the SYSTEM.INI file and assume no System drivers that support software written to Auto-Select register exists.
Page 63 CDB4231/4248 DS111DB7...
Page 64 CDB4231/4248 Figure 2. Microphone In Figure 3. Mono Speaker Out DS111DB7...
Page 65 CDB4231/4248 Figure 4. Line In & CDROM In (Aux2) DS111DB7...
Page 66 CDB4231/4248 Figure 5. Line/Headphone Out DS111DB7...
Page 67 CDB4231/4248 DS111DB7...
Page 68 CDB4231/4248 DS111DB7...
Page 69 TITLE Address Decode for CS4231 and Read ID PATTERN AD31.PDS REVISION 2.0 AUTHOR Clif Sanchez COMPANY Crystal Semiconductor DATE 10/15/93 CHIP _AD31 PAL20V8 ;---------------------------------- PIN Declarations --------------- ; Eight addresses in all. ; The first four addresses are used by the board PLD ID31 - address select RDID.
Page 70 ;---------------------------------- Declaration Segment ------------ TITLE Read ID + relay enable PATTERN ID31.PDS REVISION 2.0 AUTHOR Clif Sanchez COMPANY Crystal Semiconductor DATE 10/28/93 CHIP _ID31 PAL22V10 ;---------------------------------- PIN Declarations --------------- MUTE ; I - from Codec XCTL1 pin, Software Mute /BIOR ;...
Page 71 CDB4231/4248 ACCESS = ACCESS * /CRES + CCS * BIOR * /CRES RLYEN = ACCESS * /MUTE Board ID PLD - ID31 (continued) DS111DB7...
Page 72 CDB4231/4248 DS111DB7...
Page 73 CDB4231/4248 DS111DB7...
Page 74 CDB4231/4248 DS111DB7...
Page 75 CDB4231/4248 DS111DB7...
Page 76 CDB4231/4248 DS111DB7...

This manual is also suitable for:

Cs4231a-kl Cs4231a-kq

Crystal CS4231A Manual

Quick Links

Need help?

Questions and answers

Subscribe to Our Youtube Channel

Summary of Contents for Crystal CS4231A

This manual is also suitable for:

Table of Contents