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VMIC VMIVME-3124 Product Manual

Analog input board
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  • Page 1 sales@artisantg.com artisantg.com (217) 352-9330 | Visit our website - Click HERE...
  • Page 2 VMIVME-3124 ANALOG INPUT BOARD PRODUCT MANUAL DOCUMENT NO. 500-003124-000 B Revised June 10, 1996 VME MICROSYSTEMS INTERNATIONAL CORPORATION 12090 SOUTH MEMORIAL PARKWAY HUNTSVILLE, ALABAMA 35803-3308 (205) 880-0444 (800) 322-3616 FAX NO. (205) 882-0859...
  • Page 3 VMIC assumes no responsibility resulting from omissions or errors in this manual, or from the use of information contained herein. VMIC reserves the right to make any changes, without notice, to this or any of VMIC's products to improve reliability, performance, function, or design.
  • Page 4 RECORD OF REVISIONS REVISION DATE PAGES INVOLVED CHANGE NUMBER LETTER 01/25/95 Release 95-0528 06/10/96 Cover, Pages ii, iii, 3-5, 4-4, 5-4, and 96-0409 REV LTR PAGE NO. VME MICROSYSTEMS INT’L CORP. 12090 South Memorial Parkway DOC. NO. 500-003124-000 Huntsville, AL 35803-3308• (205) 880-0444...
  • Page 5 VMIC SAFETY SUMMARY THE FOLLOWING GENERAL SAFETY PRECAUTIONS MUST BE OBSERVED DURING ALL PHASES OF THE OPERATION, SERVICE, AND REPAIR OF THIS PRODUCT. FAILURE TO COMPLY WITH THESE PRECAUTIONS OR WITH SPECIFIC WARNINGS ELSEWHERE IN THIS MANUAL VIOLATES SAFETY STANDARDS OF DESIGN, MANUFACTURE, AND INTENDED USE OF THIS PRODUCT.
  • Page 6 SAFETY SYMBOLS GENERAL DEFINITIONS OF SAFETY SYMBOLS USED IN THIS MANUAL Instruction manual symbol: the product is marked with this symbol when it is necessary for the user to refer to the instruction manual in order to protect against damage to the system. Indicates dangerous voltage (terminals fed from the interior by voltage exceeding 1000 volts are so marked).

  • Page 7: Table Of Contents

    500-003124-000 VMIVME-3124 ANALOG INPUT BOARD TABLE OF CONTENTS Page SECTION 1. INTRODUCTION FEATURES ..........1-1 SECTION 2.
  • Page 8 LIST OF FIGURES Figure Page 3.2-1 VMIVME-3124 Functional Block Diagram ..5.3-1 VMIVME-3124 Configuration Jumper Locations ..5.4-1 P3 Connector .....

  • Page 9: Introduction

    16 or 32 input channels. Conversion data is stored automatically in a dual-port memory, making it immediately accessible from the VMEbus. The VMIVME-3124 provides on-board voltage references to perform an on-line or off-line built in self-test. The input voltage range and gain are user programmable with jumpers.
  • Page 10 500-003124-000 The VMIVME-3124 occupies 128 bytes of short I/O VMEbus addressing space. Jumpers are provided to place the board on any 128-byte boundary. The board may also be jumper-programmed to respond to supervisory, nonprivileged, or both accesses. Conversion data is available from a 16-bit register (12-bit right justified with optional sign extension).

  • Page 11: Physical Description And Specifications

    500-003124-000 SECTION 2 PHYSICAL DESCRIPTION AND SPECIFICATIONS REFER TO 800-003124-000 SPECIFICATION...

  • Page 12: Theory Of Operation

    Control/Status Register. This disables further channel address increments. The board then locks onto that channel. This allows a single channel to be digitized every 25sec. The following sections discuss the functional components of the VMIVME-3124 in detail. FUNCTIONAL ORGANIZATION The VMIVME-3124 is divided into the following functional categories. Each category will be discussed in detail.

  • Page 13: Vmivme-3124 Functional Block Diagram

    25MHz Clock CSR/Status Figure 3.2-1 VMIVME-3124 Functional Block Diagram During each read or write operation, all VMEbus control signals are ignored unless the board selection comparator detects a match between the on-board selection jumpers and the address and address modifier line from the backplane. The appropriate board response occurs if a valid match is detected.

  • Page 14: Analog-To-Digital Control And Timing

    In either case, the electrical process of analog-to-digital conversion is similar. The VMIVME-3124 uses a 12-bit ADC. The ADC has a conversion time of 8.5 sec. Settling time is required for the multiplexers and the Programmable Gain Amplifier (PGA) before the ADC cycle can begin. The total channel acquisition cycle occurs every 25 sec.

  • Page 15: Built-In-Test Reference

    500-003124-000 BUILT-IN-TEST REFERENCE The board is equipped with a programmable precision voltage reference which is used as a Built-In-Test (BIT) of the board. When selected, the BIT voltage is transferred through the Programmable Gain Amplifier (PGA) to the Analog-to-Digital Conversion (ADC), bypassing the external analog input on channel zero. Therefore, the channel zero location in the Dual-Port RAM is written with the BIT voltage’s equivalent digital value.

  • Page 16: Low-Pass Filters

    The voltage developed across a resistor is read by the VMIVME-3124. The optional -2BC board provides resistors value at 250  ±0.01%. The optional -3BC board provides resistors value at 500  ±0.01%. To support this option the 5 kHz low pass filter is not installed at the factory, all other functionality of the board remains the same.

  • Page 17: Channel Sequencer And Dual-Ported Ram Memory

    Channel Pointer register. It then sets the Stop Auto Scan bit within 25 sec. BOARD ID REGISTER The first location in the VMIVME-3124 register set is a read-only Board ID Register. It always reads $30. Other VMIC products have similar registers which read different constants.

  • Page 18: Programming

    SECTION 4 PROGRAMMING MEMORY MAP The VMIVME-3124 occupies 128-bytes of addressing space including four information and control registers plus the conversion data registers. Tables 4.1-1 through 4.1-3 map this addressing space relative to the base address as set by configuration jumpers (see Section 5 for details concerning setting the base address and address modifier jumpers).
  • Page 19 500-003124-000 Table 4.1-2. VMIVME-3124 Memory Map: Differential Inputs, Maximum Buffer Offset Function Width Access Address Board ID Register byte read-only Configuration Register byte read-only Control/Status Register byte read/write Channel Pointer Register byte read-only $04-$3F Reserved Channel 0 Data word read/(write)
  • Page 20 500-003124-000 Table 4.1-3. VMIVME-3124 Memory Map: Single-Ended Inputs Offset Function Width Access Address Board ID Register byte read-only Configuration Register byte read-only Control/Status Register byte read/write Channel Pointer Register byte read-only $04-$3F Reserved Channel 0 Data word read/(write) Channel 1 Data...

  • Page 21: Register Descriptions

    4.2.1 Board ID Register The Board ID Register is an 8-bit read only register at offset $00 with a constant value set to $30 for the VMIVME-3124. This ID number uniquely identifies the board from other VMIC products. 4.2.2 Board Configuration Register The Configuration Register is an 8-bit read-only register at offset $01 that indicates the current configuration of the VMIVME-3124 board.

  • Page 22: Control/Status Register

    The user may set the Stop Auto Scan bit; however, to cause the VMIVME-3124 to stop on a single channel. If the Stop Auto Scan bit is set, only the Data Register pointed to by the Channel Pointer Register is updated, although it will be updated much faster than usual –...

  • Page 23: Channel Pointer Register

    The Channel Pointer Register is an eight-bit read-only register at offset $03. Under most circumstances, the Channel Pointer Register holds the channel number of the current input being sampled and converted by the VMIVME-3124. The only exception occurs when the board is configured for differential input and the Max Buffer bit in the Control/Status Register is set.
  • Page 24 5 for details). Calculate the LSB weight by dividing the full-scale range by 4096. For example, the LSB weight for a VMIVME-3124 configured for 10 V at unity gain would be 4.883 mV (20/4096). Table 4.2.5-1 lists the LSB weights for all possible VMIVME-3124 configurations.

  • Page 25: Built-In-Test Functions

    BUILT-IN-TEST FUNCTIONS The VMIVME-3124 has the ability to test its functionality by applying various internal reference voltages to the channel 0 input. Host software may then read the value for channel 0 and compare it to its predicted quantity. Tables 4.3-1 through 4.3-3 show all possible BIT values.

  • Page 26: Range And Gain Determination

    Any value of $0FFF indicates an over-voltage condition. RANGE AND GAIN DETERMINATION While the VMIVME-3124 analog gain and range may be set by the user, there is no direct way to read these settings in software (see Section 5 for hardware gain and range configuration).

  • Page 27: Current Inputs, -2Bc And -3Bc Options

    500-003124-000 Once scanning is halted, any Data Register may be safely read as bytes except for the Data Register pointed to by the Channel Pointer Register. Drawbacks to this method is that it is inherently slow and the programmer loses a regular time reference. The clock is stopped while the Halt bit is set (that is, the data is frozen for all channels except the one pointed to by the Channel Pointer Register, whose input gets converted constantly).

  • Page 28: Configuration And Installation

    All claims arising from shipping damage should be filed with the carrier and a complete report sent to VMIC together with a request for advice concerning the disposition of the damaged item(s).

  • Page 29: Jumper Installations

    JUMPER INSTALLATIONS Figure 5.3-1 identifies the location of configuration jumpers and calibration potentiometers for the VMIVME-3124. Jumpers E1 through E9 are address jumpers which must be set to the desired base address of the board as described in Section 5.3.1. Jumper E10 controls the VMEbus access mode, either supervisory or nonprivileged;...

  • Page 30: Address Modifier

    A13, A12, A11, and A9 are set. Check Table 5.3.1-1. All jumpers should be installed (for the clear address bits) except for jumpers E7, E8, E9, and E3 (for the set address bits). 5.3.2 Address Modifier Jumper E10 determines whether the VMIVME-3124 responds to supervisory or nonprivileged accesses according to Table 5.3.2-1.

  • Page 31: Input Configuration

    5.3.3 Input Configuration Three jumpers (E14, E15, and E16) are used to configure the VMIVME-3124 for single-ended or differential inputs. Two jumpers (E19 and E20) control the input voltage range, and two jumpers (E18 and E17) control the amount of gain. The jumpers are shown in Table 5.3.3-1 below.

  • Page 32: Analog Input Connector Description

    ANALOG INPUT CONNECTOR DESCRIPTION The 16 differential or 32 single-ended analog input connections to the VMIVME-3124 board are made using the front panel 37-pin D connector labelled P3. See Figure 5.4-1 and Table 5.4-1 below for connector pin and signal assignments.

  • Page 33: Calibration Procedures

    To obtain the specified accuracy for analog measurements, the VMIVME-3124 must be calibrated for the range used. For greatest possible accuracy, VMIC recommends calibrating the board after it has been installed in its target chassis and after power has been applied for at least a half hour.

  • Page 34: Bipolar ±5 V Offset And Gain Calibration

    500-003124-000 d. Halt scanning on channel 0 and monitor channel 0 data. e. Adjust unipolar offset potentiometer R60 until channel 0 data fluctuates between $000 and $001. f. Connect precision voltage source to channel 0 input. g. Adjust precision voltage source to +9.996338 VDC. h.

  • Page 35: Built-In-Test Voltage Calibration

    500-003124-000 h. Change mode and gain jumpers as necessary for your final configuration. 5.5.6 Built In Test Voltage Calibration NOTE: Run this calibration procedure only after the instrumentation amp and appropriate offset and gain calibration procedures. a. Attach DVM positive to ADC input at TP1; attach negative to analog ground at TP2.

  • Page 36: Maintenance

    No components of adjacent boards are disturbed when inserting or removing the board from the chassis h. Quality of cables and I/O connections If products must be returned, contact VMIC for a Return Material Authorization (RMA) Number. This RMA Number must be obtained prior to any return.
  • Page 37 QUICK-R-NET VMEnet Soft Logic Link VMEnet II SRTbus VMEprobe TESTCAL WinUIOC “The Next Generation PLC” Registered Trademarks of VME Microsystems International Corporation: UIOC  (VMIC logo) ® (I/O man figure) Other registered trademarks are the property of their respective owners.
  • Page 38 APPENDIX A ASSEMBLY DRAWING, PARTS LIST, AND SCHEMATIC...

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