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ERM Neoverse N1 Technical Reference Manual

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Arm
Neoverse
N1 System
®
™
Development Platform
Technical Reference Manual
Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved.
101489_0000_02_en

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Summary of Contents for ERM Neoverse N1

  • Page 1 Neoverse N1 System ® ™ Development Platform Technical Reference Manual Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved. 101489_0000_02_en...
  • Page 2 Neoverse N1 System Development Platform ® ™ Neoverse N1 System Development Platform ® ™ Technical Reference Manual Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved. Release Information Document History Issue Date Confidentiality Change 0000-00 01 March 2019 Confidential Alpha1 release 0000-01...
  • Page 3 Neoverse N1 System Development Platform ® ™ Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. Unrestricted Access is an Arm internal classification.

  • Page 4: Table Of Contents

    Contents Neoverse N1 System Development Platform ® ™ Technical Reference Manual Preface About this book ......................7 Feedback ........................10 Chapter 1 Introduction Precautions ......................1-12 About the N1 SDP ....................1-13 The N1 SDP at a glance ..................1-14 Getting started ............
  • Page 5 2.11 LEDs, switches, and buttons .................. 2-55 2.12 Debug ........................2-59 Chapter 3 Configuration Overview of the configuration process ..............3-61 Powerup and powerdown sequences ..............3-62 Configuration files ....................3-64 Configuration switches .................... 3-68 Use of reset push buttons ..................3-70 Command-line interface ..........
  • Page 6 Preface This preface introduces the Arm Neoverse N1 System Development Platform Technical Reference ® ™ Manual. It contains the following: • About this book on page • Feedback on page 101489_0000_02_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved.

  • Page 7: Preface

    Using this book This book is organized into the following chapters: Chapter 1 Introduction This chapter introduces the Arm Neoverse N1 System Development Platform (N1 SDP). Chapter 2 Hardware description This chapter describes the N1 SDP hardware. Chapter 3 Configuration This chapter describes the powerup and configuration process of the N1 SDP.
  • Page 8 Preface About this book <and> Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example: MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2> SMALL CAPITALS Used in body text for a few terms that have specific technical meanings, that are defined in the Glossary.
  • Page 9 Preface About this book Arm publications • Neoverse N1 Core Technical Reference Manual (100616). ® ™ • CoreLink ‑ 620 Dynamic Memory Controller Technical Reference Manual ® ™ (100568). • CoreLink ‑ 600 System Memory Management Unit Technical Reference Manual ®...

  • Page 10: Feedback

    Feedback on content If you have comments on content then send an e-mail to errata@arm.com. Give: • The title Arm Neoverse N1 System Development Platform Technical Reference Manual. • The number 101489_0000_02_en. • If applicable, the page number(s) to which your comments refer.
  • Page 11 Chapter 1 Introduction This chapter introduces the Arm Neoverse N1 System Development Platform (N1 SDP). It contains the following sections: • 1.1 Precautions on page 1-12. • 1.2 About the N1 SDP on page 1-13. • 1.3 The N1 SDP at a glance on page 1-14.

  • Page 12: Chapter 1 Introduction

    1 Introduction 1.1 Precautions Precautions This section describes precautions that ensure safety and prevent damage to your N1 SDP. This section contains the following subsections: • 1.1.1 Ensuring safety on page 1-12. • 1.1.2 Operating temperature on page 1-12. • 1.1.3 Preventing damage on page 1-12.

  • Page 13: About The N1 Sdp

    The N1 SDP consists of the N1 board containing the N1 SoC. The N1 board is a micro-ATX form factor board and is supplied in a standard PC tower unit. The N1 SoC contains two dual-core Arm Neoverse N1 processor clusters.

  • Page 14: The N1 Sdp At A Glance

    1 Introduction 1.3 The N1 SDP at a glance The N1 SDP at a glance The following figures show the PC tower back panel and front panel, and the N1 board. Figure 1-1 Back panel Figure 1-2 Front panel reset buttons 101489_0000_02_en Copyright ©...
  • Page 15 1 Introduction 1.3 The N1 SDP at a glance Figure 1-3 N1 board The following table describes the components, connectors, and push buttons. 101489_0000_02_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 1-15 reserved. Non-Confidential - Beta...
  • Page 16 1 Introduction 1.3 The N1 SDP at a glance Table 1-1 Key to figures Component Component name Access Comment number System LEDs Back panel. Configuration switches HDMI port PCC Ethernet port GbE port. USB 3.0 ports. USB 3.0 ports. DBG USB port N1 SoC trace port N1 SoC JTAG port Ribbon cable to N1 SoC JTAG port, connector 17, on...
  • Page 17 1 Introduction 1.3 The N1 SDP at a glance Table 1-1 Key to figures (continued) Component Component name Access Comment number Board. Remove side Arm supplies the N1 SDP with the following ribbon UART0, UART1, UART2, panel for access. cable connections: and UART3 5×2 way •...
  • Page 18 1 Introduction 1.3 The N1 SDP at a glance Table 1-1 Key to figures (continued) Component Component name Access Comment number Hardware reset button, Board. Remove side The front panel I/O connector: PBRESET panel for access. • Brings the PBON and PBRESET push button functions to the front panel.

  • Page 19: Getting Started

    1 Introduction 1.4 Getting started Getting started The N1 SDP is controlled from a serial terminal that you connect to the DBG USB port. A set of files in the non-volatile Motherboard Configuration Controller (MCC) configuration microSD card configures the board. The configuration microSD card is accessible through the DBG USB port. The board is factory-programmed with the MCC and Platform Controller Chip (PCC), System Control Processor (SCP), Manageability Control Processor (MCP), and Application Processor (AP) firmware.

  • Page 20: Accessing The Atx Power Cables

    1 Introduction 1.5 Accessing the ATX power cables Accessing the ATX power cables The N1 SDP PC tower provides SATA and other ATX power cables that you can use to connect to external hard drives. The power cables are accessed by removing the metal side panel. Warning Before accessing the ATX power cables, ensure that the unit is disconnected from the mains power supply.
  • Page 21 Chapter 2 Hardware description This chapter describes the N1 SDP hardware. It contains the following sections: • 2.1 N1 SDP hardware on page 2-22. • 2.2 N1 SoC on page 2-25. • 2.3 External power on page 2-27. • 2.4 Clocks on page 2-28.

  • Page 22: N1 Sdp Hardware

    2 Hardware description 2.1 N1 SDP hardware N1 SDP hardware The support logic and peripheral interfaces of the N1 SDP support access to the N1 SoC. Overview of the N1 SDP hardware The following figure shows a high-level view of the system architecture. N1 board IOFPGA eMMC...
  • Page 23 2 Hardware description 2.1 N1 SDP hardware Note The figure shows the default UART and USB connectivity between the components on the N1 board. The UART system is configurable using the settings in the file on the configuration config.txt microSD card. See the following for more information: •...
  • Page 24 2 Hardware description 2.1 N1 SDP hardware — Eight user LEDs. — I C master connector, for future external expansion. • Two reset push buttons: — On/Off/Soft reset button PBON. — Hardware reset button, PBRESET. • Programmable oscillators. • JTAG debug port. •...

  • Page 25: N1 Soc

    2 Hardware description 2.2 N1 SoC N1 SoC The following figure shows a high-level view of architecture of the N1 SoC. PCIe/CCIX ×16 slot PCIe switch IOFPGA N1 SoC Thin Links TLX-400 PCIe Gen 4 CCIX + TSIF root complex PCIe Gen 4 running as root complex...
  • Page 26 2 Hardware description 2.2 N1 SoC Major components of the N1 SoC The N1 SoC contains the following components and interfaces: • Two dual-core N1 clusters. Each cluster has: — 64KB private L1 data cache for each core, and 64KB private L1 instruction cache for each core. —...

  • Page 27: External Power

    2 Hardware description 2.3 External power External power A mains supply in the range 100-240V AC powers the N1 SDP. This section contains the following subsections: • 2.3.1 Overview of power scheme on page 2-27. • 2.3.2 Power islands on page 2-27.

  • Page 28: Clocks

    2 Hardware description 2.4 Clocks Clocks The N1 SDP clocks drive the board and the N1 SoC. This section contains the following subsections: • 2.4.1 Overview of clocks on page 2-28. • 2.4.2 SoC clocks on page 2-28. • 2.4.3 Clock programming and control on page 2-31.
  • Page 29 2 Hardware description 2.4 Clocks TRACE P-JTAG SWCLKTCK CLKA clusters OSC1 CPU0REFCLK CPU0PLL CPU0PLLCLK Trace TRACE Base OSC2 CPU1REFCLK CPU1PLL CPU1PLLCLK CLKB element OSC3 CLUSREFCLK CLUSPLL CLUSPLLCLK DDR4 OSC6 DMCREFCLK DMCPLL DMCPLLCLK PHY0 subsystem OSC4 INTREFCLK INTPLL INTPLLCLK DDR4 OSC0 SYSREFCLK SYSPLL SYSPLLCLK...
  • Page 30 2 Hardware description 2.4 Clocks The System Control Processor (SCP) configures the PLLs, muliplexers, and dividers in the clock system during bootup. The following table shows the N1 SoC clocks. Note The default clock frequencies in this table represent an example clock configuration which enables correct operation of the N1 SoC.
  • Page 31 2 Hardware description 2.4 Clocks Table 2-1 N1 SoC clocks (continued) Clock Source Default Description frequency SENSORCLK SYSPLL 100MHz Sensor clock SCPNICLK 300MHz SCP NIC-400 clock. SCPQSPICLK 50MHz SCP QSPI reference clock SCPI2CCLK 50MHz SCP I2C clock MCPNICCLK 300MHz MCP NIC-400 clock. MCPQSPICLK 50MHz MCP QSPI reference clock...
  • Page 32 2 Hardware description 2.4 Clocks Output clock frequency = (Input clock frequency/REFDIV)×FBDIV/POSTDIV where: • REFDIV is input frequency division value. • FBDIV is the PLL feedback division value. • POSTDIV is the PLL output frequency division value. The SCC PLL control registers set the values REFDIV, FBDIV, and POSTDIV for each PLL. Other SCC registers control the clock dividers and select the inputs for the internal clocks.
  • Page 33 2 Hardware description 2.4 Clocks Table 2-2 Clock control SCC registers (continued) Register Register function Register description MCPI2CCLK_CTRL Selects input clock to generate 4.5.19 MCPI2CCLK_CTRL Register on page 4-137. MCPI2CCLK. MCPI2CCLK_DIV Sets value of divider value to generate 4.5.20 MCPI2CCLK_DIV Register on page 4-138.
  • Page 34 2 Hardware description 2.4 Clocks 2.4.4 IOFPGA clocks Programmable clock generators on the N1 board generate clocks for the internal systems of the IOFPGA. The IOFPGA Thin Links interfaces generate clocks for data transmitted to the N1 SoC interfaces. The IOFPGA also generates the Serial Configuration Controller (SCC) clock data strobe.

  • Page 35: Resets

    2 Hardware description 2.5 Resets Resets The N1 SDP provides reset signals for the N1 board and N1 SoC. N1 board resets The N1 board has the following resets. Table 2-4 N1 board resets Reset Source Target Comment nPBRESET Motherboard Configuration Powerup reset.
  • Page 36 2 Hardware description 2.5 Resets MB and Power System Warm IOFPGA reset config config config boot boot running reset config MCC reset (PoR or PBRESET button PCC reset (MCC) PBON/User ON PSU_CTRL (MCC) IOFPGA_nPOR (MCC/IOFPGA) IOFPGA_nRST (MCC/IOFPGA) SOC_nPOR (MCC/IOFPGA) SOC_nRST (MCC/IOFPGA) Figure 2-5 Reset sequence Related information...

  • Page 37: Iofpga

    2 Hardware description 2.6 IOFPGA IOFPGA The IOFPGA provides access to low‑bandwidth peripherals that the N1 SoC does not provide. The N1 SoC connects to the IOFPGA through an AXI Thin Links (TLX‑400) master and slave interfaces. This section contains the following subsections: •...
  • Page 38 2 Hardware description 2.6 IOFPGA The following figure shows the internal architecture of the IOFPGA and its connectivity to external peripherals, the N1 SoC, the MCC, and the PCC. N1 SoC TLX-400 TLX-400 UART UART UART TMIF TSIF TLX-400 TLX-400 TMIF TSIF SMB to AHB...
  • Page 39 2 Hardware description 2.6 IOFPGA Note The UART system in the IOFPGA and N1 SoC is configurable using the settings in the file. config.txt See the following for information on the UART system, and on configuring the UART system. • 2.10 UARTs on page 2-51.
  • Page 40 2 Hardware description 2.6 IOFPGA N1 board N1 SoC IOFPGA AP_EXTAUXINT HDLCD IRQ[12] nIRQCPU0 AP_EXTINT TIMER IRQ[3:0] microSD IRQ[15] System IRQ[7:6] registers nIRQCPU1 SCP_EXTINT IRQ[18] UART IRQ[9:8] IRQ[5] NIC-400 nIRQCPU2 MCP_EXTINT WDOG IRQ[4] IRQ[19] MSCP_SS_RSTREQ GPIO IRQ[11:10] eMMC IRQ[16] QSPI IRQ[26] IRQ[27] IRQ[28]...
  • Page 41 2 Hardware description 2.6 IOFPGA Table 2-6 IOFPGA GIC-400 interrupt sources (continued) Interrupt ID IRQ level Source Comment IRQ[3] Timer 3 IRQ[4] Watchdog IRQ[5] Real Time Clock IRQ[6] CFGINT (System) IRQ[7] FUNINT (System) IRQ[8] UART 0 IRQ[9] UART 1 IRQ[10] GPIO 0 IRQ[11] GPIO 1...
  • Page 42 2 Hardware description 2.6 IOFPGA Table 2-7 IOFPGA output interrupts Interrupt ID Target Comment nIRQCPU0 Application Processors (AP) N1 SoC nIRQCPU1 System Control Processor (SCP) N1 SoC nIRQCPU2 Manageability Control Processor (MCP) N1 SoC nIRQCPU3 Motherboard Configuration Controller (MCC) N1 board nIRQCPU4 Platform Controller Chip (PCC) N1 board...

  • Page 43: Hdlcd Video

    2 Hardware description 2.7 HDLCD video HDLCD video An Arm HDLCD controller in the IOFPGA and an HDMI transmitter on the N1 board provide video graphics. The controller is a simple frame buffer which supports all common 24-bit RGB formats. The design supports XGA 1024×768kHz, 50-60Hz, compatible with major Linux distributions GUI installation interfaces.
  • Page 44 2 Hardware description 2.7 HDLCD video N1 SoC clusters Thin Links TMIF TLX-400 IOFPGA Thin Links TMIF DDR3 NIC-400 HDLCD IOFPGA_PXLCLK OSC7 PXLPLLCLK HDLCD audio PCLK 24-bit HDMI PHY HDMI HDMI N1 board Figure 2-8 HDLCD interface Related information 1.3 The N1 SDP at a glance on page 1-14 101489_0000_02_en Copyright ©...

  • Page 45: Pci Express And Ccix Systems

    2 Hardware description 2.8 PCI Express and CCIX systems PCI Express and CCIX systems The N1 SDP provides PCI Express Gen 4, and Cache-Coherent Interconnect for Accelerators (CCIX) expansion. This section contains the following subsections: • 2.8.1 Overview of PCIe and CCIX systems on page 2-45.
  • Page 46 2 Hardware description 2.8 PCI Express and CCIX systems N1 board N1 SoC Chip2Chip PCIe/ Slot 4 ×16 ×16 CCIX ×16 Slot 3 ×16 Slot 2 ×8 ×4 Slot 1 ×16 ×1 PCI Express and CCIX expansion slots ×16 PCIe Gen 3 PCIe switch ×1...
  • Page 47 2 Hardware description 2.8 PCI Express and CCIX systems — Enables use of a double slot 150W/300W card which covers slot 3 and makes it unusable. — Enables use of a double slot card in slot 1. • It is not possible to simultaneously use a ×16 Triple-slot card in slot 2 and a ×16 lane CCIX in slot 3. 2.8.3 SATA 3.0 ports The PCIe switch connects to the SATA 3.0 controller over a ×1 PCIe link.

  • Page 48: Chip To Chip Communications

    2 Hardware description 2.9 Chip to Chip communications Chip to Chip communications Certain connections between master and slave systems are necessary to enable Cache-Coherent Interconnect (CCIX) between two N1 SoCs. Chip to Chip Sideband signals Various sideband, Chip to Chip (C2C), signals are necessary to enable Cache-Coherent Interconnect (CCIX) between two N1 SoCs.
  • Page 49 2 Hardware description 2.9 Chip to Chip communications Master Slave N1 board N1 board N1 SoC N1 SoC SCP_I2C0_SDA SCP_I2C0_SDA SCP_I2C0_SCL SCP_I2C0_SCL MCP_I2C0_SDA MCP_I2C0_SDA MCP_I2C0_SCL MCP_I2C0_SCL Figure 2-11 C2C SCP and MCP I C connections Chip to Chip powerup synchronization To enable C2C powerup synchronization, the N1 boards must be connected together with the following cables: •...
  • Page 50 2 Hardware description 2.9 Chip to Chip communications Table 2-9 C2C connector wiring (continued) Master N1 System Development Platform Slave N1 System Development Platform MCP_SDA MCP_SDA PRESENT_IN PRESENT_OUT CTITRIGIN CTITRIGOUT CTITRIGOUTACK CTITRIGINACK GCNTSYNC_IN GCNTSYNC_OUT CTSSYNC_IN CTSSYNC_OUT CTSSYNC_OUT CTSSYNC_IN GCNTSYNC_OUT GCNTSYNC_IN CTITRIGINACK CTITRIGOUTACK CTITRIGOUT...

  • Page 51: Uarts

    2 Hardware description 2.10 UARTs 2.10 UARTs The N1 SDP UART system enables access to the N1 SoC and IOFPGA on the N1 board. 101489_0000_02_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-51 reserved. Non-Confidential - Beta...
  • Page 52 2 Hardware description 2.10 UARTs Overview of UART system The following figure shows the N1 SDP UART system and indicates the default and non-default connectivity settings. UART0 UART1 (back panel) (back panel) Ribbon Ribbon IOFPGA cable cable UART0 UART RS232 N1 SoC MCCUART 5×2 way...
  • Page 53 2 Hardware description 2.10 UARTs Note APUART1 is used to communicate through MCPUART1 internally within the SoCand is accessible to the Application Processor (AP) cores. MCPUART1 is not accessible to the AP cores. Default UART settings The system is configurable using the settings in the file.
  • Page 54 2 Hardware description 2.10 UARTs Table 2-11 config.txt file variables config.txt UART interface or connector Comment variable USBPORT1 Serial<>USB bridge PORT1 Serial<>USB bridge connects to DBG USB connector through the USB hub. USBPORT2 Serial<>USB bridge PORT2 USBPORT3 Serial<>USB bridge PORT3 USBPORT4 Serial<>USB bridge PORT4 UART0...

  • Page 55: Leds, Switches, And Buttons

    2 Hardware description 2.11 LEDs, switches, and buttons 2.11 LEDs, switches, and buttons There are system LEDs, user LEDs, user system buttons, configuration DIP switches and, user DIP switches on the N1 board. This section contains the following subsections: • 2.11.1 MCC system LEDs on page 2-55.
  • Page 56 2 Hardware description 2.11 LEDs, switches, and buttons Related information 1.3 The N1 SDP at a glance on page 1-14 2.11.3 IOFPGA LEDs The IOFPGA drives green LEDs on the N1 board to indicate Cache-Coherent Interconnect for Accelerators (CCIX) and Chip to Chip (C2C) activity. Removing the side panel provides access to the LEDs which are near the edge of the board.
  • Page 57 2 Hardware description 2.11 LEDs, switches, and buttons 2.11.4 Miscellaneous LEDs There are other system LEDs to indicate traffic to and from the N1 board. The following table shows miscellaneous system LEDs. Table 2-15 System LEDs Description Position Access Indicates Gigabit Ethernet LEDs 1×Yellow GbE port on back panel...
  • Page 58 2 Hardware description 2.11 LEDs, switches, and buttons Related information 1.3 The N1 SDP at a glance on page 1-14 101489_0000_02_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-58 reserved. Non-Confidential - Beta...

  • Page 59: Debug

    2 Hardware description 2.12 Debug 2.12 Debug The N1 SDP provides on-chip CoreSight debug technology to enable P-JTAG and 32-bit trace debug. The 20-pin box header on the back panel provides access to JTAG debug. The trace connector on the back panel provides access to JTAG debug and to 32-bit trace. 1.3 The N1 SDP at a glance on page 1-14 for the location of the JTAG and trace connectors on the back panel.
  • Page 60 Chapter 3 Configuration This chapter describes the powerup and configuration process of the N1 SDP. It contains the following sections: • 3.1 Overview of the configuration process on page 3-61. • 3.2 Powerup and powerdown sequences on page 3-62. • 3.3 Configuration files on page 3-64.

  • Page 61: Chapter 3 Configuration

    3 Configuration 3.1 Overview of the configuration process Overview of the configuration process The Motherboard Configuration Controller (MCC), the Platform Controller Chip (PCC) together with the configuration microSD card, configure the N1 SDP during powerup or reset. The MCC uses information in the configuration EEPROM and the configuration microSD card during the configuration process, including the board HBI number.

  • Page 62: Powerup And Powerdown Sequences

    3 Configuration 3.2 Powerup and powerdown sequences Powerup and powerdown sequences The ON/OFF/Soft Reset, PBON, the Hardware Reset button, PBRESET, and powerdown requests from the operating system initiate the powerup and powerdown sequences. Powerup sequence from powered down state The powerup sequence of the N1 board is as follows: 1.
  • Page 63 3 Configuration 3.2 Powerup and powerdown sequences 9. The PCC requests a powerdown from the MCC using the SPI bus. 10. The MCC asserts nPOR, disables the board clocks and the ATXPSU. 11. The system is now in the standby state and waits for a short press of the PBON button. Related information 1.3 The N1 SDP at a glance on page 1-14 101489_0000_02_en...

  • Page 64: Configuration Files

    3 Configuration 3.3 Configuration files Configuration files Configuration files in the configuration microSD card control the board powerup and configuration process. This section contains the following subsections: • 3.3.1 Overview of configuration files and microSD card directory structure on page 3-64.
  • Page 65 3 Configuration 3.3 Configuration files file config.txt Generic configuration file for all motherboards. This file applies to all Arm development boards including the N1 board. directory LICENSES Contains one license text file. directory Contains one or more HBI subdirectories for board variants. The subdirectory names match the HBI codes for the board variants.
  • Page 66 3 Configuration 3.3 Configuration files file Points to the BIOS image that the MCC loads during configuration. board.txt file Points to the SCP and MCP image files. images.txt Files of the form IOFPGA image files for different board variants. io_v???.bit File of the form IOFPGA configuration files for different board variants.
  • Page 67 3 Configuration 3.3 Configuration files OSC10: 24.576 ;OSC3-Y4 - IOFPGA_AUDCLK OSC11: 24.0 ;OSC3-Y6 - IOFPGA_RSVDCLK [HARDWARE CONTROL] ;ASSERTNPOR: TRUE ;External resets assert nPOR !TBA [PERIPHERAL SUPPORT] FPGA_SMB: TRUE ;SMB interface is supported (MCC_SMC<>FPGA_SMB) FPGA_SCC: TRUE ;SCC interface is supported SCCREG: 0x68130000 ;SCC registers base address FPGA_DDR: TRUE...

  • Page 68: Configuration Switches

    3 Configuration 3.4 Configuration switches Configuration switches There are configuration switches SW0 and SW1 on the back panel. This section contains the following subsections: • 3.4.1 Use of configuration switches on page 3-68. • 3.4.2 Remote UART configuration on page 3-68.
  • Page 69 3 Configuration 3.4 Configuration switches Server or host N1 SDP computer UART UART connector connector STANDBY LOW = SYSTEM HIGH = MCC Figure 3-2 Modem cable wiring You can control the SER0_DSR and SER0_CTS signals using control logic on the host computer. Alternatively, you can use a custom terminal program such as that Arm provides on the VETerminal.exe...

  • Page 70: Use Of Reset Push Buttons

    3 Configuration 3.5 Use of reset push buttons Use of reset push buttons The On/Off/Soft reset button, PBON, initiates the powerup and powerdown sequences. The Hardware reset button, PBRESET, initiates a hardware reset. In standby state, press the PBON button briefly, less than two seconds, to initiate the powerup sequence. In the operating state, press the PBON button for longer than two seconds to initiate the powerdown sequence.

  • Page 71: Command-Line Interface

    3 Configuration 3.6 Command-line interface Command-line interface The N1 SDP command‑line interface supports system command-line input to the Motherboard Configuration Controller (MCC). This section contains the following subsections: • 3.6.1 Overview of the N1 SDP MCC command-line interface on page 3-71.
  • Page 72 3 Configuration 3.6 Command-line interface Table 3-1 N1 SDP MCC main command menu (continued) Command Description RESET Reset the N1 SoC using the SoC_nSRST reset signal. SHUTDOWN Shut down the power supply but leave the MCC running. The board returns to Standby mode. TYPE filename Display the contents of text file filename.
  • Page 73 3 Configuration 3.6 Command-line interface Table 3-3 N1 SDP EEPROM commands (continued) Command Description ERASECON [0] Erase configuration section of EEPROM. ERASEDEV [0] Erase device section of EEPROM. ERASERANGE [0] start end Erase EEPROM between start and end. ERASEIMAGE image_id Erase image, named image_id, stored in Motherboard EEPROM.
  • Page 74 Chapter 4 Programmers model This chapter describes the programmers model of the N1 SDP. It contains the following sections: • 4.1 About this programmers model on page 4-75. • 4.2 N1 SDP memory maps on page 4-76. • 4.3 N1 SoC interrupt maps on page 4-95.

  • Page 75: About This Programmers Model

    4 Programmers model 4.1 About this programmers model About this programmers model The following information applies to all registers in this programmers model: • Do not attempt to access reserved or unused address locations. Attempting to access these locations can result in behavior.

  • Page 76: N1 Sdp Memory Maps

    4 Programmers model 4.2 N1 SDP memory maps N1 SDP memory maps The N1 SDP contains Application Processor (AP), System Control Processor (SCP), and Manageability Control Processor (MCP) memory maps. The SCP and MCP memory maps are private. The masters which can access the AP memory map have no access to the components in the SCP and MCP memory maps.
  • Page 77 4 Programmers model 4.2 N1 SDP memory maps Reserved 0x49_0000_0000 CCIX MMI064 memory space (CCIX slave AXI) 0x29_0000_0000 PCIe MMI064 memory space (PCIe slave AXI) 0x09_0000_0000 0x3FF_FFFF_FFFF IOFPGA TLX master interface 0x05_0000_0000 DRAM2 0x100_0000_0000 Reserved 0x00_7520_0000 PCIe MMI032 memory space DRAM1 (PCIe slave AXI) 0x00_7120_0000...
  • Page 78 4 Programmers model 4.2 N1 SDP memory maps Table 4-1 AP memory map Address range Size Description From 0x0_0000_0000 0x0_0007_FFFF 512KB Boot region-Secure boot ROM 0x0_0400_0000 0x0_0407_FFFF 512KB Boot region-Trusted RAM 0x0_0500_0000 0x0_0507_FFFF 512KB Boot region-Non-trusted ROM 0x0_0600_0000 0x0_0607_FFFF 512KB Boot region-Non-trusted RAM 0x0_0080_0000 0x0_13FF_FFFF 192MB IOFPGA peripherals...
  • Page 79 4 Programmers model 4.2 N1 SDP memory maps Table 4-1 AP memory map (continued) Address range Size Description From 0x29_0000_0000 0x48_FFFF_FFFF 128GB CCIX MMI064 memory space. CCIX slave AXI. 0x80_8000_0000 0xFF_FFFF_FFFF 510GB DRAM1 0x100_0000_0000 0x3FF_FFFF_FFFF 3TB DRAM2 4.2.2 Application Processor subsystem peripherals memory map The Application Processor (AP) memory map of the N1 SDP contains a region associated with the subsystem peripherals.
  • Page 80 4 Programmers model 4.2 N1 SDP memory maps SMMU 0x00_4F00_0000 Memory Element 0x00_4E00_0000 Base STM 0x00_4D00_0000 Reserved 0x00_4C43_0000 Reserved AP2MCP MHU Secure RAM 0x00_4F48_0000 0x00_4C42_0000 PCIe TBU1 0x00_4F46_0000 AP2MCP MHU Non-Secure PCIe TBU0 0x00_4F44_0000 0x00_4C41_0000 PCIe TCU1 AP2MCP MHU 0x00_4F40_0000 0x00_4C40_0000 Reserved 0x00_4F08_0000...
  • Page 81 4 Programmers model 4.2 N1 SDP memory maps The following table shows the subsystem peripherals region of the AP memory map. Undefined locations of the memory map are reserved. Software must not attempt to access these locations. Table 4-2 AP peripherals memory map Address range Size Description...
  • Page 82 4 Programmers model 4.2 N1 SDP memory maps Table 4-2 AP peripherals memory map (continued) Address range Size Description From 0x00_300C_0000 0x00_300C_FFFF 64KB GICR registers 0x00_4410_0000 0x00_4410_FFFF 64KB REFCLK general timer control 0x00_4411_0000 0x00_4411_FFFF 64KB Cluster 0 time frame 0x00_4412_0000 0x00_4412_FFFF 64KB Cluster 1 time frame 0x00_4500_0000 0x00_4500_FFFF 64KB SCP Message Handling Unit0 (MHU0)
  • Page 83 4 Programmers model 4.2 N1 SDP memory maps 4.2.3 Manageability Control Processor memory map The following figure shows the N1 SDP Manageability Control Processor (MCP) memory map. 0x01_0000_0000 Reserved 0x0_E010_0000 Private peripheral bus - External 0x0_E004_0000 Private peripheral bus - Internal 0x0_E000_0000 System Access Port 0x0_A000_0000...
  • Page 84 4 Programmers model 4.2 N1 SDP memory maps Table 4-3 MCP memory map Address range Size Description From 0x0_0000_0000 0x0_007F_FFFF 8MB Code boot ROM 0x0_0080_0000 0x0_00FF_FFFF 8MB Code TCRAM 0x0_0100_0000 0x0_15FF_FFFF 336MB Reserved part of MCP SoC expansion memory 0x0_1600_0000 0x0_17FF_FFFF 32MB TMIF interface 0x0_1800_0000 0x0_1FFF_FFFF 128MB Reserved part of MCP SoC expansion memory 0x0_2000_0000 0x0_20FF_FFFF 16MB...
  • Page 85 4 Programmers model 4.2 N1 SDP memory maps The following figure shows the peripherals region of the MCP memory map. 0x01_0000_0000 Reserved 0x0_E010_0000 Private peripheral bus - External 0x0_E004_0000 Private peripheral bus - Internal 0x0_E000_0000 System Access Port 0x0_A000_0000 System Access Port 0x0_6000_0000 0x0_6000_0000 Reserved...
  • Page 86 4 Programmers model 4.2 N1 SDP memory maps Table 4-4 MCP peripherals memory map (continued) Address range Size Description From 0x00_4562_0000 0x00_4562_FFFF 64KB SCP2 MCP MHU Secure RAM 0x00_4C00_0000 0x00_4C00_0FFF 4KB REFCLK CNTCTL 0x00_4C00_1000 0x00_4C00_1FFF 4KB REFCLK CNTBase0 0x00_4C00_2000 0x00_4C00_2FFF 4KB MCPUART0 0x00_4C00_3000 0x00_4C00_3FFF 4KB MCPUART1...
  • Page 87 4 Programmers model 4.2 N1 SDP memory maps 4.2.5 System Control Processor memory map The following figure shows the N1 SDP System Control Processor (SCP) memory map. 0x01_0000_0000 Reserved 0x0_E010_0000 Private peripheral bus - External 0x0_E004_0000 Private peripheral bus - Internal 0x0_E000_0000 System Access Port 0x0_A000_0000...
  • Page 88 4 Programmers model 4.2 N1 SDP memory maps Table 4-5 SCP memory map (continued) Address range Size Description From 0x0_0100_0000 0x0_13FF_FFFF 304MB Reserved part of SCP SoC expansion memory 0x0_1400_0000 0x0_15FF_FFFF 32MB TMIF interface 0x0_1600_0000 0x0_1FFF_FFFF 160MB Reserved part of SCP SoC expansion memory 0x0_2000_0000 0x0_20FF_FFFF 16MB SRAM DTCRAM 0x0_2100_0000 0x0_2FFF_FFFF 240MB Reserved part of SCP SoC expansion memory...
  • Page 89 4 Programmers model 4.2 N1 SDP memory maps Table 4-5 SCP memory map (continued) Address range Size Description From 0x0_E004_0000 0x0_E00F_FFFF 768KB Private peripheral bus - External. 0x0_E010_0000 0x0_FFFF_FFFF 511MB Reserved 4.2.6 System Control Processor peripherals memory map The System Control Processor (SCP) memory map of the N1 SDP contains a region associated with the SCP peripherals.
  • Page 90 4 Programmers model 4.2 N1 SDP memory maps The following table shows the peripherals region of the N1 SDP SCP memory map. Undefined locations of the memory map are reserved. Software must not attempt to access these locations. Table 4-6 SCP peripherals memory map Address range Size Description...
  • Page 91 4 Programmers model 4.2 N1 SDP memory maps 0x3FF_FFFF_FFFF Reserved DRAM2 0x04_020F_0000 CLUS0 CLUS CTI 0x04_020E_0000 0x100_0000_0000 CLUS0 CLUS ELA 0x04_020D_0000 CLUS0 ELA 0x04_020C_0000 DRAM1 Reserved 0x04_0203_0000 0x80_8000_0000 CLUS0 CTI 0x04_0202_0000 Reserved 0x04_0100_8000 Expansion AXI2 EXP CTI2 0x04_0100_7000 0x05_0000_0000 CCIX/PCIE PIPE ELA 0x04_0100_6000 CCIX PHY PIPE ELA CoreSight subsystem...
  • Page 92 4 Programmers model 4.2 N1 SDP memory maps Table 4-7 CoreSight debug and trace memory map (continued) Address range Size Description From 0x04_0100_1000 0x04_0100_1FFF 4KB EXP CTI0/CTI1 0x04_0100_2000 0x04_0100_2FFF 4KB PCIE PHY PIPE ELA 0x04_0100_3000 0x04_0100_3FFF 4KB DDR PHY0 ELA 0x04_0100_4000 0x04_0100_4FFF 4KB DDR PHY1 ELA 0x04_0100_5000 0x04_0100_5FFF 4KB...
  • Page 93 4 Programmers model 4.2 N1 SDP memory maps 4.2.8 IOFPGA memory map The following figure shows the memory map of the peripherals inside the IOFPGA. Reserved 0x00_1D30_0000 SRAM 0x00_1D20_0000 Reserved 0x00_1D10_0000 Reserved 0x3FF_FFFF_FFFF 0x00_1D00_0000 Reserved DRAM2 0x00_1CA1_0000 GIC-400 0x00_1CA0_0000 0x100_0000_0000 Reserved 0x00_1C15_0000 SMC configuration...
  • Page 94 4 Programmers model 4.2 N1 SDP memory maps Table 4-8 IOFPGA memory map (continued) Address range Size Description From 0x1C00_0000 0x1C00_FFFF 64MB 0x1C01_0000 0x1C01_FFFF 64KB System registers 0x1C02_0000 0x1C02_FFFF 64KB System control 0x1C03_0000 0x1C03_FFFF 64KB PCIe SW I2C 0x1C04_0000 0x1C04_FFFF 64KB SoC DDR SPD 0x1C05_0000 0x1C05_FFFF 64KB HDLCD configuration...

  • Page 95: N1 Soc Interrupt Maps

    4 Programmers model 4.3 N1 SoC interrupt maps N1 SoC interrupt maps The N1 SoC contains three independent interrupt maps for the Application Processors (APs), the System Control Processor (SCP), and the Manageability Control Processor (MCP). This section contains the following subsections: •...
  • Page 96 4 Programmers model 4.3 N1 SoC interrupt maps Table 4-10 Shared peripheral interrupts (continued) Source Description DMC1_ecc_err ECC Error from DMC1 66-40 Reserved MCP2APMHU_NS MHU Non-secure interrupt Reserved MCP2APMHU_S MHU secure interrupt CATU CATUADDRERROR interrupt ETRBUFINT interrupt 77-72 Reserved CMN600_ INTREQPMU_DTC0 PMU Count Overflow Interrupt 82-79 Reserved...
  • Page 97 4 Programmers model 4.3 N1 SoC interrupt maps Table 4-10 Shared peripheral interrupts (continued) Source Description N1 SoC pcie_local_interrupt_reset N1 SoC pcie_performance_data_threshold N1 SoC pcie_negotiated_speed_change N1 SoC pcie_link_training_done N1 SoC pcie_pll_status_rise N1 SoC pcie_message_fifo_interrupt N1 SoC pcie_local_interrupt_ras 231-215 - Reserved N1 SoC ccix_bus_device_change_irq N1 SoC...
  • Page 98 4 Programmers model 4.3 N1 SoC interrupt maps Table 4-10 Shared peripheral interrupts (continued) Source Description MMUTCU2_PMU_IRPT PMU interrupt MMUTCU2_EVENT_Q_IRPT_S Event Queue Secure interrupt, indicating Event Queue Non-Empty or Overflow MMUTCU2_CMD_SYNC_IRPT_S SYNC Complete Secure interrupt MMUTCU2_GLOBAL_IRPT_S Global Secure interrupt MMUTCU2_EVENT_Q_IRPT_NS Event Queue non-Secure interrupt, indicating Event Queue Non-Empty or Overflow MMUTCU2_CMD_SYNC_IRPT_NS...
  • Page 99 4 Programmers model 4.3 N1 SoC interrupt maps Table 4-11 SCP interrupts (continued) Source Description CoreSight CoreSight debug power up request (If there is a separate debug power domain). Note SCP Firmware must support optional debug power up rail. CoreSight CoreSight system power up request CoreSight CoreSight debug reset request...
  • Page 100 4 Programmers model 4.3 N1 SoC interrupt maps Table 4-11 SCP interrupts (continued) Source Description 58-56 Reserved CPU Core Fault Indicator Consolidated nFaultIRQ for both clusters 63-60 Reserved CPU ECC error interrupts Consolidated nERRIRQ for both clusters 68-64 Reserved Cluster PLLs Consolidated lock interrupt for cluster PLLs Cluster PLLs Consolidated unlock interrupt for cluster PLLs...
  • Page 101 4 Programmers model 4.3 N1 SoC interrupt maps Table 4-11 SCP interrupts (continued) Source Description INTPLL_UNLOCK Interconnect PLL UnLock 173-144 - Reserved DMC_PLL_LOCK DMC PLL Lock DMC_PLL_UNLOCK DMC PLL Unlock 179-176 - Reserved DMC0 Interrupts DMC0 _misc oflow DMC0 _err_oflow DMC0 _ecc_err_int DMC0 _misc_access_int DMC0 _temperature_event_int...
  • Page 102 4 Programmers model 4.3 N1 SoC interrupt maps Table 4-11 SCP interrupts (continued) Source Description ccix_negotiated_speed_change ccix_negotiated_speed_change ccix_link_training_done ccix_link_training_done ccix_pll_status_rise ccix_pll_status_rise ccix_message_fifo_interrupt ccix_message_fifo_interrupt ccix_local_interrupt_ras ccix_local_interrupt_ras ccix_hot_reset_irq ccix_hot_reset_irq ccix_flr_reset_irq ccix_flr_reset_irq ccix_power_state_change_irq ccix_power_state_change_irq pcie_aer_interrupt pcie_aer_interrupt pcie_local_interrupt_reset pcie_local_interrupt_reset pcie_local_interrupt_ras pcie_local_interrupt_ras 4.3.3 Manageability Control Processor interrupt map The Manageability Control Processor (MCP) receives interrupts from several sources.
  • Page 103 4 Programmers model 4.3 N1 SoC interrupt maps Table 4-12 MCP interrupts (continued) Source Description 25-18 GPIO GPIO individual IRQ [7:0] 32-26 Reserved MCP REFCLK Generic Timer REFCLK Physical Timer interrupt Non-secure AP2MCP MHU MHU Non-Secure interrupt Reserved AP2MCP Secure MHU MHU Secure interrupt CTI Trigger 0 CTI Trigger 1...
  • Page 104 4 Programmers model 4.3 N1 SoC interrupt maps Table 4-12 MCP interrupts (continued) Source Description DMC1 Interrupts DMC1 _misc oflow DMC1 _err_oflow DMC1 _ecc_err_int DMC1 _misc_access_int DMC1 _temperature_event_int DMC1 _failed_access_int DMC1 _mgr_int MCP C2C I2C MCP C2C I2C interrupt (I2C0) MCP BMC-PCC I2C MCP BMC-PCC I2C interrupt (I2C1) MCP-QSPI...

  • Page 105: System Security Control Registers

    4 Programmers model 4.4 System Security Control registers System Security Control registers The System Security Control (SSC) interface in the N1 SoC controls system-wide security features. These features include the following: • Selection of and internal sources for Debug Authentication signals •...
  • Page 106 4 Programmers model 4.4 System Security Control registers Table 4-13 SCC registers summary (continued) Offset Name Type Reset Width Description 0x0028 0x0000_0000 32 SSC_AUXDBGCFG Auxiliary debug authentication register. 4.4.5 SSC_AUXDBGCFG Register on page 4-110. 0x0030 0x0000_0000 32 SSC_GPRETN General purpose secure retention status. 4.4.6 SSC_GPRETN Register on page 4-111.
  • Page 107 4 Programmers model 4.4 System Security Control registers Table 4-13 SCC registers summary (continued) Offset Name Type Reset Width Description 0x0FF8 0x0000_0005 32 COMPID2 Component ID2 register 4.4.18 SSC_COMPID2 Register on page 4-117. 0x0FFC COMPID3 0x0000_00B1 32 Component ID3 register 4.4.19 SSC_COMPID3 Register on page 4-118.
  • Page 108 4 Programmers model 4.4 System Security Control registers Table 4-14 SSC_DBGCFG_STAT Register bit assignments (continued) Bits Name Type Function SPNIDEN_SEL_STAT Selects between SPNIDEN external or internal drive: 0b0: External. 0b1: Internal. If external mode is selected SPNIDEN is driven by top-level configuration input. Reset value 0b0.
  • Page 109 4 Programmers model 4.4 System Security Control registers Table 4-15 SSC_DBGCFG_SET Register bit assignments Bits Name Type Function [31:8] Reserved. SPIDEN_SEL_SET Sets SPIDEN_SEL_STAT to 0b1: 0b0: No effect. 0b1: Set SPIDEN_SEL_STAT to 0b1. SPIDEN_INT_SET Sets SPIDEN_INT_STAT to 0b1: 0b0: No effect. 0b1: Set SPIDEN_INT_STAT to 0b1.
  • Page 110 4 Programmers model 4.4 System Security Control registers Table 4-16 SSC_DBGCFG_CLR Register bit assignments Bits Name Type Function [31:8] Reserved. SPIDEN_SEL_CLR Clears SPIDEN_SEL_STAT to 0b1: 0b0: No effect. 0b1: Clear SPIDEN_SEL_STAT to 0b0. SPIDEN_INT_CLR Clears SPIDEN_INT_STAT to 0b1: 0b0: No effect. 0b1: Clear SPIDEN_INT_STAT to 0b0.
  • Page 111 4 Programmers model 4.4 System Security Control registers The following table shows the SSC_AUXDBGCFG Register bit assignments. Table 4-17 SSC_AUXDBGCFG Register bit assignments Bits Name Type Function [31:2] Reserved. [1:0] INTERNAL_DEBUG_OVERRIDE 0b00: Enable Non-secure self-hosted debug. DBGEN and NIDEN inputs to the application processors are HIGH.
  • Page 112 4 Programmers model 4.4 System Security Control registers 4.4.7 SSC_VERSION Register The SSC_VERSION Register characteristics are: Purpose The SSC_VERSION register is a Secure access read-only memory mapped register that specifies the N1 SoC version ID for security purposes. Usage constraints This register is read-only.
  • Page 113 4 Programmers model 4.4 System Security Control registers Purpose The SSC_SW_CAP registers are capability registers used by the System Control Processor (SCP) software to record the design configuration. Usage constraints There are no usage constraints. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.4.1 System Security Control registers summary on page 4-105.
  • Page 114 4 Programmers model 4.4 System Security Control registers Purpose The SSC_CHIPID_ST register stores the CHIPID status for the node when there are multiple sockets. Usage constraints This register is read-only. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.4.1 System Security Control registers summary on page 4-105.
  • Page 115 4 Programmers model 4.4 System Security Control registers Table 4-24 SSC_PID4 Register bit assignments Bits Name Type Function [31:8] Reserved. [7:4] SIZE LOG2 of the number of 4KB blocks occupied by the interface. Reset value 0x0. [3:0] DES_2 JEP106 continuation code to identify designer Reset value 0x4 for Arm 4.4.13 SSC_PID0 Register...
  • Page 116 4 Programmers model 4.4 System Security Control registers Table 4-26 SSC_PID1 Register bit assignments Bits Name Type Function [31:8] Reserved. [7:4] DES_0 Bits[3:0] of JEP identity. Reset value 0xB. [3:0] PART_1 Bits[11:8] of part number. Reset value 0x8. 4.4.15 SSC_PID2 Register The SSC_PID2 Register characteristics are: Purpose Stores peripheral identification information.
  • Page 117 4 Programmers model 4.4 System Security Control registers Memory offset and full register reset value 4.4.1 System Security Control registers summary on page 4-105. The following table shows the SSC_COMPID0 Register bit assignments. Table 4-28 SSC_COMPID0 Register bit assignments Bits Name Type Function...
  • Page 118 4 Programmers model 4.4 System Security Control registers Table 4-30 SSC_COMPID2 Register bit assignments Bits Name Type Function [31:8] Reserved. [7:0] SSC_COMPID2 Component ID 2 information. Reset value 0x05. 4.4.19 SSC_COMPID3 Register The SSC_COMPID3 Register characteristics are: Purpose The SSC_COMPID3 register stores component identification information. Usage constraints This register is read-only.

  • Page 119: Serial Configuration Control Registers

    4 Programmers model 4.5 Serial Configuration Control registers Serial Configuration Control registers The Serial Configuration Control (SCC) registers contain the initial settings of blocks before bootup. Write and read accesses to these registers during run‑time enable software to alter and to read block settings.
  • Page 120 4 Programmers model 4.5 Serial Configuration Control registers • 4.5.50 TARGETIDAPP Register on page 4-165. • 4.5.51 TARGETIDSCP Register on page 4-165. • 4.5.52 TARGETIDMCP Register on page 4-166. • 4.5.53 BOOT_GPR0 Register on page 4-166. • 4.5.54 BOOT_GPR1 Register on page 4-167.
  • Page 121 4 Programmers model 4.5 Serial Configuration Control registers Table 4-32 SCC registers summary Offset Name Type Reset Width Description 0x0004 PMCLK_DIV RW/RO 0x0001_0001 32 4.5.2 PMCLK_DIV Register on page 4-124. 0x000C SYSAPBCLK_CTRL RW/RO 0x0000_0101 32 4.5.3 SYSAPBCLK_CTRL Register on page 4-125.
  • Page 122 4 Programmers model 4.5 Serial Configuration Control registers Table 4-32 SCC registers summary (continued) Offset Name Type Reset Width Description 0x0088 PCIEAXICLK_DIV RW/RO 0x0001_0001 32 4.5.24 PCIEAXICLK_DIV Register on page 4-141. 0x0090 CCIXAXICLK_CTRL RW/RO 0x0000_0101 32 4.5.25 CCIXAXICLK_CTRL Register on page 4-142.
  • Page 123 4 Programmers model 4.5 Serial Configuration Control registers Table 4-32 SCC registers summary (continued) Offset Name Type Reset Width Description 0x0168 SCP_BOOT_ADR RW/RO 0x0000_0000 32 4.5.47 SCP_BOOT_ADR Register on page 4-163. 0x016C MCP_BOOT_ADR RW/RO 0x0000_0000 32 4.5.48 MCP_BOOT_ADR Register on page 4-164.
  • Page 124 4 Programmers model 4.5 Serial Configuration Control registers Table 4-32 SCC registers summary (continued) Offset Name Type Reset Width Description 0x01D8 SCDBG_CTRL RW/RO 0x0000_0000 32 4.5.72 SCDBG_CTRL Register on page 4-176. 0x01DC EXP_IF_CTRL 0x0000_0000 32 4.5.73 EXP_IF_CTRL Register on page 4-178.
  • Page 125 4 Programmers model 4.5 Serial Configuration Control registers Usage constraints Bits[20:16] are read-only. Bits[4:0] are read/write. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the PMCLK_DIV Register bit assignments. Table 4-33 PMCLK_DIV Register bit assignments Bits Name...
  • Page 126 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the SYSAPBCLK_CTRL Register bit assignments. Table 4-34 SYSAPBCLK_CTRL Register bit assignments Bits Name Type Function [31:12] - Reserved. [11:8] CLKSEL_CUR Current value of source for SYSAPBCLK: 0b0001: Source is REFCLK. 0b0010: Source is divided SYSPLLCLK.
  • Page 127 4 Programmers model 4.5 Serial Configuration Control registers Table 4-35 SYSAPBCLK _DIV Register bit assignments (continued) Bits Name Type Function [15:5] Reserved. [4:0] CLKDIV Sets clock division value. Division value=CLKDIV_CUR+1. Reset value 0b10011, division value=20. Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC.
  • Page 128 4 Programmers model 4.5 Serial Configuration Control registers Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC. Further SoC testing and measurement, by Arm or by other developers, might result in new register values.
  • Page 129 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the IOFPGA_TSIF2XCLK_CTRL Register bit assignments. Table 4-38 IOFPGA_TSIF2XCLK_CTRL Register bit assignments Bits Name Type Function...
  • Page 130 4 Programmers model 4.5 Serial Configuration Control registers Table 4-39 IOFPGA_TSIF2XCLK_DIV Register bit assignments (continued) Bits Name Type Function [15:5] Reserved. [4:0] CLKDIV Sets clock division value. Division value=CLKDIV_CUR+1. Reset value 0b10011, division value=20. Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC.
  • Page 131 4 Programmers model 4.5 Serial Configuration Control registers Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC. Further SoC testing and measurement, by Arm or by other developers, might result in new register values.
  • Page 132 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the SCPI2CCLK_CTRL Register bit assignments. Table 4-42 SCPI2CCLK_CTRL Register bit assignments Bits Name Type Function...
  • Page 133 4 Programmers model 4.5 Serial Configuration Control registers Table 4-43 SCPI2CCLK_DIV Register bit assignments (continued) Bits Name Type Function [15:5] Reserved. [4:0] CLKDIV Sets clock division value. Division value=CLKDIV_CUR+1. Reset value 0b00000, division value=1. Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC.
  • Page 134 4 Programmers model 4.5 Serial Configuration Control registers Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC. Further SoC testing and measurement, by Arm or by other developers, might result in new register values.
  • Page 135 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the SENSORCLK_CTRL Register bit assignments. Table 4-46 SENSORCLK_CTRL Register bit assignments Bits Name Type Function...
  • Page 136 4 Programmers model 4.5 Serial Configuration Control registers Table 4-47 SENSORCLK_DIV Register bit assignments (continued) Bits Name Type Function [15:5] Reserved. [4:0] CLKDIV Sets clock division value. Division value=CLKDIV_CUR+1. Reset value 0b10111, division value=24. Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC.
  • Page 137 4 Programmers model 4.5 Serial Configuration Control registers Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC. Further SoC testing and measurement, by Arm or by other developers, might result in new register values.
  • Page 138 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the MCPI2CCLK_CTRL Register bit assignments. Table 4-50 MCPI2CCLK_CTRL Register bit assignments Bits Name Type Function...
  • Page 139 4 Programmers model 4.5 Serial Configuration Control registers Table 4-51 MCPI2CCLK_DIV Register bit assignments (continued) Bits Name Type Function [15:5] Reserved. [4:0] CLKDIV Sets clock division value. Division value=CLKDIV_CUR+1. Reset value 0b00000, division value=1. Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC.
  • Page 140 4 Programmers model 4.5 Serial Configuration Control registers Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC. Further SoC testing and measurement, by Arm or by other developers, might result in new register values.
  • Page 141 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the PCIEAXICLK_CTRL Register bit assignments. Table 4-54 PCIEAXICLK_CTRL Register bit assignments Bits Name Type Function...
  • Page 142 4 Programmers model 4.5 Serial Configuration Control registers Table 4-55 PCIEAXICLK_DIV Register bit assignments (continued) Bits Name Type Function [15:5] Reserved. [4:0] CLKDIV Sets clock division value. Division value=CLKDIV_CUR+1. Reset value 0b00001, division value=2. Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC.
  • Page 143 4 Programmers model 4.5 Serial Configuration Control registers Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC. Further SoC testing and measurement, by Arm or by other developers, might result in new register values.
  • Page 144 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the PCIEAPBCLK_CTRL Register bit assignments. Table 4-58 PCIEAPBCLK_CTRL Register bit assignments Bits Name Type Function...
  • Page 145 4 Programmers model 4.5 Serial Configuration Control registers Table 4-59 PCIEAPBCLK_DIV Register bit assignments (continued) Bits Name Type Function [15:5] Reserved. [4:0] CLKDIV Sets clock division value. Division value=CLKDIV_CUR+1. Reset value 0b01011, division value=12. Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC.
  • Page 146 4 Programmers model 4.5 Serial Configuration Control registers Note The example values in this register, and the clock frequency they generate, are part of a clock configuration which enables correct operation of the N1 SoC. Further SoC testing and measurement, by Arm or by other developers, might result in new register values.
  • Page 147 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the SYS_CLK_EN Register bit assignments. Table 4-62 SYS_CLK_EN Register bit assignments Bits Name Type Function...
  • Page 148 4 Programmers model 4.5 Serial Configuration Control registers Table 4-62 SYS_CLK_EN Register bit assignments (continued) Bits Name Type Function SENSORCLKEN Enable clock SENSORCLK: 0b0: Clock disabled. 0b1: Clock enabled. Reset value 0b1. SCPQSPICLKEN Enable clock SCPQSPICLK: 0b0: Clock disabled. 0b1: Clock enabled. Reset value 0b1.
  • Page 149 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the CPU0_PLL_CTRL0 Register bit assignments. Table 4-63 CPU0_PLL_CTRL0 Register bit assignments Bits Name Type Function...
  • Page 150 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the CPU0_PLL_CTRL1 Register bit assignments. Table 4-64 CPU0_PLL_CTRL1 Register bit assignments Bits Name Type Function [31] Reserved. [30:28] POSTDIV2 Second post-divide value. Post-divide value=POSTDIV2. Reset value 0b1. [27] Reserved.
  • Page 151 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the CPU1_PLL_CTRL0 Register bit assignments. Table 4-65 CPU1_PLL_CTRL0 Register bit assignments Bits Name Type Function [31] PLLEN PLL global enable. After SoC bootup, the PLL is disabled until this bit is set to 0b1: 0x0: PLL disabled.
  • Page 152 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the CPU1_PLL_CTRL1 Register bit assignments. Table 4-66 CPU1_PLL_CTRL1 Register bit assignments Bits Name Type Function [31] Reserved. [30:28] POSTDIV2 Second post-divide value. Post-divide value=POSTDIV2. Reset value 0b1. [27] Reserved.
  • Page 153 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the CLUS_PLL_CTRL0 Register bit assignments. Table 4-67 CLUS_PLL_CTRL0 Register bit assignments Bits Name Type Function [31] PLLEN PLL global enable. After SoC bootup, the PLL is disabled until this bit is set to 0b1: 0b0: PLL disabled.
  • Page 154 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the CLUS_PLL_CTRL1 Register bit assignments. Table 4-68 CLUS_PLL_CTRL1 Register bit assignments Bits Name Type Function [31] Reserved. [30:28] POSTDIV2 Second post-divide value. Post-divide value=POSTDIV2. Reset value 0b1. [27] Reserved.
  • Page 155 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the SYS_PLL_CTRL0 Register bit assignments. Table 4-69 SYS_PLL_CTRL0 Register bit assignments Bits Name Type Function [31] PLLEN PLL global enable. After SoC bootup, the PLL is disabled until this bit is set to 0b1: 0b0: PLL disabled.
  • Page 156 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the SYS_PLL_CTRL1 Register bit assignments. Table 4-70 SYS_PLL_CTRL1 Register bit assignments Bits Name Type Function [31] Reserved. [30:28] POSTDIV2 Second post-divide value. Post-divide value=POSTDIV2. Reset value 0b1. [27] Reserved.
  • Page 157 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the DMC_PLL_CTRL0 Register bit assignments. Table 4-71 DMC_PLL_CTRL0 Register bit assignments Bits Name Type Function [31] PLLEN PLL global enable. After SoC bootup, the PLL is disabled until this bit is set to 0b1: 0b0: PLL disabled.
  • Page 158 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the DMC_PLL_CTRL1 Register bit assignments. Table 4-72 DMC_PLL_CTRL1 Register bit assignments Bits Name Type Function [31] Reserved. [30:28] POSTDIV2 Second post-divide value. Post-divide value=POSTDIV2. Reset value 0b1. [27] Reserved.
  • Page 159 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the INT_PLL_CTRL0 Register bit assignments. Table 4-73 INT_PLL_CTRL0 Register bit assignments Bits Name Type Function [31] PLLEN PLL global enable. After SoC bootup, the PLL is disabled until this bit is set to 0b1: 0b0: PLL disabled.
  • Page 160 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the INT_PLL_CTRL1 Register bit assignments. Table 4-74 INT_PLL_CTRL1 Register bit assignments Bits Name Type Function [31] Reserved. [30:28] POSTDIV2 Second post-divide value. Post-divide value=POSTDIV2. Reset value 0b1. [27] Reserved.
  • Page 161 4 Programmers model 4.5 Serial Configuration Control registers Table 4-75 SYS_MAN_RESET Register bit assignments (continued) Bits Name Type Function [10] FORCE_PCIE_APB_RST PCIe APB reset, PCIe top reset: 0b0: Not reset. 0b1: Reset. Reset value 0b1. [9:8] Reserved. FORCE_MCP_QSPI_RST MCPQSPICLK manual reset: 0b0: Not reset.
  • Page 162 4 Programmers model 4.5 Serial Configuration Control registers Table 4-75 SYS_MAN_RESET Register bit assignments (continued) Bits Name Type Function FORCE_IOFPGA_TMIF_RST TMIF2XCLK manual reset: 0b0: Not reset. 0b1: Reset. Reset value 0b0. FORCE_SYS_APB_RST SYSAPBCLK manual reset: 0b0: Not reset. 0b1: Reset. Reset value 0b0.
  • Page 163 4 Programmers model 4.5 Serial Configuration Control registers 4.5.46 BOOT_CTRL_STA Register The BOOT_CTRL_STA Register characteristics are: Purpose Stores bootup statuses. Usage constraints Bits[31:24 are read/write. Bits[6:0] are read-only. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120.
  • Page 164 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the SCP_BOOT_ADR Register bit assignments. Table 4-78 SCP_BOOT_ADR Register bit assignments Bits Name Type Function...
  • Page 165 4 Programmers model 4.5 Serial Configuration Control registers Table 4-80 PLATFORM_CTRL Register bit assignments Bits Name Type Function [31:9] Reserved. MULTI_CHIP_MODE RO from APB interface. Multi-chip tie-off value: 0b0: Single chip. RW from serial interface. 0b1: Multi-chip. Reset value 0b0. [7:6] Reserved.
  • Page 166 4 Programmers model 4.5 Serial Configuration Control registers Table 4-82 SCP_BOOT_ADR Register bit assignments Bits Name Type Function [31:0] RO from APB interface. CoreSight target ID of SCP. Reset value 0x07B10477. RW from serial interface. 4.5.52 TARGETIDMCP Register The TARGETIDMCP Register characteristics are: Purpose Stores the MCP bootup address.
  • Page 167 4 Programmers model 4.5 Serial Configuration Control registers 4.5.54 BOOT_GPR1 Register The BOOT_GPR1 Register characteristics are: Purpose Bootup general-purpose register. This register enables an external controller to pass bootup configuration information into the N1 SoC before the release of the powerup reset. The register does not export any control from the SCC.
  • Page 168 4 Programmers model 4.5 Serial Configuration Control registers Purpose Bootup general-purpose register. This register enables an external controller to pass bootup configuration information into the N1 SoC before the release of the powerup reset. The register does not export any control from the SCC. Usage constraints This register is read-only from the APB interface and read/write from the serial interface.
  • Page 169 4 Programmers model 4.5 Serial Configuration Control registers Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the BOOT_GPR5 Register bit assignments. Table 4-89 BOOT_GPR5 Register bit assignments Bits Name...
  • Page 170 4 Programmers model 4.5 Serial Configuration Control registers Table 4-91 BOOT_GPR7 Register bit assignments Bits Name Type Function [31:0] RO from APB interface. Bootup general-purpose register 7. Reset value 0x00000000. RW from serial interface. 4.5.61 INSTANCE_ID Register The INSTANCE_ID Register characteristics are: Purpose SWJ-DP instance ID register.
  • Page 171 4 Programmers model 4.5 Serial Configuration Control registers Table 4-93 PCIE_BOOT_CTRL Register bit assignments Bits Name Type Function [31:2] Reserved. CCIX_STICKY_RST_EN Enable reset of all sticky bits in the CCIX controller during CCIX controller reset: 0b0: Not enable reset of sticky bits. 0b1: Enable reset of sticky bits.
  • Page 172 4 Programmers model 4.5 Serial Configuration Control registers Table 4-94 DBG_AUTHN_CTRL Register bit assignments (continued) Bits Name Type Function DBG_SPIDEN Secure invasive debug enable: 0b0: Disable. 0b1: Enable. Reset value 0b1. DBG_DEVICEEN Global external debug enable: 0b0: Disable. 0b1: Enable. Reset value 0b1.
  • Page 173 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the CTI1_CTRL Register bit assignments. Table 4-96 CTI1_CTRL Register bit assignments Bits Name Type Function...
  • Page 174 4 Programmers model 4.5 Serial Configuration Control registers Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the MCP_WDOGCTI_CTRL Register bit assignments. Table 4-98 MCP_WDOGCTI_CTRL Register bit assignments Bits Name Type Function...
  • Page 175 4 Programmers model 4.5 Serial Configuration Control registers Table 4-100 DBGEXPCTI_CTRL Register bit assignments Bits Name Type Function [31:24] TODBGENSEL2 CTI2 TODBGENSEL input. Reset value 0x00. [23:16] TINIDENSEL2 CTI2 TINIDENSEL input. Reset value 0x00. [15:8] TODBGENSEL1 CTI1 TODBGENSEL input. Reset value 0x00. [7:0] TINIDENSEL1 CTI1 TINIDENSEL input.
  • Page 176 4 Programmers model 4.5 Serial Configuration Control registers Usage constraints There are no usage constraints. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the CCIX_PM_CTRL Register bit assignments. Table 4-102 CCIX_PM_CTRL Register bit assignments Bits Name...
  • Page 177 4 Programmers model 4.5 Serial Configuration Control registers Table 4-103 SCDBG_CTRL Register bit assignments (continued) Bits Name Type Function SOC_ELAOUTUT0 Or-ed SoC ELA EALOUTPUT[0]. Reset value 0b0. MODE_STATUS Sticky signal which indicates that the N1 SoC has entered Scan-based debug mode: 0b0: Not Scan-based debug mode.
  • Page 178 4 Programmers model 4.5 Serial Configuration Control registers Table 4-103 SCDBG_CTRL Register bit assignments (continued) Bits Name Type Function TRIG_SS_RESETREQ Include Manageability Control Processor (MC) and System Control Processor (SCP) subsystem reset request. Reset value 0b0. MASTER_EN Scan-based debug master enable. This bit must be 0b1 to enter SCD mode.
  • Page 179 4 Programmers model 4.5 Serial Configuration Control registers Table 4-104 EXP_IF_CTRL Register bit assignments (continued) Bits Name Type Function ROUNDROBIN_TBU_CCIX Defines the Micro TLB entry replacement policy for the PCIe AXI expansion interface. 0b0: The Micro TLB uses a pseudo Least Recently Used (LRU) replacement policy.
  • Page 180 4 Programmers model 4.5 Serial Configuration Control registers Table 4-105 RO_CTRL Register bit assignments Bits Name Type Function [31:1] Reserved. RO_EN Enables and disables ring oscillator: 0b0: Disable ring oscillator. 0b1: Enable ring oscillator. Reset value 0b1. 4.5.75 CMN_CCIX_CTRL Register The CMN_CCIX_CTRL Register characteristics are: Purpose CCIX control register.
  • Page 181 4 Programmers model 4.5 Serial Configuration Control registers Table 4-106 CMN_CCIX_CTRL Register bit assignments (continued) Bits Name Type Function [24] CXLA_CXSCLK _QREQ QREQn of CXLA CXSCLK control Q channel at CXS interface side. This bit maintains its reset value while the CCIX subsystem is operating.
  • Page 182 4 Programmers model 4.5 Serial Configuration Control registers Usage constraints There are no usage constraints. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the STM_CTRL Register bit assignments. Table 4-107 STM_CTRL Register bit assignments Bits Name...
  • Page 183 4 Programmers model 4.5 Serial Configuration Control registers Table 4-108 AXI_OVRD_PCIE Register bit assignments (continued) Bits Name Type Function [19:16] AWCACHE_TPH Override value of AWCACHE when TPH values are present. Reset value 0b0000. [15:14] - Reserved. [13:12] ARDOMAIN Override value of ARCACHE. Reset value 0b11.
  • Page 184 4 Programmers model 4.5 Serial Configuration Control registers Table 4-109 AXI_OVRD_CCIX Register bit assignments (continued) Bits Name Type Function [15:14] - Reserved. [13:12] ARDOMAIN Override value of ARCACHE. Reset value 0b11. [11:8] ARCACHE Override value of AWCACHE. Reset value 0b0000. [7:6] Reserved.
  • Page 185 4 Programmers model 4.5 Serial Configuration Control registers Purpose Controls the drive strengths and slew rates of trace data output pads. Usage constraints There are no usage constraints. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120.
  • Page 186 4 Programmers model 4.5 Serial Configuration Control registers Table 4-111 TRACE_PAD_CTRL0 Register bit assignments (continued) Bits Name Type Function [17:16] IO_DS_TRACE_DATA 2 Drive strength control of trace port output pads TRACE_DATA[23:16]: 0b00: 2mA. 0b01: 8mA. 0b10: 4mA. 0b11: 12mA. Reset value 0b01. [15:13] - Reserved.
  • Page 187 4 Programmers model 4.5 Serial Configuration Control registers 4.5.81 TRACE_PAD_CTRL1 Register The TRACE_PAD_CTRL1 Register characteristics are: Purpose Controls the drive strengths and slew rates of the trace clock output pads. Usage constraints There are no usage constraints. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120.
  • Page 188 4 Programmers model 4.5 Serial Configuration Control registers Table 4-112 TRACE_PAD_CTRL1 Register bit assignments (continued) Bits Name Type Function [3:2] Reserved. [1:0] IO_DS_TRACE_CLK_A Drive strength control of trace port output pad TRACE_CLK_A: 0b00: 2mA. 0b01: 8mA. 0b10: 4mA. 0b11: 12mA. Reset value 0b01.
  • Page 189 4 Programmers model 4.5 Serial Configuration Control registers Table 4-113 IOFPGA_TMIF_PAD_CTRL Register bit assignments (continued) Bits Name Type Function [15:13] - Reserved. [12] IO_SR_IOFPGA_AXI_TMIF_CTL Slew rate control of IOFPGA AXI TMIF output pads IOFPGA_TMIF_VALID_O and IOFPGA_TMIF_CTL_O: 0b0: Fast. 0b1: Slow. Reset value 0b1.
  • Page 190 4 Programmers model 4.5 Serial Configuration Control registers Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the IOFPGA_TSIF_PAD_CTRL Register bit assignments. Table 4-114 IOFPGA_TSIF_PAD_CTRL Register bit assignments Bits Name...
  • Page 191 4 Programmers model 4.5 Serial Configuration Control registers Table 4-114 IOFPGA_TSIF_PAD_CTRL Register bit assignments (continued) Bits Name Type Function IO_SR_IOFPGA_AXI_TSIF_DATA Slew rate control of IOFPGA AXI TSIF output pads IOFPGA_TSIF_DATA_O[7:0]: 0b0: Fast. 0b1: Slow. Reset value 0b1. [3:2] Reserved. [1:0] IO_DS_IOFPGA_AXI_TSIF_DATA Drive strength control of IOFPGA AXI TSIF output pads IOFPGA_TSIF_DATA_O[7:0]:...
  • Page 192 4 Programmers model 4.5 Serial Configuration Control registers Usage constraints This register is read-only. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.5.1 Serial Configuration Control registers summary on page 4-120. The following table shows the PID4 Register bit assignments. Table 4-116 PID4 Register bit assignments Bits Name...
  • Page 193 4 Programmers model 4.5 Serial Configuration Control registers The following table shows the PID1 Register bit assignments. Table 4-118 PID1 Register bit assignments Bits Name Type Function [31:8] Reserved. [7:0] PID1 Peripheral ID 1 identification. Reset value 0xB0. 4.5.88 PID2 Register The PID2 Register characteristics are: Purpose Stores peripheral identification information.
  • Page 194 4 Programmers model 4.5 Serial Configuration Control registers Table 4-120 PID3 Register bit assignments Bits Name Type Function [31:8] Reserved. [7:0] PID3 Peripheral ID 3 identification. Reset value 0x00. 4.5.90 CID0 Register The CID0 Register characteristics are: Purpose Stores component identification information. Usage constraints This register is read-only.
  • Page 195 4 Programmers model 4.5 Serial Configuration Control registers Table 4-122 CID1 Register bit assignments Bits Name Type Function [31:8] Reserved. [7:0] CID1 Component ID 1 identification. Reset value 0xF0. 4.5.92 CID2 Register The CID2 Register characteristics are: Purpose Stores component identification information. Usage constraints This register is read-only.
  • Page 196 4 Programmers model 4.5 Serial Configuration Control registers Table 4-124 CID3 Register bit assignments Bits Name Type Function [31:8] Reserved. [7:0] CID3 Component ID 3 identification. Reset value 0xB1. 101489_0000_02_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 4-196 reserved.

  • Page 197: Apb System Registers

    4 Programmers model 4.6 APB system registers APB system registers The IOFPGA contains the APB system registers. This section contains the following subsections: • 4.6.1 APB system register summary on page 4-197. • 4.6.2 SYS_ID Register on page 4-198. • 4.6.3 SYS_SW Register on page 4-198.
  • Page 198 4 Programmers model 4.6 APB system registers Table 4-125 N1 SDP APB system register summary (continued) Offset Name Type Reset Width Description 0x0084 SYS_PROC_ID0 0x0X000000 32 4.6.11 SYS_PROC_ID0 Register on page 4-203. 0x0120 SYS_FAN_SPEED 0x00000000 32 4.6.12 SYS_FAN_SPEED Register on page 4-203.
  • Page 199 4 Programmers model 4.6 APB system registers Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.6.1 APB system register summary on page 4-197. The following table shows the bit assignments. Table 4-127 SYS_SW Register bit assignments Bits Name Type...
  • Page 200 4 Programmers model 4.6 APB system registers Purpose A 32‑bit counter that updates at 100Hz. The input clock derives from the 24MHz clock generator on the N1 board. Usage constraints The SYS_100HZ Register is read‑only. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.6.1 APB system register summary on page 4-197.
  • Page 201 4 Programmers model 4.6 APB system registers SYS_NVFLAGS Register The SYS_NVFLAGS Register is one of the two flag registers. It contains the current states of the flags. The SYS_NVFLAGS Register is non‑volatile, that is, a reset signal from the reset push button does not reset the SYS_FLAGS Register.
  • Page 202 4 Programmers model 4.6 APB system registers Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.6.1 APB system register summary on page 4-197. The following table shows the bit assignments. Table 4-131 SYS_24MHZ Register bit assignments Bits Name Type...
  • Page 203 4 Programmers model 4.6 APB system registers The following table shows the bit assignments. Table 4-133 SYS_PCI_GBE Register bit assignments Bits Name Type Function [63:48] - Reserved. [47:32] SYS_PCIE_GBE_H Most significant 16 bits of the PCI Express Ethernet MAC address. [31:0] SYS_PCIE_GBE_L Least significant 32 bits of the PCI Express...
  • Page 204 4 Programmers model 4.6 APB system registers Table 4-135 SYS_FAN_SPEED Register bit assignments Bits Name Type Function [31] UPDATE_FAN_SPEED Set this bit to 0b1 when updating the fan speed control bits [4:0]. The system clears this bit to 0b0 after updating the fan speed.
  • Page 205 4 Programmers model 4.6 APB system registers Table 4-136 SP810_CTRL Register bit assignments (continued) Bits Name Type Function [20] Reserved. [19] TimerEn2Sel Selects the source clock for SP804 2 timer clock TIM_CLK[2]: TIM_CLK[2] = 32kHz. TIM_CLK[2] = 1MHz. Note The default is 0b0. [18] Reserved.

  • Page 206: Apb Energy Meter Registers

    4 Programmers model 4.7 APB energy meter registers APB energy meter registers The IOFPGA contains the APB energy meter registers. This section contains the following subsections: • 4.7.1 APB energy meter registers summary on page 4-206. • 4.7.2 SYS_I_SYS Register on page 4-208.
  • Page 207 4 Programmers model 4.7 APB energy meter registers Note The current, power, and energy meter registers are provisional and subject to characterization on the RevB boards. The following table shows the registers in address offset order from the base memory address. Table 4-137 N1 SDP APB system register summary Offset Name...
  • Page 208 4 Programmers model 4.7 APB energy meter registers Table 4-137 N1 SDP APB system register summary (continued) Offset Name Type Reset Width Description 0x0130 SYS_POW_ DDR0 0x0000_0000 32 4.7.22 SYS_POW_DDR0 Register on page 4-221. 0x0134 SYS_POW_ DDR1 0x0000_0000 32 4.7.23 SYS_POW_DDR1 Register on page 4-222.
  • Page 209 4 Programmers model 4.7 APB energy meter registers Purpose Contains a 12‑bit representation of the instantaneous current consumption of N1 cluster 0. Usage constraints This register is read‑only. You must use one of the cluster 1 cores to read this register. Configurations Available in all N1 board configurations.
  • Page 210 4 Programmers model 4.7 APB energy meter registers Table 4-140 SYS_I_PCIE Register bit assignments Bits Name Type Function [31:12] - Reserved. [11:0] SYS_I_PCIE 12‑bit representation of the instantaneous current consumption of the PCIe cluster: • Full scale measurement, 4096, represents 10A. Full scale is 0xFFF.
  • Page 211 4 Programmers model 4.7 APB energy meter registers Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.7.1 APB energy meter registers summary on page 4-206. The following table shows the bit assignments. Table 4-142 SYS_V_SYS Register bit assignments Bits Name Type...
  • Page 212 4 Programmers model 4.7 APB energy meter registers Purpose Contains a 12‑bit representation of the instantaneous supply voltage of the PCIe cluster. Usage constraints This register is read‑only. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.7.1 APB energy meter registers summary on page 4-206.
  • Page 213 4 Programmers model 4.7 APB energy meter registers 4.7.10 SYS_POW_SYS Register The SYS_POW_SYS Register characteristics are: Purpose Contains a 24‑bit representation of the instantaneous power consumption of the parts of the N1 SoC, outside the clusters, that operate from the VSYS power supply. Usage constraints This register is read-only.
  • Page 214 4 Programmers model 4.7 APB energy meter registers Table 4-147 SYS_POW_CL0 Register bit assignments Bits Name Type Function [31:24] - Reserved. [23:0] SYS_POW_CL0 24‑bit representation of the instantaneous power consumption of N1 SoC cluster 0: • The value of these bits represents [SYS_I_CL0(I) × SYS_V_CL0(V)]/617402 watts.
  • Page 215 4 Programmers model 4.7 APB energy meter registers Usage constraints This register is read‑only. You must use one of the cluster 0 cores to read this register. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.7.1 APB energy meter registers summary on page 4-206.
  • Page 216 4 Programmers model 4.7 APB energy meter registers Table 4-150 SYS_ENM_SYS Register bit assignments Bits Name Type Function [63:32] SYS_ENM_H_SYS Most significant 32 bits of a 64‑bit representation of the accumulated energy energy consumption of the fabric of the N1 SoC outside the clusters: The memory address offset of these bits is 0x0104.
  • Page 217 4 Programmers model 4.7 APB energy meter registers Table 4-151 SYS_ENM_CL0 Register bit assignments Bits Name Type Function [63:32] SYS_ENM_H_CL0 Most significant 32 bits of a 64‑bit representation of the accumulated energy consumption of the N1 SoC cluster 0: The memory address offset of these bits is 0x010C. •...
  • Page 218 4 Programmers model 4.7 APB energy meter registers Table 4-152 SYS_ENM_PCIE Register bit assignments Bits Name Type Function [63:32] SYS_ENM_H_PCIE Most significant 32 bits of a 64‑bit representation of the accumulated energy consumption of the N1 SoC cluster 0: The memory address offset of these bits is 0x0114. •...
  • Page 219 4 Programmers model 4.7 APB energy meter registers Table 4-153 SYS_ENM_CL1 Register bit assignments Bits Name Type Function [63:32] SYS_ENM_H_CL1 Most significant 32 bits of a 64‑bit representation of the accumulated energy consumption of N1 SoC cluster 1: The memory address offset of these bits is 0x011C. •...
  • Page 220 4 Programmers model 4.7 APB energy meter registers 4.7.19 SYS_I_DDR1 Register SYS_I_DDR1 Register characteristics are: Purpose Contains a 12‑bit representation of the instantaneous current consumption of DDR 1. Usage constraints This register is read‑only. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.7.1 APB energy meter registers summary on page 4-206.
  • Page 221 4 Programmers model 4.7 APB energy meter registers Table 4-156 SYS_V_DDR0 Register bit assignments Bits Name Type Function [31:12] - Reserved. [11:0] SYS_V_DDR0 12‑bit representation of the instantaneous supply voltage of DDR • Full scale measurement, 4096, represents 2V5. Full scale is 0xFFF.
  • Page 222 4 Programmers model 4.7 APB energy meter registers Memory offset and full register reset value 4.7.1 APB energy meter registers summary on page 4-206. Note The value measured by this register is provisional and subject to characterization on the RevB boards. The following table shows the bit assignments.
  • Page 223 4 Programmers model 4.7 APB energy meter registers Table 4-159 SYS_POW_DDR1 Register bit assignments Bits Name Type Function [31:24] - Reserved. [23:0] SYS_POW_DDR1 24‑bit representation of the instantaneous power consumption of DDR 1: • The value of these bits represents [SYS_I_DDR1(I) × SYS_V_DDR1(V)]/617402 watts.
  • Page 224 4 Programmers model 4.7 APB energy meter registers 4.7.25 SYS_ENM_DDR1 Register The SYS_ENM_DDR1 Register characteristics are: Purpose Contains a 64‑bit representation of the accumulated energy consumption of DDR 1. Usage constraints This register is read‑only. Configurations Available in all N1 board configurations. Memory offset and full register reset value 4.7.1 APB energy meter registers summary on page 4-206.

  • Page 225: Uart Memory Addresses And Control Registers

    4 Programmers model 4.8 UART memory addresses and control registers UART memory addresses and control registers The N1 SoC and IOFPGA contain registers that control the UARTs in the N1 System Development Platform. The following table shows the N1 SDP UART memory addresses. Table 4-162 UART memory locations UART Memory address Comment...
  • Page 226 4 Programmers model 4.8 UART memory addresses and control registers Table 4-163 UART control registers summary Offset Name Type Reset value Width Function 0x0000 UART0DR Data Register. 0x0004 UART0RSR/UART0ECR RW 0x0000_0000 32 Receive Status Register/Error Clear Register. 0x0018 UART0FR 0x0000_0012 32 Flag Register.
  • Page 227 4 Programmers model 4.8 UART memory addresses and control registers Table 4-163 UART control registers summary (continued) Offset Name Type Reset value Width Function 0x102C UART1LCR_H 0x0000_0000 32 Line Control Register. 0x1030 UART1CR 0x0000_0300 32 Control Register. 0x1034 UART1IFLS 0x0000_0012 32 Interrupt FIFO Level Select Register.

  • Page 228: Appendix A Signal Descriptions

    Appendix A Signal descriptions This appendix describes the signals that are present at the N1 SDP ports. It contains the following sections: • A.1 UART headers on page Appx-A-229. • A.2 UART DB9 connectors on page Appx-A-231. • A.3 N1-SoC JTAG connector on page Appx-A-232.

  • Page 229: Uart Headers

    A Signal descriptions A.1 UART headers UART headers There are four 5×2 way, no pin 10, UART headers on the N1 board. The settings in the define the connectivity of the UART system. See 3.3.2 config.txt config.txt board configuration file on page 3-65 2.10 UARTs on page 2-51 for information on configuring the UART system.
  • Page 230 A Signal descriptions A.1 UART headers Table A-4 UART3 header signal list Pin Signal Pin Signal No connection 2 No connection No connection No connection No connection 8 No connection Related information 1.3 The N1 SDP at a glance on page 1-14 101489_0000_02_en Copyright ©...

  • Page 231: Uart Db9 Connectors

    A Signal descriptions A.2 UART DB9 connectors UART DB9 connectors There are two DB9 connectors on the back panel that connect to logical UART channels UART0 and UART1. The settings in the define the connectivity of the UART system. See 3.3.2 config.txt config.txt...

  • Page 232: N1-Soc Jtag Connector

    A Signal descriptions A.3 N1-SoC JTAG connector N1-SoC JTAG connector There is one 20-pin JTAG box header connector on the back panel. The I/O voltage of the JTAG connector is 1V8. The following table shows the pin mapping of the P-JTAG connector. Table A-7 N1-SoC P-JTAG connector signal list Pin Signal Pin Signal...

  • Page 233: Trace Connector

    A Signal descriptions A.4 Trace connector Trace connector There is a Samtec QSH 60-pin plug connector on the back panel which supports 32‑bit trace, JTAG debug, and Serial Wire Debug (SWD). The I/O voltage for the connector is 1V8. The following table shows the pin mapping of the trace connector. Table A-8 Trace connector pin mapping Pin Signal Pin Signal...
  • Page 234 A Signal descriptions A.4 Trace connector Table A-8 Trace connector pin mapping (continued) Pin Signal Pin Signal No connection No connection Note Pin 17, TRACE_CTL, is not used and has a pulldown resistor to GND. Related information 1.3 The N1 SDP at a glance on page 1-14 101489_0000_02_en Copyright ©...

  • Page 235: Front Panel I/O Header

    A Signal descriptions A.5 Front panel I/O header Front panel I/O header There is a 20-pin header, 10×2, on the N1 board near the front panel. The header provides connectivity for LEDs and switches between the front panel and the board. Some signals are not brought out to the front panel but are available on the header but are available for use at the connector.

  • Page 236: Pci Express And Ccix Slots

    A Signal descriptions A.6 PCI Express and CCIX slots PCI Express and CCIX slots There are two 16-lane PCIe slots, one 4-lane PCIe slot, and one dual-use 16-lane PCIe-Cache-Coherent Interconnect for Accelerators (CCIX) slot on the N1 board. The following table shows the PCIe slots and the number of lanes implemented. Table A-10 PCI Express expansion slots Slot number PCIe lane connector size Used lanes Unused lanes Comment Slot 1...

  • Page 237: C2C Connector

    A Signal descriptions A.7 C2C connector C2C connector The N1 System Development Platform provides a Chip-to-Chip (C2C) connector on the back panel. The C2C enables N1 SoC to N1 SoC CCIX connectivity. Arm supplies adapter boards and connector cables for the master and slave CCIX slots. See 2.9 Chip to Chip communications on page 2-48.

  • Page 238: Power Connectors

    A Signal descriptions A.8 Power connectors Power connectors There are an ATX 24-pin power connector and an ATX/EPS 8-pin secondary connector on the N1 board. The ATX 24-pin power connector has the standard ATXv2.2 pin connections. The following table shows the ATX/EPS connector pin mapping. Table A-11 ATX/EPS pin mapping Pin Connection Related information...

  • Page 239: Appendix B Revisions

    Appendix B Revisions This appendix describes the technical changes between released issues of this book. It contains the following section: • B.1 Revisions on page Appx-B-240. 101489_0000_02_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-B-239 reserved. Non-Confidential - Beta...
  • Page 240 B Revisions B.1 Revisions Revisions The following table lists the technical changes between released issues of this book. Table B-1 Issue 101489_0000_00 Change Location Affects No changes, first release. - Table B-2 Differences between issue 101489_0000_00 and issue 101489_0000_01 Change Location Affects Added Cache-Coherent Interconnect for...
  • Page 241 B Revisions B.1 Revisions Table B-2 Differences between issue 101489_0000_00 and issue 101489_0000_01 (continued) Change Location Affects Added AP, SCP, and MCP interrupt information. All board 4.3.1 Application Processor interrupt map versions on page 4-95 4.3.2 System Control Processor interrupt map on page 4-98 4.3.3 Manageability Control Processor interrupt map on page 4-102...

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