AWINIC AW86225 Manual

Low power fo detect and tracking lra haptic driver

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Low Power F0 Detect and Tracking LRA Haptic Driver
Features
1MHz I2C Bus
Integrated 3K Memory
12k/24k/48k input wave sampling rate
F0 detect and tracking
Advance autobrake engine integrated
Playback mode:
Real time playback
Memory playback
1 Trigger playback
Cont playback
Resistance-Based LRA Diagnostics
Drive signal monitor for LRA protect
Drive Compensation Over Battery Discharge
Fast Start Up Time <0.4ms
Reused interrupt output pin
Support automatically switch to standby mode
Standby current:3uA
Shutdown current:<1uA
Supply voltage range 3 to 5.5V
Short-Circuit Protection, Over-Temperature
Protection, Under-Voltage Protection
WLCSP
1.127mmX1.127mmX0.557mm-9B
Package
Applications
Mobile phones
Tablets
Wearable Devices
All trademarks are the property of their respective owners.
www.awinic.com
General Description
AW86225 is a low cost H-bridge, single chip LRA
haptic driver, with F0 detecting and tracking based
on BEMF, supporting real time playback, memory
playback, Cont playback and hardware pin trigged
playback with fast start up time. All these make the
AW86225 an ideal candidate for haptic driver.
AW86225 integrates a 3KByte SRAM for user-
defined waveforms to achieve a variety of
vibration experiences, supporting 3 sampling
rate(12k/24k/48k) of waveforms loaded in SRAM,
supporting output waveform sampling rate up-
sampling to 48k.
AW86225 integrates an autobrake engine to
suppress the aftershocks to zero for different drive
waveforms (short or long) on different LRA
motors.
AW86225 supports LRA fault diagnostic based on
resistance measurement and protections of short-
circuit, over-temperature and under-voltage.
AW86225 features configurable automatically
switch to standby mode after haptic waveform
playback finished. This can less quiescent power
consumption. The RSTN pin provides further
power saving by fully shut down the whole device.
Reused interrupt output pin can detect real time
FIFO status and the error status of the chip.
AW86225
communicated via an I2C-bus interface.
AW86225
1.127mmX1.127mmX0.557mm-9B package.
1
Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
October 2021 V1.9
features
general
settings
is
available
in
AW86225
are
a
WLCSP

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Summary of Contents for AWINIC AW86225

  • Page 1 Low Power F0 Detect and Tracking LRA Haptic Driver Features General Description  1MHz I2C Bus AW86225 is a low cost H-bridge, single chip LRA haptic driver, with F0 detecting and tracking based  Integrated 3K Memory on BEMF, supporting real time playback, memory ...
  • Page 2: Pin Definition

    Output of LDO Active low hardware reset RSTN High: standby/active mode Low: power-down mode Power Chip power supply Positive haptic driver differential output Ground Supply ground Negative haptic driver differential output www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 3: Functional Block Diagram

    Typical Application Circuits 0.1uF 0.1uF 10uF VREG 4.7kΩ RSTN GPIO TRIG/INTN GPIO 0.1nF AW86225 4.7kΩ 4.7kΩ 0.1nF Figure 3 Typical Application Circuit of AW86225 All trademarks are the property of their respective owners. www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 4: Ordering Information

    2: For the sake of driving capability, the power lines (especially the one to VDD) and output lines should be short and wide as possible. Ordering Information Moisture Environment Part Delivery Temperature Package Marking Sensitivity Information Number Form Level WLCSP 4500 units/ AW86225CSR -40°C~85°C MSL1 ROHS+HF 1.127mmX1.127mmX0.557mm- Tape and Reel www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 5: Absolute Maximum Ratings

    The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. NOTE 2 Test method: ANSI/ESDA/JEDEC JS-001-2017. : NOTE 3 Charge Device Model test method: ANSI/ESDA/JEDEC JS-002-2018. www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 6: Electrical Characteristics

    VDD=4.2V Load impedance Ω threshold for over current protection VDD=4.2V, PD_HWM=0 PWM output frequency VDD=4.2V, PD_HWM=1 LRA Consistency F0-2 F0+2 CALI_ACC_LRA Calibration accuracy RL=8Ω+100μH Output voltage VDD=4.2V peak Output voltage RL=16Ω+100μH www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 7: I 2 C Interface Timing

    HI GH SU:DAT HD:DAT (10) (11) Figure 4 SCL and SDA timing relationships in the data transmission process HD:STA SU:STO SU:STA Figure 5 The timing relationship between START and STOP state www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 8: Measurement Setup

    October 2021 V1.9 Measurement Setup AW86225 features switching digital output, as shown in Figure 6. Need to connect a low pass filter to HDP/HDN output respectively to filter out switch modulation frequency, then measure the differential output of filter to obtain analog output signal.
  • Page 9: Typical Characteristics

    AW86225 October 2021 V1.9 Typical Characteristics Supply Vlotage(V) Figure 7 Standby Current Vs Supply Voltage Figure 8 LRA with Automatic Braking Figure 9 Trig Application Figure 10 Automatic Resonance Tracking www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 10: Detailed Functional Description

    C interface isn’t accessible in this mode, and all of the internal configurable registers and Memory are cleared. The device will jump out of the power-down mode automatically when the supply voltages are OK and RSTN www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 11 Figure 12 Power On Sequence Playback Sequence Make sure the device is not in POWER-DOWN MODE before sending a playback request, then the playback sequence is illustrated in the following figure: www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 12 C interface will reset the device internal circuits except SRAM, including configuration registers. Battery Voltage Detect Software can send command to detect the battery voltage. Detect steps:  Set EN_RAMINIT to 1 in register 0x43; www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 13: Use Steps

    678 × (���� × 4 + ����_����) ���� = (��) 1024 × D2S_GAIN The values of the D2S_GAIN that can be configured for different sizes of RL are listed below. The higher the www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 14 The waveform header defines the data boundaries for each waveform ID in the data field, and the waveform data contains a signed data format (2's complement) to specify the magnitude of the drive. www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 15  Set base address (register 0x2D, 0x2E);  Write waveform library data into register 0x42 continually until all the waveform library data written; Set register EN_RAMINIT=0, to disable SRAM initial;  www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 16 Set playback loop registers (0x12~ 0x16) as desired;  Set GO bit to 1 in register 0x09 to trigger waveform playback;  Device will be switched to STANDBY mode after haptic waveform playback finished. www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 17 The device has a configuration, multi-mode pin TRIG/INTN. It can serve as a dedicated hardware pin for quickly trigger haptic data playback through configuration register INTN_PIN. Quickly trigger can be configured posedge/negedge/both-edge/level trigger. www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 18 If the resonant frequency shifts for any reason, the function tracks the frequency from cycle to cycle. When TRACK_EN is set to 0, the width of waveform of cont mode is determined by DRV_WIDTH in register 0x1A. www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 19 Auto-brake engine will not work when BRK_TIME in register 0x21 is set to 0;  Device will be switched to STANDBY mode after haptic waveform playback finished. DRV_WIDTH PLAY WAVE BRAKE WAVE Motor BRAKE ENGINE D2S_GAIN SENSOR www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 20: Protection Mechanisms

    When SCL is high level, SDA level must be constant. SDA can be changed only when SCL is low level. Data Line Change Stable of Data Data Valid Allowed Figure 21 Data Validation Diagram www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 21 STOP state to end the process after the data transmission is completed. However, if the master device intends to continue data transmission, you can directly send a Repeated START state, without the need to use the STOP state to end transmission. www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 22 Before and after the change, the master device sends START state and slave address twice, and sends the opposite "read/write" flag. In particular, AW86225 as the slave device, the transmission process carried out by following steps listed in Figure 26: Master device asserts a start condition;...
  • Page 23 CHIPID(2-bit) consists of CHIPID_H and CHIPID_L. The features of CHIPID are shown in the following table. Table 4 CHIPID feature CHIPID (0x64) Product 0: AW86223/AW86224/AW86225 CHIPID_H 1: AW86214 0: AW86224/AW86225 CHIPID_L 1: AW86223/AW86214 www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 24: Register Configuration

    0x3C GLBCFG2 START_DLY 0x04 0x3E GLBCFG4 GO_PRIO TRG1_PRIO 0x1B 0x3F GLBRD5 GLB_STATE 0x00 0x40 RAMADDRH RAMADDRH 0x00 0x41 RAMADDRL RAMADDRL 0x00 0x42 RAMDATA RAMDATA 0x00 0x43 SYSCTRL1 VBAT_MODE EN_RAMINIT EN_FIR 0x04 www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 25 1: INTN pin will not be pulled down when FF_AEI=1 Interrupt mask for FF_AFI: FF_AFM 0: INTN pin will be pulled down when FF_AFI=1 1: INTN pin will not be pulled down when FF_AFI=1 www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 26 When set to 1, WAVSEQ2 means wait time, else means wave sequence number WAVSEQ2 Wait time (code*WAITSLOT) or wave sequence number WAVCFG3: (Address 0Ch) Symbol Description Default SEQ3WAIT When set to 1, WAVSEQ3 means wait time, else means wave sequence number www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 27 STOP set to 1 or SEQ5LOOP ≠0xF control the loop number of the sixth sequence b0000~b1110: play code+1 time SEQ6LOOP b1111: playback infinitely until STOP set to 1 or SEQ6LOOP ≠0xF www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 28 F0. DRV_WIDTH 0x6A DRV_WIDTH is recommended to be configured as(24k/F0)-8-TRACK_MARGIN- BRK_GAIN CONTCFG5: (Address 1Ch) Symbol Description Default www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 29 CONTRD15: (Address 26h) Symbol Description Default Low 8 bit of the measure value for the f0 of LRA in the f0 detection mode F_LRA_F0_L F0=(384000/(F_LRA_F0_H*256+F_LRA_F0_L))Hz CONTRD16: (Address 27h) Symbol Description Default www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 30 TRG1 rising edge enable/disable control TRG1_POS 0: disable 1: enable TRG1SEQ_P TRIG1 posedge trigged wave sequence number TRGCFG4: (Address 36h) Symbol Description Default TRG1 falling edge enable/disable control TRG1_NEG 0: disable 1: enable www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 31 The state of glb state b0000: STANDBY b0110: CONT GLB_STATE b0111: RAM b1000: RTP b1001: TRIG b1011: BRAKE RAMADDRH: (Address 40h) Symbol Description Default Reserved Not used RAMADDRH SRAM address high 4 bits www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 32 4 D2S_GAIN b011: 5 b100: 8 b101: 10 b110: 20 b111: 40 PWMCFG1: (Address 4Ch) Symbol Description Default Set enable of output signal protection mode of pwm: PRC_EN 0: disable www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 33 Set the enabled of VBAT mode DIAG_GO Set the enabled of DIAG mode DET_RL: (Address 53h) Symbol Description Default The measured value of resistance of LRA in DIAG mode(high eight bits) RL=((RL*4+RL_LO)*678)/(1024*d2s_gain)Ω DET_VBAT: (Address 55h) www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 34 ANACFG8: (Address 77h) Symbol Description Default HDP and HDN rising time control b00: Trise = 60ns TRTF_CTRL_HDRV b01: Trise = 20ns b10: Trise = 16ns b11: Trise = 4ns Reserved Not used www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 35: Application Information

    0.1nF ceramic capacitor rated voltage of 10V. If you want to get better EMI suppression performance, can use 1nF, rated voltage 10V capacitor, but quiescent current will increase. www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 36 5. The traces from HDP and HDN to the load should be as short and thick as possible, and the current flow capacity of the traces not be less than 1.2A www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 37: Tape And Reel Information

    Sprocket Holes User Direction of Feed Pocket Quadrants All Dimensions are nominal Pin1 Quadrant (mm) (mm) (mm) (mm) (mm) (mm) (mm) (mm) (mm) 179.00 9.00 1.23 1.23 0.69 2.00 4.00 4.00 8.00 www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 38: Package Description

    Top View 0.380 ± 0.015 0.592 0.177 ± 0.020 BALL TYP Side View 9X( 0.240± 0.020) 0.1635 REF SYMM 0.800 0.400 0.1635 0.400 0.800 0.1635 0.1635 SYMM Bottom View Unit: mm www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 39 0.400 SYMM 0.400 SYMM 0.05 MAX 0.05 MAX ALL AROUND ALL AROUND SOLDER MASK SOLDER MASK OPENING OPENING METAL UNDER METAL SOLDER MASK NON-SOLDER MASK DEFINED SOLDER MASK DEFINED UNIT: mm www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 40: Revision History

    Modify Register Configuration and Waveform library initialization steps 2021 August V1.7 Modify Register Detailed Description and Detailed Functional Description 2021 September V1.8 Modify Detailed Functional Description 2021 October V1.9 Modify Register Detailed Description 2021 www.awinic.com Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD...
  • Page 41 Resale of AWINIC components or services with statements different from or beyond the parameters stated by AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for any such statements.

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