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Allegro APEK85110-D1-E User Manual

Half-bridge driver switch board
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APEK85110-D1-E
Half-Bridge Driver Switch Board User Manual
Description
The Allegro APEK85110-D1-E Half-Bridge Driver Switch Board is a demo board containing two AHV85110 GaN FET driv-
ers and two GaN FETs in a half-bridge configuration.
Figure 1: APEK85110 Evaluation Board
The APEK85110 can be used to perform double pulse tests (see Double Pulse Test section) or to interface the half bridge to
an existing LC power section, as shown below.
The isolated AHV85110 driver does not require secondary-side power or bootstrap components. Gate drive power is supplied
to the secondary side from the primary-side supply voltage, V
. The amplitude of the gate drive can be varied by varying
DRV
V
between 7 and 15 V.
DRV
APEK85110D1-E-UM
August 30, 2022
Advance Information
• Subject to Change Without Notice

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Summary of Contents for Allegro APEK85110-D1-E

  • Page 1 APEK85110-D1-E Half-Bridge Driver Switch Board User Manual Description The Allegro APEK85110-D1-E Half-Bridge Driver Switch Board is a demo board containing two AHV85110 GaN FET driv- ers and two GaN FETs in a half-bridge configuration. Figure 1: APEK85110 Evaluation Board The APEK85110 can be used to perform double pulse tests (see Double Pulse Test section) or to interface the half bridge to an existing LC power section, as shown below.
  • Page 2 DANGER DO NOT TOUCH THE BOARD WHEN IT IS ENERGIZED AND ALLOW ALL COMPONENTS TO DISCHARGE COMPLETELY PRIOR HANDLING THE BOARD. HIGH VOLTAGE CAN BE EXPOSED ON THE BOARD WHEN IT IS CONNECTED TO POWER SOURCE. EVEN BRIEF CONTACT DURING OPERATION MAY RESULT IN SEVERE INJURY OR DEATH. Ensure that appropriate safety procedures are followed.
  • Page 3 Quick Start Guide Figure 2: APEK85110 Quick Start 1. Apply V = 12 V 2. Link pins EN_PU and EN (if not using external Enable control) 3. Apply input gate signals, with adequate dead time, to the IN_L and IN_H inputs. 4.
  • Page 4 Enable and Start Sequence The AHV85110 has an open-drain enable pin (EN) to facilitate a system level wired-AND startup. When the enable pin is externally pulled low, the driver is forced into a low-power mode. The driver output is pulled low in this mode. In the event of an internal fault condition, such as UVLO, this pin is actively pulled low internally by the driver.

  • Page 5: Measurement Points

    Measurement Points The APEK85110 evaluation board contains convenient test points for monitoring the high- and low-side gate drives as well as the switch node as shown in Figure 5. When measuring V , use a differential probe with suitable ratings for the applied bus voltage. The APEK85110 evaluation board GS_H uses a bipolar gate drive arrangement as shown in Figure 6.

  • Page 6: Propagation Delay

    Figure 6: Bipolar Gate Drive Schematic Propagation Delay • V = 12 V • Input = 100 kHz • R = 10 Ω, R = 1 Ω • Power train unloaded, i.e., VHV+ = 0 V. Figure 7: Typical Driver Output at 100 kHz Advance Information Allegro MicroSystems 955 Perimeter Road...
  • Page 7 Double Pulse Test Theory The double pulse test is used to evaluate the switching characteristics of a power switch under hard switching but in a safe manner. For a low-side switch, the set up is as shown below: AHV85110 VBUS AHV85110 Figure 8: Double Pulse Test The low-side switch is driven with two pulses as shown below.

  • Page 8: Test Results

    During period 3, the inductor current will again rise. Period 3 should not be so long that the inductor current rises to an excessive level. The falling edge of pulse 1 is used to examine the hard turn-off characteristics of the switch. The rising edge of pulse 3 is used to examine the hard turn-on characteristics of the switch.
  • Page 9 DPT Result 400V – 62A Figure 11: DPT 400 V, 62 A Advance Information Allegro MicroSystems 955 Perimeter Road Subject to Change Without Notice Manchester, NH 03103-3353 U.S.A. August 30, 2022 www.allegromicro.com...
  • Page 10 APEK85110 SCHEMATIC Figure 12: APEK85110 Schematic Advance Information Allegro MicroSystems 955 Perimeter Road Subject to Change Without Notice Manchester, NH 03103-3353 U.S.A. August 30, 2022 www.allegromicro.com...

  • Page 11: Pcb Layout

    PCB Layout Figure 13: APEK85110 Silkscreen and Component Placement Figure 14: APEK85110 Top-Side Copper (L) and Layer 2 Copper (R) Figure 15: APEK85110 Layer 2 Copper(L) and Bottom-Side Copper (R) Advance Information Allegro MicroSystems 955 Perimeter Road Subject to Change Without Notice Manchester, NH 03103-3353 U.S.A.
  • Page 12 APEK85110 Half-Bridge Driver Switch Board Bill Of Materials Table 1: Bill of Materials Item Ref Name Description Value Manufacturer Manufacturer PN C1, C2 CAP CERALINK, 1 µF, 500 V PLZT 1 µF B58031U5105M062 C14, C15, C16, C17 CAP, CER,100 nF,16 V, X7R, S0402 100 nF KEMET C0402C104K4RALTU...
  • Page 13 Revision History Number Date Description – August 30, 2022 Initial release Copyright 2022, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.