ISSI IS31AP2121 Manual

2×25w stereo / 1× 50w mono digital audio amplifier with 20 bands eq functions, drc and 2.1ch mode

Hide thumbs

Table Of Contents

Table of Contents

Quick Links

Download this manual

IS31AP2121

2×25W STEREO / 1× 50W MONO DIGITAL AUDIO AMPLIFIER

WITH 20 BANDS EQ FUNCTIONS, DRC AND 2.1CH MODE

GENERAL DESCRIPTION

The IS31AP2121 is a digital audio amplifier capable of

driving 25W (BTL) each to a pair of 8Ω speakers and

50W (PBTL) to a 4Ω speaker operating at 24V supply

without external heat-sink or fan. The IS31AP2121 is

also capable of driving 4Ω, 12W (SE)×2 + 8Ω, 25W

(BTL)×1 at 24V supply for 2.1CH application.

The IS31AP2121 can provide advanced audio

processing functions, such as volume control, 20 EQ

bands, audio mixing, 3D surround sound and Dynamic

Range Control (DRC). These are fully programmable

via a simple I2C control interface. Robust protection

circuits are provided to protect the IS31AP2121 from

damage due to accidental erroneous operating

condition. The full digital circuit design of IS31AP2121

is more tolerant to noise and PVT (Process, Voltage,

and Temperature) variation than the analog Class-AB

or Class-D audio amplifier counterpart implemented by

analog circuit design. IS31AP2121 is pop free during

instantaneous power on/off or mute/shut down

switching because of its robust built-in anti-pop circuit.

APPLICATIONS



TV audio



Boom-box, CD and DVD receiver, docking system



Powered speaker



Wireless audio

Integrated Silicon Solution, Inc. – www.issi.com

Rev. C, 10/20/2015

FEATURES



16/18/20/24-bits input with I2S, Left-alignment and

Right-alignment data format



PSNR & DR (A-weighting)

Loudspeaker: 104dB (PSNR), 110dB (DR) @24V



Multiple sampling frequencies (F

- 32kHz / 44.1kHz / 48kHz and

- 64kHz / 88.2kHz / 96kHz and

- 128kHz / 176.4kHz / 192kHz



System clock = 64x, 128x, 192x, 256x, 384x,

512x, 576x, 768x, 1024x Fs

- 64x~1024x F

for 32kHz / 44.1kHz / 48kHz

- 64x~512x F

for 64kHz / 88.2kHz / 96kHz

- 64x~256x F

for 128kHz / 176.4kHz / 192kHz



Supply voltage

- 3.3V for digital circuit

- 10V~26V for speaker driver



Supports 2.0CH/2.1CH/Mono configuration



Loudspeaker output power for at 24V

- 10W × 2CH into 8Ω @0.16% THD+N for stereo

- 15W × 2CH into 8Ω @0.19% THD+N for stereo

- 25W × 2CH into 8Ω @0.3% THD+N for stereo



Sound processing including:

- 20 bands parametric speaker EQ

- Volume control (+24dB ~ -103dB, 0.125dB/step),

- Dynamic range control (DRC)

- Dual band dynamic range control

- Power clipping

- 3D surround sound

- Channel mixing

- Noise gate with hysteresis window

- Bass/Treble tone control

Bass management crossover filter

- DC-blocking high-pass filter



Anti-pop design



Short circuit and over-temperature protection



Supports I2C control without MCLK



I2C control interface with selectable device

address



Support BCLK system



Support hardware and software reset



Internal PLL



LV Under-voltage shutdown and HV Under-voltage

detection



Power saving mode

October 2015

)

Table of Contents

Need help?

Do you have a question about the IS31AP2121 and is the answer not in the manual?

Questions and answers

Summary of Contents for ISSI IS31AP2121

Page 1 October 2015 GENERAL DESCRIPTION FEATURES  The IS31AP2121 is a digital audio amplifier capable of 16/18/20/24-bits input with I2S, Left-alignment and driving 25W (BTL) each to a pair of 8Ω speakers and Right-alignment data format 50W (PBTL) to a 4Ω speaker operating at 24V supply ...
Page 2: Typical Application Circuit
15 H 100nF Digital BCLK Audio OUTRA LRCIN Source OUTRB SDATA 470pF BEAD OUTRB Figure 2 Typical Application Circuit (For Mono) Logic Power Down Normal RSTB Reset Normal PBTL Stereo Mono Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 3 Note 4: When concerning about short-circuit protection or performance, it is suggested using the choke with its I larger than 14A. Note 5: 2.1CH configuration, it programs by I2C via register address 0x11, D4 bit SEM. Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 4: Pin Configuration
IS31AP2121 PIN CONFIGURATION Package Pin Configuration (Top View) OUTLA OUTRB VCCLA VCCRA VCCLB VCCRB eLQFP-48 CLK_OUT PBTL DGND DGND DVDD RSTB Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 5: Pin Description
Schmitt trigger TTL input buffer I2C serial clock input. Schmitt trigger TTL input buffer Schmitt trigger TTL input buffer, internal RSTB Reset, low active. pull High with a 330kΩ resistor. 29~33,40 Not connected. Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 6 Right channel output B. 37,38 GNDR Right channel ground. OUTRA Right channel output A. 42,43,45 Not connected. OUTLB Left channel output B. 47,48 GNDL Left channel ground. Thermal Pad Connect to DGND. Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 7: Ordering Information
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 8: Absolute Maximum Ratings
Static drain-to-source on-state resistor, NMOS L/R channel over-current protection =24V, I =500mA (Note 1) Mono channel over-current protection Junction temperature for driver °C shutdown Temperature hysteresis for recovery °C from shutdown Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 9: Ac Electrical Characteristics
+8dB volume, input level is -9dB Signal-to-noise ratio (Note 3) +8dB volume, input level is -68dB Dynamic range (Note 3) PSRR Power supply ripple rejection V = 1V at 1kHz RIPPLE Channel separation 1W @1kHz Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 10 Note 2: Thermal dissipation is limited by package type and PCB design. The external heat-sink or system cooling method should be adopted for maximum power output. Note 3: Measured with A-weighting filter. Note 4: Guaranteed by design. Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 11 IS31AP2121 Figure 4 I2C Timing Figure 5 I2S Figure 6 Left-Alignment Figure 7 Right-Alignment Figure 8 System Clock Timing Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 12 IS31AP2121 Figure 9 Timing Relationship (Using I2S format as an example) Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 13: Typical Performance Characteristics
2.1CH Mode = 5W = 1W = 2.5W = 2.5W = 0.5W 0.05 0.05 = 1W 0.02 0.02 0.01 0.01 Frequency(Hz) Frequency(Hz) Figure 14 THD+N vs. Frequency Figure 15 THD+N vs. Frequency Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 14 = 1kHz Stereo = 12V +0.5 -0.5 0.05 = 24V = 18V -1.5 0.02 0.01 50m 100m 500m 1 Frequency(Hz) Output Power(W) Figure 21 Frequency Response Figure 20 THD+N vs. Output Power Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 15 THD+N = 1% = 8Ω Stereo Output Power(W) Supply Voltage(V) Figure 26 Efficiency vs. Output Power (Power Saving Mode) Figure 27 Output Power vs. Supply Voltage Note: Dashed lines represent thermally limited region. Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 16 Supply Voltage(V) Supply Voltage(V) Figure 28 Output Power vs. Supply Voltage Figure 29 Output Power vs. Supply Voltage Note: Dashed lines represent thermally limited region. Note: Dashed lines represent thermally limited region. Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 17: Functional Block Diagram
IS31AP2121 FUNCTIONAL BLOCK DIAGRAM Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 18 RESET the internal analog circuits. After PDB pin is pulled low, IS31AP2121 needs up to 256 LRCIN clocks to When the RSTB pin is lowered, IS31AP2121 will finish the above works before entering power down clear the stored data and reset the register table to state.
Page 19: Output Configuration
The bit 4 [SEM] of address 0X11 and PBTL pin stage when the wires connected to loudspeakers are defines the configuration mode. IS31AP2121 can be shorted to each other or GND/VDD. For normal 24V configured to stereo, mono via PBTL pin (the bit 4 operations, the current flowing through the power [SEM] of address 0X11 default is low).
Page 20: Power-On Sequence
IS31AP2121 POWER ON SEQUENCE Hereunder is IS31AP2121’s power on sequence. Give a de-mute command via I2C when the whole system is stable. Normal Normal Power-On PDB=L Operation Operation MCLK BCLK LRCIN RSTB I2C Active De-mute Figure 33 Power On Sequence...
Page 21 IS31AP2121 Table 3 Power Off Sequence Symbol Min. t1 (With I2C Control) 35ms t1 (Without I2C Control) 0ms (Note) Note: When t2 is less than 0.1ms, pop noise may occur. Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 22: Register Definitions
Figure 35 Data Transferring REGISTER DEFINITIONS The IS31AP2121’s audio signal processing data flow is shown below. Users can control these functions by programming appropriate settings in the register table. In this section, the register table is summarized first. The definition of each register follows in the next section.
Page 23 BCLK SDATA ASRC PreScal MCLK Clipping Surround Volume DRC1 HPFdc PostScal S/H2 OUTLA OUTLB Clipping Power Surroun Volume DRC1 HPFdc PostScal S/H2 Stage OUTRA OUTRB Clipping Volume DRC2 HPFdc PostScal S/H2 Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 24 PWMR_X LV_UVSEL LREXC Default OUTLA/B exchange PWML_X IS31AP2121 supports multiple serial data input No exchanged formats including I2S, Left-alignment and Right- L/R exchanged alignment. These formats are selected by users via D7~D5 of address 00h. The left/right channels can OUTRA/B exchange...
Page 25 Channel x not muted Only channel x muted Name BCLK_SEL Default 0100 Table 8 03h Master Volume Control Register IS31AP2121 has a built-in PLL and support multiple D7:D0 MCLK/Fs ratios. Detail setting is shown in the following table. Name Default 0001 1000...
Page 26 The -3dB corner frequency of bass is 360Hz, and treble is Default 7kHz. The gain range for both filters is +12db ~ - The IS31AP2121 provides several DSP setting as 12dB with 1dB per step. following. Bass/Treble Gain Setting...
Page 27 The IS31AP2121 can configure each channel to D7:D5 enable or bypass DRC and channel volume and Name CxDRCM CxPCBP select the limiter set. IS31AP2121 support two mode of DRC, RMS and PEAK detection which can be Default selected via D4. Channel 3 DRC Mode C3DRCM...
Page 28 D7. IS31AP2121 support multi-level HV under- 1000 0.0198dB/ms voltage detection via D3~ D0, using this function, 1001 0.0172dB/ms IS31AP2121 will fade out signal to avoid pop sounds 1010 0.0147dB/ms if high voltage supply disappear before low voltage supply. 1011 0.0137dB/ms...
Page 29 Name Default Default 000 0000 Table 25 24h Coefficients Control Register An on-chip RAM in IS31AP2121 stores user-defined D7:D4 EQ and mixing coefficients. The content of this coefficient RAM is indirectly accessed via coefficient Name registers, which consist of one base address register...
Page 30: Ram Access
0X15 Default 4. Read middle 8-bits of coefficient A1in I2C address-0X16 IS31AP2121 supports both master-volume fine tune 5. Read bottom 8-bits of coefficient A1 in I2C and channel-volume control fine tune modes. Both address-0X17 volume control settings range from 0dB ~ -0.375dB and 0.125dB per step.
Page 31 8. Write top 8-bits of coefficient B1 in I2C address- 0X1B MIXER 9. Write middle 8-bits of coefficient B1 in I2C The IS31AP2121 provides mixers to generate the address-0X1C extra audio source from the input left and right 10. Write bottom 8-bits of coefficient B1 in I2C channels.
Page 32 3. Attack threshold is defined by 24-bit representation and is stored in RAM address 0X71 and 0X72. RELEASE THRESHOLD After IS31AP2121 has reached the attack threshold, Figure 36 Mixer Function Block Diagram its output power will be limited to that level. The PRE-SCALE output power level will be gradually adjusted to the programmable release threshold level.
Page 33 0X75. NOISE GATE RELEASE LEVEL After entering the noise gating status, the noise gain will be removed whenever IS31AP2121 receives any Figure 38 Digital Processing of Calculating RMS Signal Power input signal that is more than the noise gate release level.
Page 34 IS31AP2121 Table 31 Sample Calculation for DRC Energy Coefficient DRC Energy Linear Decimal Coefficient (1.23 Format) 8388607 7FFFFF 1/256 -48.2 1/256 32768 8000 1/1024 -60.2 1/1024 8192 2000 (x/20) 8388607×L dec2hex(D) Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 35 0x4B CH2EQ6A1 0x000000 0x1A CH1EQ6A2 0x000000 0x4C CH2EQ6A2 0x000000 Channel 1 Channel 2 0x1B CH1EQ6B1 0x000000 0x4D CH2EQ6B1 0x000000 0x1C CH1EQ6B2 0x000000 0x4E CH2EQ6B2 0x000000 0x1D CH1EQ6A0 0x200000 0x4F CH2EQ6A0 0x200000 Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 36 0x5F CH3EQ2A1 0x000000 0x2E CH3EQ1A2 0x000000 0x60 CH3EQ2A2 0x000000 Channel 3 Channel 3 0x2F CH3EQ1B1 0x000000 0x61 CH3EQ2B1 0x000000 0x30 CH3EQ1B2 0x000000 0x62 CH3EQ2B2 0x000000 0x31 CH3EQ1A0 0x200000 0x63 CH3EQ2A0 0x200000 Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 37 CH3 DRC Release Threshold DRC2_RTH 0x80000 0x75 Noise Gate Attack Level NGAL 0x0001A 0x76 Noise Gate Release Level NGRL 0x000053 0x77 DRC1 Energy Coefficient DRC1_EC 0x8000 0x78 DRC2 Energy Coefficient DRC2_EC 0x2000 Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 38 Time (tp)** within 5°C of the specified Max 30 seconds classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 39 Classification Profile Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 39: Package Information
IS31AP2121 PACKAGE INFORMATION eLQFP-48 Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 40 3. This document (including dimensions, notes & specs) is a recommendation based on typical circuit board manufacturing parameters. Since land pattern design depends on many factors unknown (eg. user’s board manufacturing specs), user must determine suitability for use. Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...
Page 41: Revision History
IS31AP2121 REVISION HISTORY Revision Detail Information Date Initial release 2015.07.07 Update pin out, exchange Pin 36 and Pin 39 2015.09.10 1. Update EC table 2015.10.20 2. Add performance figures Integrated Silicon Solution, Inc. – www.issi.com Rev. C, 10/20/2015...

ISSI IS31AP2121 Manual

Quick Links

Need help?

Questions and answers

Subscribe to Our Youtube Channel

Related Manuals for ISSI IS31AP2121

Summary of Contents for ISSI IS31AP2121

Table of Contents