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BitFlow The Karbon-CL Hardware Reference Manual

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The Karbon-CL
Hardware Reference Manual
BitFlow, Inc.
300 Wildwood Ave
Woburn, MA 01801
USA
Tel: 781-932-2900
Fax: 781-933-9965
Email: support@bitflow.com
Web: www.bitflow.com
Revision F.0

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  • Page 1 The Karbon-CL Hardware Reference Manual BitFlow, Inc. 300 Wildwood Ave Woburn, MA 01801 Tel: 781-932-2900 Fax: 781-933-9965 Email: support@bitflow.com Web: www.bitflow.com Revision F.0...
  • Page 2 BitFlow, Inc. BitFlow, Inc. makes no implicit warranty for the use of its products and assumes no responsibility for any errors that may appear in this document, nor does it make a commit- ment to update the information contained herein.

  • Page 3: Table Of Contents

    Support Services KBN-P-1 Technical Support KBN-P-1 Sales Support KBN-P-1 Conventions KBN-P-2 1 - General Description and Architecture The Karbon-CL family KBN-1-1 Virtual vs. Hardware KBN-1-1 The Virtual Frame Grabber (VFG) KBN-1-1 Karbon Configuration Spaces KBN-1-2 Firmware, Camera Files and Downloads KBN-1-5...
  • Page 4 CON20 Register KBN-4-70 CON21 Register (Bayer Version) KBN-4-73 CON23 Register KBN-4-76 CON24 Register KBN-4-78 CON25 Register KBN-4-82 CON26 Register KBN-4-84 CON27 Register KBN-4-85 CON36 Register KBN-4-86 CON37 Register KBN-4-88 CON38 Register KBN-4-90 5 - Karbon/Neon DMA Registers Introduction KBN-5-1 BitFlow, Inc.
  • Page 5 General Purpose Inputs (GPIN) KBN-7-6 General Purpose Outputs (GPOUT) KBN-7-7 The Open Collector Drivers for GPOUT5 and GPOUT6 KBN-7-7 Camera Link Controls (CCs) KBN-7-11 8 - Specifications Introduction KBN-8-1 Maximum Pixels Per Line KBN-8-2 Maximum Lines Per Frame KBN-8-3 Power Consumption KBN-8-4 BitFlow, Inc.
  • Page 6 Table of Contents 9 - Mechanical Introduction KBN-9-1 The Karbon-CL Connectors KBN-9-3 The CL Connectors KBN-9-3 The I/O Connector KBN-9-4 The Auxiliary Connectors KBN-9-4 The Jumpers and Switches KBN-9-5 Jumpers KBN-9-5 Switches KBN-9-7 The Camera Link Connector Pinouts (CL1 to CL4) KBN-9-8 The I/O Connector Pinout (P11) KBN-9-9 BitFlow, Inc.

  • Page 7: Support Services Kbn

    Second, it is a reference manual describing in detail the functionality of all of the board’s registers. P.1.1 Support Services BitFlow, Inc. provides both sales and technical support for the Karbon family of prod- ucts. P.1.2 Technical Support Our web site is www.bitflow.com.
  • Page 8 Table P-1 Base Abbreviations Base Designator Example Binary 1010b Decimal None 4223 Hexidecimal 12fah Table P-2 shows the numerical abbreviations that are used in this manual. Table P-2 Numeric Abbreviations Abbreviation Value Example 1024 256K 1048576 KBN-P-2 BitFlow, Inc. Version F.0...

  • Page 9: General Description And Architecture

    General Description and Architecture Chapter 1 1.1 The Karbon-CL family The purpose of this chapter is to explain, at a block diagram level, how the Karbon-CL works, and what different versions are available. There are four main models in the Karbon-CL family:...

  • Page 10: Karbon Configuration Spaces Kbn-1-2

    The idea of modifying a frame grabber by making changes to its firmware is not new. BitFlow has been doing this since its very first product. However, what is new about the Karbon family, is the fact the entire frame grabber is written in firmware. The only fixed hardware components are the interfaces to the outside world (e.g.
  • Page 11 General Description and Architecture The Karbon-CL family Channel Connector Link Chip Channel Connector Link Chip Channel Connector Link Chip Channel Connector Link Chip Device Device Device Device KBN-PCE-CL4-D only PCI Express Bus Figure 1-1 KBN-PCE-CL2-D and KBN-PCE-CL4-D Version F.0 BitFlow, Inc.
  • Page 12 The Karbon-CL family The Karbon Channel Connector Link Chips Channel Connector Link Chip Channel Connector Link Chips Channel Connector Link Chip Device Device KBN-PCE-CL4-F only PCI Express Bus Figure 1-2 KBN-PCE-CL2-F and KBN-PCE-CL4-F KBN-1-4 BitFlow, Inc. Version F.0...

  • Page 13: Firmware, Camera Files And Downloads Kbn-1-5

    In all other ways, however, the two configurations do not have to match. If you have a requirement where this rule must be broken, please contact BitFlow’s support department. Custom combinations of firmware are available.
  • Page 14 The Karbon 1.3 General Description The Karbon-CL is a x8 PCI Express board. It can work in any PCI Express slot that it can fit it. Usually this means an x8 or x16 slot. However, some mother boards have x4 slots with x8 connectors.
  • Page 15 General Description and Architecture General Description The Karbon-CL is offered in two major configuration: the KBN-PCE-CL4, which sup- port up to four base CL cameras or two full CL cameras, and the KBN-PCE-CL2, which supports up to two base CL cameras or one full CL camera. The final D or F in the model number determines whether the board supports base CL cameras only (i.e.
  • Page 16 Figure 1-5 illustrates the Full CL virtual frame grabber (VFG) that is support on the Kar- bon-CL hardware. Since the Base CL interface requires one CL connectors, the KBN- PCE-CL2-D can support two of these virtual frame grabbers, and the KBN-PCE-CL4-D can support four of these virtual frame grabbers. KBN-1-8 BitFlow, Inc. Version F.0...
  • Page 17 The FIFO block, ?? Kilobytes deep, decouples the camera from the DMA engine. It is implemented with dual ported memories. Version F.0 BitFlow, Inc. KBN-1-9...
  • Page 18 UART on the Karbon platform. It can be switch between the various CL connectors for programming each camera in turn. The IO connector block has transmitters/receivers to communicate with external industrial equipment (triggers, encoders, light strobes etc.). KBN-1-10 BitFlow, Inc. Version F.0...

  • Page 19: The Karbon-Cl Models Kbn-1-11

    General Description and Architecture The Karbon-CL Models 1.4 The Karbon-CL Models There are two models in the Karbon-CL family, the KBN-PCE-CL2 and the KBN-PCE- CL4. Table 1-1 illustrates the capablitlites of each model. Table 1-1 Karbon-CL Models Capability KBN-PCE- KBN-PCE-...
  • Page 20 The Karbon-CL Models The Karbon KBN-1-12 BitFlow, Inc. Version F.0...

  • Page 21: Acquisition And Camera Control

    Acquisition and Camera Control Introduction Acquisition and Camera Control Chapter 2 2.1 Introduction This section covers acquisition and camera control for the R64-CL, Karbon-CL and the Neon-CL. Version F.0 BitFlow, Inc. KBN-2-1...

  • Page 22: Bitflow's Flow-Thru Architecture Kbn-2-2

    BitFlow’s Flow-Thru Architecture The Karbon 2.2 BitFlow’s Flow-Thru Architecture The MUX block in Figure 2-1 is composed of a chain of sub-blocks that make up the Flow-Thru Architecture (FTA). Figure 2-1 shows the structure of the FTA. All the data paths are 64-bit.
  • Page 23 Acquisition and Camera Control BitFlow’s Flow-Thru Architecture The amount of data written in the FIFOs is controlled by the Acquisition Window. The vertical and horizontal size of this window is programmed in the ALPF and the ACLP registers respectively (see Section 2.4). The timing of this window is determined by the camera and the acquisition state machine.
  • Page 24 BitFlow’s Flow-Thru Architecture The Karbon Channel Channel Channel Link Chip Link Chip Link Chip Channel X Channel Y Channel Z Equalizer Equalizer Equalizer FIFO FIFO FIFO Camera Link Pixel PIX_DEPTH Data Descrambler SHIFT_RAW, SHIFT_DSP, SHIFT_RAW_LEFT, Barrel Barrel Barrel Barrel SHIFT_DISP_LEFT,...
  • Page 25 2 cameras: 2 taps, odd-even lines MUX_8TS 8 taps, segmented MUX_BAY Bayer decoder, 1 tap 8 bit MUX_BAY_OE Bayer decoder, 2 taps, odd-even pixels MUX_BAY_2TS Bayer decoder, 2 taps, segmented MUX_4WI 4 taps, 4-way interleaved Version F.0 BitFlow, Inc. KBN-2-5...
  • Page 26 The Karbon Table 2-1 Firmware Options FORMAT Firmware Name Format Description MUX_2TOEPI 2 taps, odd-even pixels, both inverted MUX_1TI 1 tap, inverted MUX_8WI 8 taps, 8-way interleaved MUX_BAY_2TS_RI Bayer decoder, 2 taps, segmented, right inverted KBN-2-6 BitFlow, Inc. Version F.0...

  • Page 27: Generation Of Acquisition Windows Kbn-2-7

    (HSTART or LEN). This is done by the DELAY bits in CON14. The HCTAB is the Horizontal Control Table that generates the HSTART, see section on CTABs. Figure 2-2 shows the controls that generate the HAW. Version F.0 BitFlow, Inc. KBN-2-7...
  • Page 28 The VSTART bit in the VCTAB, if VAW_START = 1. The start of FEN, if VAW_START = 0. Data will be acquired in the window defined by the HAW and the VAW Figure 2-3 shows the controls that generate the VAW. KBN-2-8 BitFlow, Inc. Version F.0...
  • Page 29 Acquisition and Camera Control Generation of Acquisition Windows ALPF VSTART Vertical CTAB Generator VAW_START Figure 2-3 Generation of the Vertical Active Window, VAW Version F.0 BitFlow, Inc. KBN-2-9...
  • Page 30 VCOUNT - a synchronous counter that can be incremented, loaded and reset. The clock that drives VCOUNT is derived from the HCTAB, see below. VCOUNT is 17-bit wide and is connected to the address input of the VCTAB. KBN-2-10 BitFlow, Inc. Version F.0...
  • Page 31 General purpose vertical function 1 GPV2 General purpose vertical function 2 GPV3 General purpose vertical function 3 VSTART defines the start of the Vertical Acquisition Window (VAW), if the start is pro- vided by the VCTAB, see previous section. Version F.0 BitFlow, Inc. KBN-2-11...
  • Page 32 FEN. While we expect the camera to assert FEN, VCOUNT is still being incremented. If it takes too long for the camera to respond, VCOUNT will eventually reach and pass beyond 8000h. A vertical KBN-2-12 BitFlow, Inc. Version F.0...

  • Page 33: Horizontal Control Table Kbn-2-13

    The Horizontal Control Table (HCTAB) is 8 bits wide. The function of each bit is show in the following table. Figure 2-5 depicts the structure of the HCTAB. For clarity, the address and data path that allow the host to program the HCTAB are not shown Version F.0 BitFlow, Inc. KBN-2-13...
  • Page 34 The output of the HCTAB depends on the data that has been written in the HCTAB by the host. If the HCOUNT is free running, it will cyclically scan all the HCTAB’s addresses. Any arbitrary cyclic waveform can be implemented by programming the HCTAB with the adequate data. KBN-2-14 BitFlow, Inc. Version F.0...
  • Page 35 There are only two instances when we want to inhibit the incrementing of HCTAB. The first instance is when HCOUNT reaches 0000h, “Stop at Zero” case. The other instance is when HCOUNT reaches 1FF1h, the “Horizontal Stick” case. Version F.0 BitFlow, Inc. KBN-2-15...
  • Page 36 Operation on the rising/falling edge of LEN is selected by LENPOL, see CON14. The RESET_H Control RESET_H is the logic of reset HCOUNT. HCOUNT can be reset from several sources, according to HCNT_RST bitfield, see next section on camera synchronization. KBN-2-16 BitFlow, Inc. Version F.0...
  • Page 37 CTABs. The minimum horizontal pulse is 8 PCLKs. The minimum ver- tical pulse is one line. The CT’s can be steered to the Camera Controls (on the CL connectors) and to the GPOUTs, on the IO connector. Version F.0 BitFlow, Inc. KBN-2-17...
  • Page 38 VCNT_RLS_ZERO VCOUNT reset to 0000h VCNT_RST VCOUNT load with 8000h VCNT_LD VCOUNT frozen/released from 7FF0h VCNT_RLS_STK VCOUNT increment VCNT_INC Acquire (SNAP, GRAB, CONTINUOUS) ACQ_CON FREEZE acquisition FREEZE_CON ABORT acquisition ABORT_CON START vertical acquisition window VAW_START KBN-2-18 BitFlow, Inc. Version F.0...
  • Page 39 None Normal operation mode, no stop at 0000h TRIG_ASRT Edge Mode (aka Letter Mode), always stay at 0000h, release on TRIG_ASRT TRIG_HI Level Mode (aka Luggage Mode), stay at 0000h if TRIG_LO, release on TRIG_ASRT Version F.0 BitFlow, Inc. KBN-2-19...
  • Page 40 7ff0h. See Table 2-9. Table 2-9 VCNT_RLS_STK Initiator VCNT_RLS_STK Comments None Normal operation mode, no stop at 7FF0h VLOAD or VRESET Stick at 7FF0h till load (usually FEN) or reset asserted KBN-2-20 BitFlow, Inc. Version F.0...
  • Page 41 GRAB/SNAP/ SNAP FREEZE TRIG_ASRT Triggered initiated GRAB/SNAP/ FREEZE TRIG_ASRT and HOST_ Triggered SNAP WCMD_GRAB TRIG_HI Continuous data, wo. CTABs Note: See also Section 2.7 for more details on the how the acquisition commands work. Version F.0 BitFlow, Inc. KBN-2-21...

  • Page 42: Horizontal Operations And Events Kbn-2-22

    HCOUNT. Each operation can be initiated by some event. The selection of the event that will initiate the specific operation is done by a set of three control bits related to each operation. KBN-2-22 BitFlow, Inc. Version F.0...
  • Page 43 RESET from SW RST_SW FEN asserted FEN_ASRT The sections below enumerate all of the horizontal operations and how the various events can initiate them. The control of each operation is independent from all of the others. Version F.0 BitFlow, Inc. KBN-2-23...
  • Page 44 1ff0h. See Table 2-18. Table 2-18 HCNT_RLS_STK Initiator HCNT_RLS_STK Comments None Normal operation mode, no stop at 1FF0h HLOAD or HRESET Stay at x1FF0 till load (usually LEN) or reset asserted KBN-2-24 BitFlow, Inc. Version F.0...
  • Page 45 This operation controls how and when HCOUNT loads (jumps to) 2000h (see Table 2- 19). Table 2-19 HCNT_LD Initiator HCNT_LD Comments None No load LEN_ASRT Load on LEN assert, qualified with ENH- LOAD column ENC_ASRT Load on ENCODER assert, qualified with ENHLOAD column Version F.0 BitFlow, Inc. KBN-2-25...

  • Page 46: Acquisition Command And Status Kbn-2-26

    For a SNAP command, when the SNAP starts, the AQCMD bits are cleared. Note that for SNAP, the AQCMD bits are written by the host and cleared by the state machine. If during a SNAP/GRAB operation another SNAP/GRAB command is issued, it is ignored. KBN-2-26 BitFlow, Inc. Version F.0...
  • Page 47 ACQ_CON=2 mode. Here, as long as the GRAB command is on, a frame will be acquired for every assertion of the TRIGGER. In this mode, there is no need for the host to write a new command. Version F.0 BitFlow, Inc. KBN-2-27...
  • Page 48 Freeze command written AQSTAT reset, grabbing ends Figure 2-7 Grab Command Timing VACTIVE AQCMD AQSTAT Grab command written AQSTAT set, grabbing starts Abort command written AQCMD reset, AQSTAT reset, grabbing ends Figure 2-8 Abort Command Timing KBN-2-28 BitFlow, Inc. Version F.0...
  • Page 49 Acquisition and Camera Control Acquisition Command and Status VACTIVE AQCMD AQSTAT TRIG Snap command written Trigger asserts AQCMD reset and AQSTAT set AQSTAT reset Figure 2-9 Snap Command Timing with ACQ_CON = 2 Version F.0 BitFlow, Inc. KBN-2-29...
  • Page 50 Acquisition Command and Status The Karbon VACTIVE AQCMD AQSTAT TRIG Grab command written Trigger asserts AQSTAT set AQSTAT set AQSTAT reset AQSTAT reset Figure 2-10 Grab Command Timing with ACQ_CON = 2 KBN-2-30 BitFlow, Inc. Version F.0...

  • Page 51: Trigger Processing Kbn-2-31

    8192 lines (granularity is 8 lines). This delay works only with the external hardware trigger. Figure 2-11 illustrates the trigger circuit. TRIGGER_TTL TRIGGER_DIF TRIGGER_OPTO DELAY LINE TRIGGER SEL_TRIG TRIGGER_DELAY TRIGPOL EN_TRIGGER SW_TRIG Figure 2-11 Trigger Circuit Version F.0 BitFlow, Inc. KBN-2-31...

  • Page 52: Encoder Processing Kbn-2-32

    The selected external encoder can be divided by the value in the ENC_DIV register. Figure 2-12 illustrates the encoder circuit. ENCODER_TTL ENCODER_DIF ENCODER_OPTO ENCODER SELENC ENC_DIV ENCPOL EN_ENCODER SW_ENC Figure 2-12 Encoder Circuit KBN-2-32 BitFlow, Inc. Version F.0...

  • Page 53: The On-Board Signal Generator Kbn-2-33

    Set FREE_RUN_RATE = 1831 (3662/2). This will produce the 2Hz rate. Set FREE_RUN_HI = 128 ( 3662.1x0.035 = 128.1 ). This will produce a pulse 0.035 seconds wide. Set SIG_GEN_POL = 0. The output needed is active high. Version F.0 BitFlow, Inc. KBN-2-33...
  • Page 54 The On-Board Signal Generator The Karbon Divide By 8K Clock Generator CFREQ SCALE_BY8 CLOCK_IN Signal FREE_RUN_HI SIG_GEN Generator FREE_RUN_RATE SIG_GEN_POL Figure 2-13 Signal Generator KBN-2-34 BitFlow, Inc. Version F.0...
  • Page 55 Section 3.5 cycling HCOUNT Acquistion status, HCTAB CON6 Section 3.5 cycling LINES_TOGO Acquistion status, current line in CON19 Section 3.5 frame FIFO_EQ Camera status, video value CON20 Section 3.6 DEST_ADD DMA running CON22 Section 3.7 Version F.0 BitFlow, Inc. KBN-3-1...
  • Page 56 FCOUNT is a 3-bit frame counter that is incremented by the rising edge of FACTIVE. It can be used to track acquisition, especially in triggered modes. FCOUNT works for both area scan and line scan cameras. KBN-3-2 BitFlow, Inc. Version F.0...
  • Page 57 LEN does not reach the acquisition cir- cuitry. FENCOUNT is a 2-bit counter clocked by the camera’s FEN. Reading a constant value from this register indicates that the camera’s FEN does not reach the acquisition cir- cuitry. Version F.0 BitFlow, Inc. KBN-3-3...
  • Page 58 RD_TRIG_DIFF/TTL/OPTO, RD_ENC_DIFF/TTL/OPTO The Karbon 3.4 RD_TRIG_DIFF/TTL/OPTO, RD_ENC_DIFF/TTL/OPTO The level of all three trigger and all three encoder inputs can be read. This helps establish connection with external industrial equipment. KBN-3-4 BitFlow, Inc. Version F.0...
  • Page 59 HCOUNT is the 2 LSB of the HCTAB address counter. This register indicates only if the HCTAB is cycling. Reading a constant value on HCOUNT indicates that the HCTAB address is stuck. LINES_TOGO specifies how more many lines there are till the end of the frame. Version F.0 BitFlow, Inc. KBN-3-5...
  • Page 60 It is helpful to determine if the camera is reacting to light. Convering the cam- era’s lense will yield a low value in this register. Pointing the camera to a light source will yield a high value in this register. KBN-3-6 BitFlow, Inc. Version F.0...
  • Page 61 System Status DEST_ADD 3.7 DEST_ADD This register gives the DMA destination address. During acquisition, this register should change. Reading a constant value from this register suggests that the DMA operation is not progressing. Version F.0 BitFlow, Inc. KBN-3-7...
  • Page 62 DEST_ADD The Karbon KBN-3-8 BitFlow, Inc. Version F.0...
  • Page 63 All of the registers are 32 bits wide. These wide registers are named CON0, CON1, etc. Each registers is broken into one or more bitfields. Bitfields can be from one to 32 bits wide. Each bitfield controls a specific function on the board. Version F.0 BitFlow, Inc. KBN-4-1...
  • Page 64 0 to 7. Finally this section also indicates if the register is specific to only one product family. Bitfield discussion This section explains the purposed of the bitfield in detail. Usually meaning of every possible value of the bitfield is listed. KBN-4-2 BitFlow, Inc. Version F.0...
  • Page 65 Bitfield can only be written. Reading from this bit will return meaning- less values. Karbon This bitfield is functional on the Karbon. Neon This bitfield is functional on the Neon This bitfield is functional on the R64 family. Version F.0 BitFlow, Inc. KBN-4-3...
  • Page 66 4.3 CON0 Register Name CFGDATA CFGSTATUS CFGEN CFGDONE CFGCLOCK FW_7MHZ Reserved POCL_EN CFREQ CFREQ CFREQ Reserved L_CLKCON L_CLKCON SEL_UCLKC_7MHZ RELOAD_FPGA FW_SEL FW_SEL FW_SEL CPLD_MODE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved KBN-4-4 BitFlow, Inc. Version F.0...
  • Page 67 This bit turns the the PoCL Safe Power system. This bit must be set to one in order to enable power to PoCL cameras. However, the system uses the Safe Power system, so a number of conditions must be met before power is actually applied to the camera. Version F.0 BitFlow, Inc. KBN-4-5...
  • Page 68 This bit selects the frequency that is used to driver the UART for serial communica- tions. This functionality is only available on boards with update firmware. The bit FW_ 7MHZ can be used to check the version of the firmware. SEL_UCLK_ Frequency 7MHZ 8 MHz 7.3 MHz KBN-4-6 BitFlow, Inc. Version F.0...
  • Page 69 CPLD_MODE R/W, CON0[19], Neon - [New] On the Neon, the CPLD used to load the FPGAs has two modes. This bit is used to set the mode. This is not a user programmable bit. Version F.0 BitFlow, Inc. KBN-4-7...
  • Page 70 4.4 CON1 Register Name VCNT_RLS_ZERO VCNT_RLS_ZERO VCNT_RLS_ZERO VCNT_RST VCNT_RST VCNT_RST VCNT_LD VCNT_LD VCNT_LD VCNT_RLS_STK VCNT_RLS_STK VCNT_RLS_STK ABORT_CON ABORT_CON ABORT_CON NO_VB_WAIT ACQ_CON ACQ_CON ACQ_CON FREEZE_CON FREEZE_CON FREEZE_CON ACQ_SAFETY NO_RULE INT_CTAB INT_OVSTEP INT_HW INT_TRIG INT_SER INT_QUAD INT_TRIGCON INT_TRIGCON KBN-4-8 BitFlow, Inc. Version F.0...
  • Page 71 VCOUNT is reset by the assertion of FEN or by the VRESET column in the VCTAB. 4 (100b) VCOUNT is reset by the de-assertion of the trigger, or by the VRESET column in the VCTAB. Version F.0 BitFlow, Inc. KBN-4-9...
  • Page 72 This bit has the following properties. NO_VB_WAIT Meaning Wait for the Vertical Active Window before executing the Head Tag Quad. Do not wait for the Vertical Active Window for exe- cuting the Head Tag Quad. KBN-4-10 BitFlow, Inc. Version F.0...
  • Page 73 R/W, CON1[23], R64 Test/diagnostic bit. For normal operation this bit should always be set to 0. When set to 1, the DMA engine will DMA data at maximum speed, regardless of wether the data is valid. Version F.0 BitFlow, Inc. KBN-4-11...
  • Page 74 1. This interrupt can be cleared by the host writing a 0 to this location. For the host to be able to write to this location, the CMDWRITE code must be set to 3. INT_HW Meaning No interrupt from HW Interrupt from HW asserted. KBN-4-12 BitFlow, Inc. Version F.0...
  • Page 75 0 to this location. For the host to be able to write to this location, the CMDWRITE code must be set to 5. INT_QUAD Meaning No interrupt from QUAD Interrupt from QUAD asserted. Version F.0 BitFlow, Inc. KBN-4-13...
  • Page 76 0 (00b) reserved 1 (01b) Assert interrupt on rising edge of trigger. 2 (10b) Assert interrupt on falling edge of trigger. 3 (11b) Assert interrupt on both the rising and the falling edge of the trigger. KBN-4-14 BitFlow, Inc. Version F.0...
  • Page 77 4.5 CON2 Register Name HCNT_RLS_ZERO HCNT_RLS_ZERO HCNT_RLS_ZERO HCNT_RST HCNT_RST HCNT_RST HCNT_LD HCNT_LD HCNT_LD HCNT_RLS_STK HCNT_RLS_STK HCNT_RLS_STK RST_HVCOUNT RST_DPM_ADDR CTABHOLD Reserved CC1_CON CC1_CON CC1_CON CC2_CON CC2_CON CC2_CON CC3_CON CC3_CON CC3_CON CC4_CON CC4_CON CC4_CON CMDWRITE CMDWRITE CMDWRITE QTBSRC Version F.0 BitFlow, Inc. KBN-4-15...
  • Page 78 HCOUNT will be loaded by assertion of LEN if the ENHLOAD function in the HCTAB is set to 1. 2 (010b) HCOUNT will be loaded by assertion of encoder if the ENHLOAD function in the HCTAB is set to 1. KBN-4-16 BitFlow, Inc. Version F.0...
  • Page 79 This bit has the following properties. RST_DPM_ADDR Meaning Normal operation for DPM_ADDR Reset DPM_ADDR.. CTABHOLD R/W, CON2[14], Karbon, Neon, R64 This bit has the following properties. CTABHOLD Meaing Normal operation for CTABs Freeze outputs and operation of CTABs.. Version F.0 BitFlow, Inc. KBN-4-17...
  • Page 80 Signal steered to CC2 0 (000b) CT0 from CTAB 1 (001b) CT1 from CTAB 2 (010b) CT2 from CTAB 3 (011b) Free running signal generated on-board 4 (100b) On-board generated CLOCK 5 (101b) GPIN0 6 (110b) 7 (111b) KBN-4-18 BitFlow, Inc. Version F.0...
  • Page 81 Signal steered to CC4 0 (000b) CT0 from CTAB 1 (001b) CT1 from CTAB 2 (010b) CT2 from CTAB 3 (011b) Free running signal generated on-board 4 (100b) CT3 from CTAB 5 (101b) GPIN0 6 (110b) 7 (111b) Version F.0 BitFlow, Inc. KBN-4-19...
  • Page 82 No interrupt can be accessed by host 1 (001b) INT_CTAB 2 (010b) INT_OVSTP 3 (011b) INT_HW 4 (100b) INT_TRIG 5 (101b) INT_QTAB 6 (110b) INT_EOF 7 (111b) reserved QTBSRC RO, CON2[31], Karbon, Neon, R64 Always read back 1. KBN-4-20 BitFlow, Inc. Version F.0...
  • Page 83 CON3 Register 4.6 CON3 Register Name AQCMD AQCMD AQSTAT AQSTAT FACTIVE FCOUNT FCOUNT FCOUNT REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC REV_DCC AUX_DETECT GPIN0 GPIN1 GPIN2 GPIN3 GPIN4 Version F.0 BitFlow, Inc. KBN-4-21...
  • Page 84 RO, CON3[7..5], Karbon, Neon, R64 This is a 3-bit modulo-8 counter. The counter is incremented by the start of the Verti- cal Acquisition Window. It is used as a debug/diagnostic tool. REV_DCC WO, CON3[23..8], Karbon, Neon, R64 FW revision. KBN-4-22 BitFlow, Inc. Version F.0...
  • Page 85 RO, CON3[31..30], Karbon, Neon, R64 This register reads back the setting of the two mechanical switches installed on the edge of the board. Helps physical identification of up to four boards installed in one Version F.0 BitFlow, Inc. KBN-4-23...
  • Page 86 4.7 CON4 Register Name ENINT_CTAB ENINT_OVSTEP ENINT_HW ENINT_TRIG ENINT_SER ENINT_QUAD EOF_IN_AQ INT_ANY ENINT_ALL AUX_CAM GPOUT0 GPOUT1 GPOUT2 GPOUT3 GPOUT4 GPOUT5 GPOUT6 RST_SER RST_OVS CL_DISABLE LCOUNT LCOUNT PCOUNT PCOUNT FENCOUNT FENCOUNT POP_TOSS PUMP_OFF DMA_BUSY HAW_START VAW_START KBN-4-24 BitFlow, Inc. Version F.0...
  • Page 87 R/W, CON4[2], Karbon, Neon, R64 This bit has the following properties. ENINT_HW Meaning HW interrupt disabled HW interrupt enabled ENINT_TRIG R/W, CON4[3], Karbon, Neon, R64 This bit has the following properties. ENINT_TRIG Meaning Trigger interrupt disabled Trigger interrupt enabled Version F.0 BitFlow, Inc. KBN-4-25...
  • Page 88 This bit can be checked first to see if some event caused the interrupt, before inquiring other bits to see the actual cause of the interrupt. ENINT_ALL R/W, CON4[8], Neon, R64 - [New] This bit enables or disables all interrupts on boards that use the PLDA engine. KBN-4-26 BitFlow, Inc. Version F.0...
  • Page 89 IO connector. See also CON8 for signals steered to the GPOUTs GPOUT6 R/W, CON4[16], Karbon, Neon, R64 The value written in this register will be reflected on the open collector output 33 on the IO connector. See also CON8 for signals steered to the GPOUTs Version F.0 BitFlow, Inc. KBN-4-27...
  • Page 90 LCOUNT RO, CON4[22..21], Karbon, Neon, R64 This is a 2-bit counter clocked by the LEN supplied by the Camera Link main connec- tor. Reading this counter and observing changes between reads indicates an active LEN. KBN-4-28 BitFlow, Inc. Version F.0...
  • Page 91 DMA engine’s normal operation. Inhibit DMA operation. DMA_BUSY RO, CON4[29], R64, Karbon, Neon, R64 This bit indicates the state of the DMA engine. DMA_BUYS Meaning DMA engine is idle. DMA engine is currently DMAing data. Version F.0 BitFlow, Inc. KBN-4-29...
  • Page 92 VAW_START Meaning The start of the Vertical Active Window (VAW) is con- trolled by the start of the FEN. The start of the Vertical Active Window is controlled by the VSTART column in the VCTAB. KBN-4-30 BitFlow, Inc. Version F.0...
  • Page 93 4.8 CON5 Register Name SEL_TRIG SEL_TRIG TRIGPOL SW_TRIG SELENC SELENC ENCPOL SW_ENC RD_TRIG_DIFF RD_TRIG_TTL RD_TRIG_OPTO RD_ENC_DIFF RD_ENC_TTL RD_ENC_OPTO TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY TRIGGER_DELAY ENINT_EOF INT_EOF RD_FEN CCSYNC CCSYNC CCSYNC EN_TRIGGER EN_ENCODER Version F.0 BitFlow, Inc. KBN-4-31...
  • Page 94 R/W, CON5[3], Karbon, Neon, R64 The SW trigger is OR-ed with the external trigger. The polarity of the SW trigger is always active-HI. TRIGPOL has no effect on the SW trigger. SW_TRIG Meaning SW trigger de-asserted. SW trigger asserted. KBN-4-32 BitFlow, Inc. Version F.0...
  • Page 95 This register reflects the status of the differential trigger input on the IO connector, pins 1,2. RD_TRIG_TTL RO, CON5[9], Karbon, Neon, R64 This register reflects the status of the TTL trigger input on the IO connector, pin 3. Version F.0 BitFlow, Inc. KBN-4-33...
  • Page 96 VAW). This ordinarily corresponds to the camera’s end of frame. However, if the board is in start-stop triggered mode, this interrupt with also occur when the trigger de-asserts. The host writing a 1 to this bit will also cause and interrupt. The interrupt KBN-4-34 BitFlow, Inc. Version F.0...
  • Page 97 5 (101b) Reserved 6 (110b) Reserved 7 (111b) Reserved EN_TRIGGER R/W, CON5[30], Karbon, Neon, R64 This bitfield has the following properties. EN_TRIGGER Meaning External (HW) selected trigger is disabled. External (HW) selected trigger is enabled. Version F.0 BitFlow, Inc. KBN-4-35...
  • Page 98 CON5 Register The Karbon EN_ENCODER R/W, CON5[31], Karbon, Neon, R64 This bitfield has the following properties. EN_ENCODER Meaning External (HW) selected encoder is disabled. External (HW) selected encoder is enabled. KBN-4-36 BitFlow, Inc. Version F.0...
  • Page 99 4.9 CON6 Register Name VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT VCOUNT ENC_DIV ENC_DIV ENC_DIV ENC_DIV ENC_DIV ENC_DIV ENC_DIV ENC_DIV ENC_DIV ENC_DIV HCOUNT HCOUNT Reserved Reserved Version F.0 BitFlow, Inc. KBN-4-37...
  • Page 100 Programming this register to 0 or 1 will both divide by HCOUNT R/W, CON6[29..28], Karbon, Neon, R64 This register reflects the current value of the two LSBs of the HCOUNT. Reading this register and observing changes in its value means that the HCOUNT is cycling. KBN-4-38 BitFlow, Inc. Version F.0...
  • Page 101 4.10 CON7 Register Name AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT AQ_COUNT SEL_REG_GEN SEL_REG_GEN GEN_ONESHOT Reserved TAG_BANK TAG_BANK TAG_BANK TAG_BANK TAG_BANK TAG_BANK Reserved Reserved Version F.0 BitFlow, Inc. KBN-4-39...
  • Page 102 GEN_ONESHOT Meaning Signal generator is free running. Signal generator syncrhonized to the external encoder signal. TAG_BANK RO, CON7[29..24], R64 This is the calculated bank from the address generator latched by the TAG QUAD; diagnostics/test register. KBN-4-40 BitFlow, Inc. Version F.0...
  • Page 103 4.11 CON8 Register Name GPOUT0_CON GPOUT0_CON GPOUT0_CON GPOUT1_CON GPOUT1_CON GPOUT1_CON GPOUT2_CON GPOUT2_CON GPOUT2_CON GPOUT3_CON GPOUT3_CON GPOUT3_CON GPOUT4_CON GPOUT4_CON GPOUT4_CON GPOUT5_CON GPOUT5_CON GPOUT5_CON GPOUT6_CON GPOUT6_CON GPOUT6_CON Reserved Reserved Reserved RLE_LOAD_H RLE_LOAD_H RLE_LOAD_H RLE_LOAD_H RLE_LOAD_V RLE_LOAD_V RLE_LOAD_V RLE_LOAD_V Version F.0 BitFlow, Inc. KBN-4-41...

  • Page 104: Gpout0_Con

    5 (101b) Internally generated CLOCK (frequency controlled by CFREQ in CON1). 6 (110b) Internally generated signal (frequency and duty- cycle controlled by CON17). 7 (111b) The encoder input signal is routed to the GPOUT0 output signal. KBN-4-42 BitFlow, Inc. Version F.0...

  • Page 105: Gpout2_Con

    3 (011b) CT2 from CTAB. 4 (100b) CT3 from CTAB. 5 (101b) Internally generated CLOCK (frequency controlled by CFREQ in CON1). 6 (110b) Internally generated signal (frequency and duty- cycle controlled by CON17). 7 (111b) reserved. Version F.0 BitFlow, Inc. KBN-4-43...

  • Page 106: Gpout4_Con

    3 (011b) CT2 from CTAB. 4 (100b) CT3 from CTAB. 5 (101b) Internally generated CLOCK (frequency controlled by CFREQ in CON1). 6 (110b) Internally generated signal (frequency and duty- cycle controlled by CON17). 7 (111b) reserved. KBN-4-44 BitFlow, Inc. Version F.0...

  • Page 107: Gpout6_Con

    RLE entry, not the CTAB location. In other words, if the jump point is 0x20000 CTAB location, but the RLE entry for this location is 3, then this register should be pro- grammed to 3. Version F.0 BitFlow, Inc. KBN-4-45...
  • Page 108 4.12 CON9 Register Name MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV MUX_REV TRIM TRIM TRIM TRIM FW_TYPE FW_TYPE FW_TYPE FW_TYPE DISPLAY CLIP SHORT_FRAME RST_CALC_BANK CALC_BANK CALC_BANK CALC_BANK CALC_BANK CALC_BANK CALC_BANK ACPL_MUL ACPL_MUL KBN-4-46 BitFlow, Inc. Version F.0...
  • Page 109 8 LSB of the data will be acquired in each lane. To be able to display the 8 MSB (or any other consecutive group of 8 bits), the data must be shifted accordingly with the barrel shifter. For 9 to 16-bit cameras, setting this bit will result in an 8-bit dis- Version F.0 BitFlow, Inc. KBN-4-47...
  • Page 110 R/W, CON9[23], Karbon, Neon, R64 BANK For normal operation this bit should be 0. RST_CALC_BANK Meaning Normal operation Reset the calculated starting bank. CALC_BANK RO, CON9[29..24], Karbon, Neon, R64 Value of the current calculated starting bank. KBN-4-48 BitFlow, Inc. Version F.0...
  • Page 111 ACPL (Active Clocks Per Line) register. ACPL_MUL Meaning 0 (00b) Normal operation. ACPL is used as is 1 (01b) ACPL is multiplied by 2 2 (10b) Reserved 3 (11b) Reserved Version F.0 BitFlow, Inc. KBN-4-49...
  • Page 112 4.13 CON10 Register Name ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL ACPL FORMAT FORMAT FORMAT FORMAT FORMAT VID_SOURCE VID_SOURCE VID_SOURCE VID_SOURCE PIX_DEPTH PIX_DEPTH PIX_DEPTH PIX_DEPTH PIX_DEPTH FORCE_8BIT KBN-4-50 BitFlow, Inc. Version F.0...
  • Page 113 8 taps, segmented 14 (01110b) MUX_BAY Bayer decoder, 1 tap 8 bit 15 (01111b) MUX_BAY_OE Bayer decoder, 2 taps, odd-even pixels 16 (10000b) MUX_BAY_2TS Bayer decoder, 2 taps, segmented 17 (10001b) MUX_4WI 4 taps, 4-way interleaved Version F.0 BitFlow, Inc. KBN-4-51...
  • Page 114 This register defines the pixel depth as well as the color order and packing mode for RGB cameras. PIX_DEPTH Bit/pixel, color order and packing 0 (0000b) 8 bits 1 (0001b) 10 bits 2 (0010b) 12 bits 3 (0011b) 14 bits KBN-4-52 BitFlow, Inc. Version F.0...
  • Page 115 3x12 BGR, DMAed as 48 bits (packed), display mode is 24 bits FORCE_8BIT R/W, CON10[31], Karbon, Neon, R64 This bitfield has the following properties. FORCE_8BIT Meaning 0 (000b) Normal operation 1 (001b) Only 8 LSB of pixel will be acquired Version F.0 BitFlow, Inc. KBN-4-53...
  • Page 116 4.14 CON11 Register Name ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD ALAST_ADD Reserved BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD BLAST_ADD UART_MASTER KBN-4-54 BitFlow, Inc. Version F.0...
  • Page 117 Last address for lane B (used for diagnostics). UART_MASTER R/W, CON11[31], Karbon - [New] This bit controls which Karbon VFG is in control of the UART. Poke this bit to one in order to take control of the UART. Version F.0 BitFlow, Inc. KBN-4-55...
  • Page 118 4.15 CON12 Register Name CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD CLAST_ADD Reserved DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD DLAST_ADD Reserved KBN-4-56 BitFlow, Inc. Version F.0...
  • Page 119 Camera Control Registers CON12 Register CLAST_ADD RO, CON11[14..0], Karbon, Neon, R64 Last address for lane C (used for diagnostics). DLAST_ADD R/W, CON11[30..16], Karbon, Neon, R64 Last address for lane D (used for diagnostics). Version F.0 BitFlow, Inc. KBN-4-57...
  • Page 120 4.16 CON13 Register Name VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK VIDEO_MASK KBN-4-58 BitFlow, Inc. Version F.0...
  • Page 121 With the aid of this mask, individual bits in the video data stream can be set to 0. The 32 bit mask is duplicated for the 32 MSB of a 64 bit word. Bit N in VIDEO_MASK Meaning Set bit N to 0 Pass bit N as is Version F.0 BitFlow, Inc. KBN-4-59...
  • Page 122 4.17 CON14 Register Name SWRESET FENPOL LENPOL BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS BUTTONS SHIFT_RAW SHIFT_RAW SHIFT_RAW SHIFT_RAW SHIFT_RAW_LEFT DELAY DELAY DELAY SWAP UART_CON UART_CON Reserved DPM_SPLIT DPM_SPLIT DPM_SPLIT DPM_SPLIT KBN-4-60 BitFlow, Inc. Version F.0...
  • Page 123 LEN is asserted on falling edge. BUTTONS R/W, CON14[15..3], Karbon, Neon, R64 R/W register for test/diagnostics. SHIFT_RAW R/W, CON14[19..16], Karbon, Neon, R64 This register defines for the barrel shifter the amount of shift for the data to be acquired Version F.0 BitFlow, Inc. KBN-4-61...
  • Page 124 HAW is delayed by 4 clocks 5 (101b) HAW is delayed by 5 clocks 6 (11ob) HAW is delayed by 6 clocks 7 (111b) HAW is delayed by 7 clocks SWAP R/W, CON14[24], Karbon, Neon, R64 Future use. KBN-4-62 BitFlow, Inc. Version F.0...
  • Page 125 This register controls how incoming data is written to the DPM. DPM_SPLIT Mode 0 (0000b) Normal mode 1 (0001b) Each tap’s output is split in half. 2 (0010b) to 14 (1110b) Reserved 15 (1111b) Each tap’s output is written in 4K chunks Version F.0 BitFlow, Inc. KBN-4-63...
  • Page 126 4.18 CON17 Register Name FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_RATE FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI FREE_RUN_HI KBN-4-64 BitFlow, Inc. Version F.0...
  • Page 127 Setting this register to 100, for example, will yield a signal that is 1 for 100 clocks, regardless of the period. Obviously, the number programmed in FREE_RUN_ RATE must be larger than the number programmed in FREE_RUN_HI. Version F.0 BitFlow, Inc. KBN-4-65...
  • Page 128 4.19 CON18 Register Name ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF ALPF TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV TOP_REV SIG_GEN_POL SCALE_BY8K KBN-4-66 BitFlow, Inc. Version F.0...
  • Page 129 Scaling down the clock to the free running generator can yield waveforms on the order of single Hz. SCALE_BY8K Meaning Use on board CLOCK as is for the free running signal generator Divide by 8K the on-board CLOCK to be used by the free running generator.. Version F.0 BitFlow, Inc. KBN-4-67...
  • Page 130 4.20 CON19 Register Name LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO LINES_TOGO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved KBN-4-68 BitFlow, Inc. Version F.0...
  • Page 131 Camera Control Registers CON19 Register LINES_TOGO R/W, CON19[16..0], Karbon, Neon, R64 This register will reflect the number of remaining lines left to be acquired till the end of the frame. Version F.0 BitFlow, Inc. KBN-4-69...
  • Page 132 4.21 CON20 Register Name FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ FIFO_EQ VID_BRL VID_BRL VID_BRL VID_BRL VID_BRL VID_BRL VID_BRL VID_BRL VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM VIDEO_2DPM COLOR_MASK COLOR_MASK SHIFT_DSP_SELECT SHIFT_DSP SHIFT_DSP SHIFT_DSP SHIFT_DSP SHIFT_DSP_LEFT KBN-4-70 BitFlow, Inc. Version F.0...
  • Page 133 SHIFT_DSP_SELECT Meaning Supply barrel shifter with the acquisition shift code Supply barrel shifter with the display shift code. SHIFT_DISP R/W, CON20[30..27], Karbon, Neon, R64 This register holds the shift amount for data to be displayed. Version F.0 BitFlow, Inc. KBN-4-71...
  • Page 134 CON20 Register The Karbon SHIFT_DSP_LEFT R/W, CON20[31], Karbon, Neon, R64 This bitfield has the following properties. SHIFT_DSP_LEFT Meaning Shift display data right Shift display data left. KBN-4-72 BitFlow, Inc. Version F.0...
  • Page 135 BLUE_GAIN BLUE_GAIN BLUE_GAIN BLUE_GAIN DECODER_OUT DECODER_OUT DECODER_OUT Reserved BAYER_BIT_DEPTH BAYER_BIT_DEPTH DECODER_PHASE DECODER_PHASE CON21 is a “soft” register. Soft registers change definitions depending on the version board and the firmware that is downloaded to the board. Version F.0 BitFlow, Inc. KBN-4-73...
  • Page 136 Decode intensity on all three channels 3 (011b) Decode red on all three channels 4 (100b) Decode green on all three channels 5 (101b) Decode blue on all three channels 6 (110b) Reserved 7 (111b) Reserved KBN-4-74 BitFlow, Inc. Version F.0...
  • Page 137 CCD. DECODER_PHASE Meaning 0 (00b) First two pixels: Blue, Green 1 (01b) First two pixels: Green, Blue 2 (10b) First two pixels: Red, Green 3 (11b) First two pixels: Green, Red Version F.0 BitFlow, Inc. KBN-4-75...
  • Page 138 4.23 CON23 Register Name DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE DPM_SIZE Reserved Reserved Reserved Reserved Reserved Reserved Reserved CTAB_INT_CON LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT LINES_PER_INT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved KBN-4-76 BitFlow, Inc. Version F.0...
  • Page 139 CTAB interrupt. The interrupt rate will be every N lines, where N is the value programmed in this register. Note that CTAB_INT_CON must be set to one in order for the interrupts to be seen by the host. Version F.0 BitFlow, Inc. KBN-4-77...
  • Page 140 LUT_HOST_ADDR LUT_HOST_ADDR LUT_HOST_ADDR LUT_HOST_ADDR LUT_BANK LUT_BANK Reserved LUT_DATA_WRITE_ LUT_HOST_LANE LUT_HOST_LANE LUT_WEN LUT_HOST_ACCESS CON24 is a “soft” register. Soft registers change definitions depending on the version board and the firmware that is downloaded to the board. KBN-4-78 BitFlow, Inc. Version F.0...
  • Page 141 R/W CON24[23..16], Karbon, R64 ADDR This register is used to set the address for a read operation from the LUT memory or a write operation to the LUT memory. See the description of LUT_HOST_DATA for more details. Version F.0 BitFlow, Inc. KBN-4-79...
  • Page 142 When LUT_DATA_WRITE_SEL is set to 1, Writing a 1 to this bit casues the value in LUT_HOST_DATA to be transfered to the LUT memory. When LUT_DATA_WRITE_SEL is set to 0, writing to this bit has no effect. See LUT_HOST_DATA for more information. KBN-4-80 BitFlow, Inc. Version F.0...
  • Page 143 LUT_HOST_ R/W, CON24[31], Karbon, R64 ACCESS These bits turns on and off host access to the LUT.. DECODER_OUT Meaning The LUT cannot be accessed by the host The LUT can be accessed by the host Version F.0 BitFlow, Inc. KBN-4-81...
  • Page 144 4.25 CON25 Register Name DELAY_TAP1 DELAY_TAP1 DELAY_TAP1 DELAY_TAP1_SEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved KBN-4-82 BitFlow, Inc. Version F.0...
  • Page 145 This bit selects the register that controls the delay for tap 1. Tap 0 is always controlled by the register DELAY. DELAY_TAP1_SEL Meaning Tap 1 is controlled by DELAY Tap 1 is controlled by DELAY_TAP1 Version F.0 BitFlow, Inc. KBN-4-83...
  • Page 146 4.26 CON26 Register Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved KBN-4-84 BitFlow, Inc. Version F.0...
  • Page 147 4.27 CON27 Register Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version F.0 BitFlow, Inc. KBN-4-85...
  • Page 148 4.28 CON36 Register Name MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO MEM_ADDR_LO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved KBN-4-86 BitFlow, Inc. Version F.0...
  • Page 149 CON36 Register MEM_ADDR_LO R/W, CON25[15..0], Neon - [New] This register is the lower 16 bits used to access the flash or ROM memory on boards that have it. This is not a user programmable register. Version F.0 BitFlow, Inc. KBN-4-87...
  • Page 150 4.29 CON37 Register Name MEM_ADDR_HI MEM_ADDR_HI MEM_ADDR_HI MEM_ADDR_HI MEM_CS MEM_WRITE DWNLD_MODE DWNLD_MODE MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved KBN-4-88 BitFlow, Inc. Version F.0...
  • Page 151 R/W, CON37[7..6], Neon - [New] MEM_DATA R/W, CON37[15..8], Neon - [New] This bitfield provides data access used when reading or writting the flash or ROM on boards that support these features. This is not a user programmable register. Version F.0 BitFlow, Inc. KBN-4-89...
  • Page 152 4.30 CON38 Register Name POCL_POWER_ON POCL_EN_GND POCL_CLOCK_WAIT Reserved POCL_SENSE POCL_CLK_ DETECTED POCL_DETECTED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved KBN-4-90 BitFlow, Inc. Version F.0...
  • Page 153 PoCL state machine is watching the impen- dence on the CL cable. If the impendence of a PoCL camera is detected, the power will be applied. It a short is detected, indicating a legacy camera/cable has been con- Version F.0 BitFlow, Inc. KBN-4-91...
  • Page 154 This register indicates that the PoCL state machine has detected a PoCL camera.. POCL_DETECTED Meaning The PoCL state machine has not detected a PoCL- camera. The PoCL state machine has detected a PoCL cam- era. KBN-4-92 BitFlow, Inc. Version F.0...
  • Page 155 Karbon/Neon DMA Registers Introduction Karbon/Neon DMA Registers Chapter 5 5.1 Introduction This section enumerates all of the registers that control DMA on boards using the PLDA DMA engine (e.g. Karbon-CL). The formatting is explained in Section 4.2. Version F.0 BitFlow, Inc. KBN-5-1...
  • Page 156 5.2 CON28 Register Name FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO KBN-5-2 BitFlow, Inc. Version F.0...
  • Page 157 This is the low word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. This register can be written at any time, but the DMA engine only loads this value when byte count (as set by CHAIN_DATA_SIZE) goes to zero. Version F.0 BitFlow, Inc. KBN-5-3...
  • Page 158 5.3 CON29 Register Name FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI KBN-5-4 BitFlow, Inc. Version F.0...
  • Page 159 This is the high word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. This register can be written at any time, but the DMA engine only loads this value when byte count (as set by CHAIN_DATA_SIZE) goes to zero. Version F.0 BitFlow, Inc. KBN-5-5...
  • Page 160 5.4 CON30 Register Name CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE CHAIN_DATA_SIZE KBN-5-6 BitFlow, Inc. Version F.0...
  • Page 161 DMA engine when DMA is initiated. This value is then decremented every DMA transfer. When the count reached zero, this value in this register is reloaded into the DMA engine, and the first scatter gather instruction pointed to by FIRST_QUAD_PTR_HI and FIRST_QUAD_PTR_LO is loaded. Version F.0 BitFlow, Inc. KBN-5-7...
  • Page 162 5.5 CON31 Register Name CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO CHAIN_DATA_TOGO KBN-5-8 BitFlow, Inc. Version F.0...
  • Page 163 Karbon/Neon DMA Registers CON31 Register CHAIN_DATA_ RO, CON31[31..0], Karbon, Neon TOGO This register indicates the number of bytes remaining the DMA chain. Version F.0 BitFlow, Inc. KBN-5-9...
  • Page 164 5.6 CON32 Register Name DMA_AUTO_START DMA_ABORT DMA_DIRECTION DMA_DONE DMA_STATUS DMA_STATUS DMA_STATUS DMA_STATUS DMA_NO_RULE Reserved Reserved Reserved Reserved Reserved Reserved Reserved DMA_INIT_FUNC DMA_PRIORITY DMA_64_BIT DMA_CHAINING DMA_COMMAND DMA_COMMAND DMA_COMMAND DMA_COMMAND DMA_BEN DMA_BEN DMA_BEN DMA_BEN LATCH_CONTROL LATCH_CONTROL Reserved Reserved KBN-5-10 BitFlow, Inc. Version F.0...
  • Page 165 Setting this bit to a 1 will cause the DMA engine to DMA data as fast as it can. It will not wait for data to be available from the acquisition engine. The actual data that is DMAed will be unpredictable. This bit, therefore, is only useful for diagnostics. Version F.0 BitFlow, Inc. KBN-5-11...
  • Page 166 DMA_CHAINING RW, CON32[19], Karbon, Neon This bit determines whether the DMA engine will execute chaining DMA or not. DMA_CHAINING Meaning DMA_ R/W, CON32[23..20], Karbon, Neon COMMAND DMA_BEN R/W, CON32[27..24], Karbon, Neon LATCH_ R/W, CON32[29..28 ], Karbon, Neon CONTROL KBN-5-12 BitFlow, Inc. Version F.0...
  • Page 167 5.7 CON33 Register Name XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT XFR_PER_INT Version F.0 BitFlow, Inc. KBN-5-13...
  • Page 168 CON33 Register The Karbon XFR_PER_INT R/W, CON33[31..0], Karbon, Neon This register controls how often the board issues an EOF interupt. Every time XFR_ PER_INT bytes have been DMAed, the board will emit an interrupt. KBN-5-14 BitFlow, Inc. Version F.0...
  • Page 169 Register and Memory Mapping Introduction Register and Memory Mapping Chapter 6 6.1 Introduction This section explains how the registers and the various chunks of memory are mapped and accessed on the Karbon-CL and its virtual frame grabbers. Version F.0 BitFlow, Inc. KBN-6-1...
  • Page 170 15 to 8. The VCTAB address is 17 bits, AD, i.e. 128K locations. The HCTAB address is 15 bits, AD. The CTAB can be accessed only as 64 bit wide, i.e. there is no provision for accessing less than 64 bits. KBN-6-2 BitFlow, Inc. Version F.0...
  • Page 171 CON28 CON29 CON30 CON31 CON32 CTABS ADD select 128K addresses ADD select 16K addresses for a 128K DPM UART 8 internal 8-bit registers on 64 bit boundary RO_INFOHI R/O info, model/rev, etc. RO_INFOLO R/O info Version F.0 BitFlow, Inc. KBN-6-3...
  • Page 172 ??? BAR0, memory mapped, 1M size, is used for access to QL5064 internal regis- ters. BAR1, memory mapped, 16M size, is used for access to R64 registers, CTABs, DPM. The Karbon uses address lines 23 to 3. Pre-fetch and posting WRITEs are disabled for both BARs KBN-6-4 BitFlow, Inc. Version F.0...
  • Page 173 There are only two FPGAs to download: MUX and DCC. The MUX is downloaded first. Different types of firmware types can be downloaded for different applications. The board has been designed to handle different size gate arrays if needed. Version F.0 BitFlow, Inc. KBN-6-5...
  • Page 174 PCI Configuration Space and Model/Revision Information The Karbon 6.5 PCI Configuration Space and Model/Revision Information All Karbon boards will have the same device ID. Information about different models and board capabilities will be stored in the INFO_HI and INFO_LO registers. KBN-6-6 BitFlow, Inc. Version F.0...
  • Page 175 A list of instructions are called a Quad Table or QTAB. Each quad consists of the following entries. 1. Destination address 2. Size of transfer 3. Next quad address. The following sections document the structure of these quads. Version F.0 BitFlow, Inc. KBN-6-7...
  • Page 176 Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address Destination Address KBN-6-8 BitFlow, Inc. Version F.0...
  • Page 177 Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Data Size Version F.0 BitFlow, Inc. KBN-6-9...
  • Page 178 Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address Next Quad Address KBN-6-10 BitFlow, Inc. Version F.0...
  • Page 179 This chapter describes the electrical interface of the Karbon/Neon/R64. This includes detailed information on the all if the input and output signals. In addition, information is provided on recommend circuits to use when connecting to these signals. Version F.0 BitFlow, Inc. KBN-7-1...
  • Page 180 The LED is driven by an open collector driver. The user must supply his +5V power to the LED. Note that there is no galvanic connection between the user’s circuit and the acquisition circuitry. KBN-7-2 BitFlow, Inc. Version F.0...
  • Page 181 T RIG G ER_O PT O O pt o -C o upl er PC 3H 711 740 7 T RIG G ER_O PT O _K P3-Pin 4 U ser C ir c uit Figure 7-1 Driver Circuit for Opto-Coupled Trigger Version F.0 BitFlow, Inc. KBN-7-3...
  • Page 182 The LED is driven by an open collector driver. The user must supply his +5V power to the LED. Note that there is no galvanic connection between the user’s circuit and the acquisition circuitry. KBN-7-4 BitFlow, Inc. Version F.0...
  • Page 183 Electrical Interfacing Encoder ENCODER_OPTO_A P3-Pin 11 3.3K ENCODER_OPTO Opto-Coupler PC3H711 7407 ENCODER_OPTO_K P3-Pin 10 User Circuit Figure 7-2 Driver Circuit for Opto-Coupled Encoder Version F.0 BitFlow, Inc. KBN-7-5...
  • Page 184 There are five general purpose inputs. The signal level on each input can be read on the corresponding GPIN bit. The electrical characteristic of these inputs is shown in the following list. GPIN0, GPIN1 - Single ended TTL level inputs GPIN2, GPIN3, GPIN4 - Differential (LVDS) inputs KBN-7-6 BitFlow, Inc. Version F.0...
  • Page 185 GPOUT6 driver circuits and their associated jumpers for various configurations. ???[how to handle difference between boards?] The board is shipped in with JP2 in position 1-2, JP4 in position 1-2, no jumpers in JP1 and JP3. Version F.0 BitFlow, Inc. KBN-7-7...
  • Page 186 General Purpose Outputs (GPOUT) The Karbon +12V GPOUT5_VCC (P3-Pin 32) 7407 GPOUT5_OC (P3-Pin 31) GPOUT5 +12V GPOU6_VCC (P3-Pin 42) 7407 GPOUT6_OC (P3-Pin 33) GPOUT6 Figure 7-3 Driver Circuits for GPOUT5 and GPOUT6 (in Default Configuration) KBN-7-8 BitFlow, Inc. Version F.0...
  • Page 187 The open collector driver will sink the current from the LED. There is no gal- vanic connection between the board and the user’s circuit. Information is passed from the board to the user as light, transmitted by the LED and received by the photo-tran- sistor. Version F.0 BitFlow, Inc. KBN-7-9...
  • Page 188 General Purpose Outputs (GPOUT) The Karbon +12V GPOUT5_VCC P3-Pin 32 Opto-Coupler 7407 GPOUT5_OC GPOUT5 P3-Pin 31 User Circuit Figure 7-5 GPOUT5 Driving Opto-Coupled Circuit using Galvanic Isolation KBN-7-10 BitFlow, Inc. Version F.0...
  • Page 189 3 (011b) Free running on board signal generator. Controlled by FREE_RUN_RATE and FREE_ RUN_HIGH 4 (100b) Internally generated clock. Frequency set by CFREQ. 5 (101b) GPIN0’s signal level 6 (110b) Forced low 7 (111b) Forced high Version F.0 BitFlow, Inc. KBN-7-11...
  • Page 190 Camera Link Controls (CCs) The Karbon KBN-7-12 BitFlow, Inc. Version F.0...
  • Page 191 Section 8.4 Temperature range 0 to 50 Degrees Celsius Humidity 25% to 80% Mechanical dimensions 6.8 x 4.2 Inches Mechanical dimensions 17.27 x 10.67 Centimeters Minimum UART baud rate Bits/Second Maximum UART baud rate 256K Bits/Second Version F.0 BitFlow, Inc. KBN-8-1...
  • Page 192 A two tap camera that supplies odd/even pixels, Max_pix_per_line = 512K. An RGB camera that supplies RGB over 24 bits, Max_pix_per_line = 256K, as every clock the camera supplies one single pixel. A four tap, two segments, each left right, Max_pix_per_line = 1M KBN-8-2 BitFlow, Inc. Version F.0...
  • Page 193 Line_taps is the number of taps that supply a whole line. Examples: A one tap camera, Max_lines_per_frame = 128K. A two tap camera that supplies odd/even lines, Max_lines_per_frame = 256K. A two tap camera that supplies odd/even pixels, Max_lines_per_frame = 128K. Version F.0 BitFlow, Inc. KBN-8-3...
  • Page 194 Power Consumption The Karbon 8.4 Power Consumption ???? KBN-8-4 BitFlow, Inc. Version F.0...
  • Page 195 PC and can be located in any slot that is not used. The mechanical layout of the Karbon-CL main board is shown in Figure 9-1. The mechanical layout of the Karbon-CL auxiliary board is shown in Figure 9-2.
  • Page 196 Introduction The Karbon Jumper Set 3 Figure 9-2 Karbon Auxiliary Board Layout KBN-9-2 BitFlow, Inc. Version F.0...
  • Page 197 Mechanical The Karbon-CL Connectors 9.2 The Karbon-CL Connectors There are six connectors on the Karbon-CL main board: CL1 - Camera Link Connector 1 CL2 - Camera Link Connector 2 P1 - Auxiliary Connector 1 P2 - Auxiliary Connector 2 P3 - Auxiliary Connector 3 P11 - The I/O connector Figure 9-1 shows the locations of these connectors.
  • Page 198 The Karbon-CL Connectors The Karbon Table 9-1 CL Connector Configuration Camera(s) One Medium Camera Camera 1, Camera 1, Connector 1 Connector 2 VFG0 VFG0 Two Medium Cameras Camera 1, Camera 1, Camera 2, Camera 2, Connector 1 Connector 2 Connector 1...
  • Page 199 The Jumpers and Switches 9.3 The Jumpers and Switches On the Karbon-CL main board there are four jumper fields that are user configurable, JP2, JP3, JP4 and JP5 and two that are not, JP10 and JP11. Figure 9-3 shows the loca- tions of these jumpers and switches.
  • Page 200 JP1 aux Cameras Medium Configu- ration Cameras JP11 main, Full Configuration Dual Base and JP2 aux Cameras Medium Configu- ration Cameras Note: Users should not change the factory setting of JP1,. JP2, JP10 and JP11. KBN-9-6 BitFlow, Inc. Version F.0...
  • Page 201 Switches 9.4 Switches There is one piano-type switch block on the Karbon-CL with two switches. These are used to identify individual boards when there is more than one board in a system. The idea is to set the switches differently on each board in the system. The switch settings can be read for each board from software (by reading the SW bitfield).
  • Page 202 It is important to understand that some of these signals are the output of a high speed serial converter chip, and require special instrumentation to be observed. KBN-9-8 BitFlow, Inc. Version F.0...
  • Page 203 Cathode of optocoupling sensor VFG0_ENCODER_OPTO_A Anode of optocoupling sensor VFG0_GPIN0_TTL VFG0_GPIN1_TTL VFG0_GPIN2+ LVDS VFG0_GPIN2- LVDS VFG0_GPIN3+ LVDS VFG0_GPIN3- LVDS VFG0_GPIN4+ LVDS VFG0_GPIN4- LVDS VFG0_GPOUT0+ LVDS VFG0_GPOUT0- LVDS VFG0_GPOUT1+ LVDS VFG0_GPOUT1- LVDS VFG0_GPOUT2+ LVDS VFG0_GPOUT2- LVDS VFG0_GPOUT3_TTL Version F.0 BitFlow, Inc. KBN-9-9...
  • Page 204 RS232 receive line VFG1_TRIGGER+ LVDS VFG1_TRIGGER- LVDS VFG1_TRIGGER_TTL VFG1_ENCODER+ LVDS VFG1_ENCODER- LVDS VFG1_ENCODER_TTL VFG2_TRIGGER+ LVDS VFG2_TRIGGER- LVDS VFG2_TRIGGER_TTL VFG2_ENCODER+ LVDS VFG2_ENCODER- LVDS VFG2_ENCODER_TTL VFG3_TRIGGER+ LVDS VFG3_TRIGGER- LVDS VFG3_TRIGGER_TTL VFG3_ENCODER+ LVDS VFG3_ENCODER- LVDS VFG3_ENCODER_TTL Reserverd Reserved KBN-9-10 BitFlow, Inc. Version F.0...
  • Page 205 CHAIN_DATA_TOGO KBN-5-9 DELAY KBN-4-62 CL_DISABLE KBN-4-28 DELAY_TAP1 KBN-4-83 CLAST_ADD KBN-4-57 DELAY_TAP1_SEL KBN-4-83 CLIP KBN-4-48 DISPLAY KBN-4-47 CMDWRITE KBN-4-20 DLAST_ADD KBN-4-57 CON0 KBN-4-4 DMA_64_BIT KBN-5-12 CON1 KBN-4-8 DMA_AUTO_START KBN-5-11 CON10 KBN-4-50 DMA_BEN KBN-5-12 CON11 KBN-4-54 DMA_BUSY KBN-4-29 CON12 KBN-4-56 BitFlow, Inc.
  • Page 206 FORCE_8BIT KBN-4-53 INT_OVSTEP KBN-4-12 FORMAT KBN-4-51 INT_QUAD KBN-4-13 FREE_RUN_HI KBN-4-65 INT_SER KBN-4-13 FREE_RUN_RATE KBN-4-65 INT_TRIG KBN-4-13 FREEZE_CON KBN-4-11 INT_TRIGCON KBN-4-14 FW_7MHZ KBN-4-5 FW_SEL KBN-4-7 FW_TYPE KBN-4-47 Jumpers KBN-9-5 GEN_ONESHOT KBN-4-40 L_CLKCON0 KBN-4-6 General Purpose Inputs (GPIN) KBN-7-6 LAL KBN-4-38 BitFlow, Inc.
  • Page 207 SW_ENC KBN-4-33 POCL_DETECTED KBN-4-92 SW_RESET KBN-4-61 POCL_EN KBN-4-5 SW_TRIG KBN-4-32 POCL_EN_POWER KBN-4-91 SWAP KBN-4-62 POCL_GND_ON KBN-4-91 Switches KBN-9-7 POCL_SENSE KBN-4-91 POP_TOSS KBN-4-29 PUMP_OFF KBN-4-29 TAG_BANK KBN-4-40 TOP_REV KBN-4-67 Trigger KBN-7-2 QTBSRC KBN-4-20 TRIGGER_DELAY KBN-4-34 TRIGPOL KBN-4-32 TRIM KBN-4-47 BitFlow, Inc.
  • Page 208 Index UART_CON KBN-4-63 UART_MASTER KBN-4-55 VAW_START KBN-4-30 VCNT_LD KBN-4-10 VCNT_RLS_STK KBN-4-10 VCNT_RLS_ZERO KBN-4-9 VCNT_RST KBN-4-9 VCOUNT KBN-4-38 VFG KBN-1-1 VID_BRL KBN-4-71 VID_SOURCE KBN-4-52 VIDEO_2DPM KBN-4-71 VIDEO_MASK KBN-4-59 WO KBN-4-3 XFR_PER_INT KBN-5-14 BitFlow, Inc.

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