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ARM Musca-S1 Technical Reference Manual

Test chip and board
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Musca-S1 Test Chip and Board
®
Technical Reference Manual
Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved.
101835_0000_01_en

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Summary of Contents for ARM Musca-S1

  • Page 1 Musca-S1 Test Chip and Board ® Technical Reference Manual Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved. 101835_0000_01_en...
  • Page 2 Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company.
  • Page 3 This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.

  • Page 4: Table Of Contents

    About this book ......................7 Feedback ........................10 Chapter 1 Introduction Precautions ......................1-12 About the Musca-S1 test chip and board ..............1-13 The Musca-S1 development board at a glance ............1-14 Getting started ......................1-16 Chapter 2 Hardware description Board hardware ...........
  • Page 5 PVT sensors ....................Appx-C-187 Appendix D IP configuration IP configuration .................... Appx-D-190 Appendix E Specifications Electrical specifications ................Appx-E-192 Appendix F Revisions Revisions ....................Appx-F-194 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 6 This preface introduces the Arm Musca-S1 Test Chip and Board Technical Reference Manual. ® It contains the following: • About this book on page • Feedback on page 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved. Non-Confidential...

  • Page 7: About This Book

    Glossary is a list of terms used in Arm documentation, together with definitions for those ® terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning. See the Glossary for more information.
  • Page 8 At the start or end of a signal name, n denotes an active-LOW signal. Additional reading This book contains information that is specific to this product. See the following documents for other relevant information. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved. Non-Confidential...
  • Page 9 ‑ M Architecture Reference Manual (Arm DDI 0553) ® • AMBA 5 AHB Protocol Specification (Arm IHI 0033). ® ® • AMBA APB Protocol Specification Version 2.0 (Arm IHI 0024). ® ® 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights reserved. Non-Confidential...

  • Page 10: Feedback

    A concise explanation of your comments. Arm also welcomes general suggestions for additions and improvements. Note Arm tests the PDF only in Adobe Acrobat and Acrobat Reader, and cannot guarantee the quality of the represented document when used with any other PDF reader. 101835_0000_01_en Copyright ©...
  • Page 11 This chapter introduces the Musca‑S1 test chip and Musca‑S1 development board. It contains the following sections: • 1.1 Precautions on page 1-12. • 1.2 About the Musca-S1 test chip and board on page 1-13. • 1.3 The Musca ‑ S1 development board at a glance on page 1-14.

  • Page 12: Chapter 1 Introduction

    Avoid touching the component pins or any other metallic element. • Do not fit an Arduino Expansion Shield while the Musca‑S1 development board is powered up. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 1-12 reserved. Non-Confidential...

  • Page 13: About The Musca-S1 Test Chip And Board

    Depleted Silicon on Insulator process (28FDS). The implementation is ready to be used to form the core processing element of energy-efficiency mainstream IoT devices with secure PSA Root-of-Trust (RoT). Musca-S1 can also be used to prototype secure boot, on-chip storage execution and network device management through Trusted Firmware-M (TF-M), Arm Mbed...

  • Page 14: The Musca-S1 Development Board At A Glance

    Samsung Foundry 28FDS eMRAM-enabled Internet of Things (IoT) test chip. Boot selector slider switch eMRAM or QSPI Expansion Shield analog I/O connector 1V8 or 3V3 I/O. Selected by jumper link J12. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 1-14 reserved. Non-Confidential...
  • Page 15 1 (17). Next to PWR LED. CoreSight debug connector SWJ-DP USB mini B connector Expansion Shield digital I/O connector Jumper J12 selects 1V8 or 3V3. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 1-15 reserved. Non-Confidential...

  • Page 16: Getting Started

    8N1. • No hardware or software flow control. To load a new user image, drag and drop the new image onto the drive labeled MUSCA_S. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 1-16 reserved. Non-Confidential...
  • Page 17 2.10 Arduino Expansion Shield interface on page 2-38. • 2.11 Boot memory on page 2-40. • 2.12 DAPLink controller on page 2-41. • 2.13 Debug on page 2-42. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-17 reserved. Non-Confidential...

  • Page 18: Board Hardware

    — 4 × 128KB SRAM. One 128KB bank, SRAM3, functions as Tightly ‑ Coupled Memory (TCM), Tightly‑Coupled to CPU1 and operates at CPU1 clock speed. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-18 reserved. Non-Confidential...
  • Page 19 — DAPLink 5V USB connector. — CLN 523450, Lithium Ion, 3.7V, 950mAh (not supplied). Related information 1.3 The Musca ‑ S1 development board at a glance on page 1-14 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-19 reserved. Non-Confidential...

  • Page 20: Musca-S1 Test Chip

    ‑ 200 Subsystem for Embedded Technical Reference Manual (r1p0) for more ® ™ information on the SSE-200 subsystem: The following figure shows a high-level view of the architecture of the Musca‑S1 test chip. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-20 reserved. Non-Confidential...
  • Page 21 1MB GPIO multiplexer 512KB Code SRAM 3 eMRAM 1MB 512KB DAPLink Gyro, ADC/DAC Arduino QSPI controller Temperature sensor Shield memory Figure 2-2 Musca-S1 test chip 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-21 reserved. Non-Confidential...
  • Page 22 ® — One secure watchdog in the S32KCLK domain. — One secure watchdog in the SYSCLK domain. — One Non‑secure watchdog in the SYSCLK domain. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-22 reserved. Non-Confidential...
  • Page 23 3.11.1 IOMUX registers on page 3-122 for information on the Musca‑S1 test chip I/O multiplexer and the IOMUX registers. Note The IOMUX registers select each Musca‑S1 test chip I/O individually. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-23 reserved. Non-Confidential...
  • Page 24 Reserved GPIO[11] Boot selector slider switch Note MT stands for Master Transmitter. MR stands for Master Receiver. Related information 3.11.1 IOMUX registers on page 3-122 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-24 reserved. Non-Confidential...

  • Page 25: Software, Firmware, Board, And Tools Setup

    To power the board, connect the USB port to your computer and press the PBON user push button. The DAPLink interface appears in the Windows device manager as an Arm Mbed composite device, part of which is the Mbed serial port, UART. The following figure shows an example configuration that contains the Mbed composite device and the Mbed serial port.
  • Page 26 2 Hardware description 2.3 Software, firmware, board, and tools setup Note The file is available at the Arm Community pages which are accessible from https:// blinky.bin www.arm.com/musca. DAPLink UART setting The default DAPLink UART setting is 115,200 baud (8N1). Related information 1.3 The Musca...

  • Page 27: User Components And Status Leds

    ‑ S1 development board at a glance on page 1-14 2.2.2 Test chip multiplexed I/O on page 2-23 3.11 Serial Configuration Control registers on page 3-122 2.7 Resets and powerup on page 2-33 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-27 reserved. Non-Confidential...

  • Page 28: Clocks

    The driver clock goes to an on-chip PLL and divider system. The on-chip system multiplies the clock frequency to drive the Cortex‑M33 processors, the SSE‑200 subsystem, and other blocks. The following figure shows the Musca‑S1 test chip and board clock system. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-28 reserved. Non-Confidential...
  • Page 29 The SCC registers control the clock system. See 3.11 Serial Configuration Control registers on page 3-122. The following table shows the SCC clock control registers. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-29 reserved. Non-Confidential...
  • Page 30 TEST_CLK is present on Musca‑S1 test chip I/O PA13 which is also part of the multiplexed Musca‑S1 test chip I/O. The IOMUX registers select TEST_CLK by selecting alternative function ALTF2 for Musca‑S1 test chip I/O PA13. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-30 reserved. Non-Confidential...
  • Page 31 3.11.1 IOMUX registers on page 3-122. Related information 3.11.2 SCC registers summary on page 3-125 2.2.2 Test chip multiplexed I/O on page 2-23 3.11.1 IOMUX registers on page 3-122 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-31 reserved. Non-Confidential...

  • Page 32: Cryptocell -312 And One Time Programmable Security System

    CryptoCell -312 and One Time Programmable security system ™ The Musca‑S1 test chip implements an Arm CryptoCell‑312 (r1p0) security subsystem and emulates One Time Programming (OTP) secure memory. CryptoCell-312, in the SSE-200 subsystem, is a cryptographic module that provides fundamental security services to the Cortex‑M33 processors and protects them against unauthorized access.

  • Page 33: Resets And Powerup

    PSUs ON CFG_nRST CB_nRST CS_nSRST Figure 2-5 Musca-S1 test chip and board reset and configuration timing Related information 1.3 The Musca ‑ S1 development board at a glance on page 1-14 2.4 User components and status LEDs on page 2-27 101835_0000_01_en Copyright ©...

  • Page 34: Power

    Figure 2-6 Musca-S1 development board power supplies Caution Do not fit an Arduino Expansion Shield to the Musca‑S1 development board while the Musca‑S1 development board is powered up. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-34 reserved. Non-Confidential...
  • Page 35 A backup battery can power the Musca‑S1 development board, using the connector on the lower face of the board. Arm recommends using the Lithium Ion, CLN 523450, 3.7V, 950mAh battery. The battery is recharged from an external supply during USB 5V operation. If a battery is fitted while external power is connected, circuitry on the board automatically charges the battery with a maximum charging current of 500mA.
  • Page 36 Related information 1.3 The Musca ‑ S1 development board at a glance on page 1-14 A.3 USB connector on page Appx-A-182 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-36 reserved. Non-Confidential...

  • Page 37: I 2 C Interfaces And Sensors

    2.2.2 Test chip multiplexed I/O on page 2-23. • 3.11.1 IOMUX registers on page 3-122. Related information 1.3 The Musca ‑ S1 development board at a glance on page 1-14 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-37 reserved. Non-Confidential...

  • Page 38: Arduino Expansion Shield Interface

    VIN connects to the 5V source through a reverse protection diode. The 5V power source is selectable between USB or battery using jumper link J19. • Reset. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-38 reserved. Non-Confidential...
  • Page 39 3.11.1 IOMUX registers on page 3-122. Related information 1.3 The Musca ‑ S1 development board at a glance on page 1-14 A.1 Arduino Expansion Shield connectors on page Appx-A-178 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-39 reserved. Non-Confidential...

  • Page 40: Boot Memory

    Musca‑S1 test chip I/O pins: • 2.2.2 Test chip multiplexed I/O on page 2-23. • 3.11.1 IOMUX registers on page 3-122. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-40 reserved. Non-Confidential...

  • Page 41: Daplink Controller

    2.12 DAPLink controller The DAPLink controller is an Arm Mbed component that uses a Cortex‑M0 processor. The DAPLink controller contains pre-defined firmware that enables access to the CoreSight component in Musca‑S1 test chip, USB Mass Storage Device (USBMSD), USB UART, and remote reset.

  • Page 42: Debug

    Serial Wire or JTAG processor debug (SWJ - DP), available over USB DAPLink: Related information 1.3 The Musca ‑ S1 development board at a glance on page 1-14 A.2 Debug connector on page Appx-A-181 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 2-42 reserved. Non-Confidential...
  • Page 43 3.11 Serial Configuration Control registers on page 3-122. • 3.12 UART control registers on page 3-171. • 3.13 GPIO control registers on page 3-174. • 3.14 Third-party IP on page 3-176. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-43 reserved. Non-Confidential...

  • Page 44: About This Programmers Model

    — All register bits are reset to a logic 0 by a system or powerup reset. — All register summary tables in this chapter describe register access types as follows: Read/write. Read-only. Write-only. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-44 reserved. Non-Confidential...

  • Page 45: Memory Maps

    SSE-200 system memory map. The following figure shows the Musca‑S1 test chip implementation of the code, AHB5 expansion, and SRAM regions of the SSE-200 system memory map. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-45 reserved. Non-Confidential...
  • Page 46 Reserved 0x0220_0000 External QSPI Flash (NS) 0x0020_0000 Code SRAM (NS) 0x0000_0000 Musca-S1 memory maps Figure 3-1 Musca-S1 test chip memory map code and SRAM regions 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-46 reserved. Non-Confidential...
  • Page 47 CMSDK Timer 1 (NS) 0x4000_1000 0x0000_0000 CMSDK Timer 0 (NS) 0x4000_0000 SSE-200 system memory map Musca-S1 memory map Figure 3-2 Musca-S1 test chip memory map Peripheral region 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-47 reserved. Non-Confidential...
  • Page 48 0x0000_0000 Reserved 0x4010_0000 Expansion 1 region (Non-secure) SSE-200 system memory map Musca-S1 memory map Figure 3-3 Musca-S1 test chip memory map Non-secure Expansion 1 region 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-48 reserved. Non-Confidential...
  • Page 49 Reserved 0x0000_0000 0x5010_0000 Expansion 1 region (Secure) SSE-200 system memory map Musca-S1 memory map Figure 3-4 Musca-S1 test chip memory map Secure Expansion 1 region 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-49 reserved. Non-Confidential...
  • Page 50 AHB5 expansion 0 0x6000_0000 Peripheral (expansion) 0x4000_0000 SRAM 0x2000_0000 Code (AHB5 expansion) 0x0000_0000 SSE-200 system memory map Figure 3-5 Musca-S1 test chip memory map System region 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-50 reserved. Non-Confidential...
  • Page 51 Secure privilege control Non‑secure privilege control 0x4008_1000 0x4008_1FFF 0x5008_1000 0x5008_1FFF 4KB Non-secure CMSDK Secure CMSDK Watchdog Watchdog Timer Timer 0x5008_3000 0x5008_3FFF 4KB SRAM 0 Memory Protection Controller 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-51 reserved. Non-Confidential...
  • Page 52 Protection Controller (MPC) (MPC) 0x4014_0000 0x4014_0FFF 0x5014_0000 0x5014_0FFF 4KB eMRAM MPC eMRAM MPC 0xF000_0000 0xF000_0FFF 4KB Debug system ROM 0xF000_1000 0xF000_1FFF 4KB Debug element funnel 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-52 reserved. Non-Confidential...
  • Page 53 Non-secure Secure Description From From Size Non-secure Secure 0xF000_2000 0xF000_2FFF 4KB Debug element Cross Trigger Interface (CTI) 0xF008_0000 0xF00F_FFFF 512KB - Debug APB expansion region. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-53 reserved. Non-Confidential...

  • Page 54: Processor Elements

    0x0308 ICSUC 0x0000_0000 32 Instruction cache Statistic Uncached Count Register 0x0FD0 PIDR4 0x0000_0004 32 Product ID Register 4 0x0FE4 PIDR1 0x0000_00B8 32 Product ID Register 1 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-54 reserved. Non-Confidential...
  • Page 55 At the end of the invalidation process, the interrupt status, IC, is asserted. If that interrupt is already enabled, or is enabled later, an interrupt is raised. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-55 reserved.
  • Page 56 3.3.5 Interrupts The Musca‑S1 test chip implements an Arm Nested Vector Interrupt Controller (NVIC) and an Arm Wakeup Interrupt Controller (WIC). See the following documentation for more information on the interrupt controller.
  • Page 57 CPU1DBG_PPU IRQ[20] Reserved IRQ[21] Reserved IRQ[22] RAM0_PPU IRQ[23] RAM1_PPU IRQ[24] RAM2_PPU IRQ[25] RAM3_PPU IRQ[26] DBG_PPU IRQ[27] Reserved IRQ[28] CPU0CTIIRQ0, CPU1CTIIRQ0 IRQ[29] CPU0CTIIRQ1, CPU1CTIIRQ1 IRQ[31:30] Reserved 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-57 reserved. Non-Confidential...
  • Page 58 General‑purpose timer interrupt[1] (Comparator 1). IRQ[73] GPTIMERINT0 General‑purpose timer interrupt[0] (Comparator 0). IRQ[74] PWMINT1 PWM1 interrupt. IRQ[75] PWMINT2 PWM2 interrupt. IRQ[76] GPIO_COMB_NONSEC_INTR GPIO Non-secure interrupt. IRQ[95:77] Reserved 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-58 reserved. Non-Confidential...
  • Page 59 When the WIC is enabled and the processor is in deep‑sleep mode, the Power Management Unit (PMU) can power down most of the processor. When the WIC receives an interrupt, it takes several clock cycles 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-59 reserved.
  • Page 60 FCLK can be gated completely during WIC-based deep‑sleep. This complete gating is not a standard Cortex-M33 processor feature. See the Arm Cortex ‑ M33 Processor Technical Reference Manual (r0p2) for more information on the ® ® WIC. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-60 reserved. Non-Confidential...

  • Page 61: Base Element

    Secure region. 0x5000_0000 TIMER 1 registers are at the following base memory addresses: • in the Non‑secure region. 0x4000_1000 • in the Secure region. 0x5000_1000 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-61 reserved. Non-Confidential...
  • Page 62 Peripheral ID Register 0. Bits [7:0] Part number [7:0]. 0x0FE4 PID1 0x0000_00B8 32 Peripheral ID Register 1: Bits [7:4] jep106_id_3_0. Bits [3:0] Part number [11:8]. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-62 reserved. Non-Confidential...
  • Page 63 Bits [31:8] are reserved. 0x000C DTIMER1INTCLR Dual timer 1 interrupt clear register. 0x0010 DTIMER1RIS 0x0000_0000 32 Dual timer 1 raw interrupt status register. Bits [31:1] are reserved. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-63 reserved. Non-Confidential...
  • Page 64 Bits [31:8] are reserved. 0x0FF0 DTIMERPCELLID0 0x0000_000D 32 Component ID Register 0. Bits [31:8] are reserved. 0x0FF4 DTIMERPCELLID1 0x0000_00F0 32 Component ID Register 1. Bits [31:8] are reserved. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-64 reserved. Non-Confidential...
  • Page 65 Timer 1 control register. Bits [31:2] are reserved. 0x000C WDOGINTCLR Watchdog interrupt clear register. 0x0010 WDOGRIS 0x0000_0000 1 Watchdog interrupt status register. Bits [31:1] are reserved. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-65 reserved. Non-Confidential...
  • Page 66 Reads and writes are supported only from Secure Privileged access. See the Arm CoreLink ‑ 200 Subsystem for Embedded Technical Reference Manual (r1p0) for more ® ™ information. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-66 reserved. Non-Confidential...
  • Page 67 0x0000_0000 Bridge buffer error interrupt status register. (Bit[0]) BRGINTEN Register on page 3-75 for information on how this register is implemented in the Musca‑S1 test chip. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-67 reserved. Non-Confidential...
  • Page 68 0. This register controls the PPC within the Base element. See the Arm CoreLink ‑ 200 Subsystem for Embedded Technical ® ™ Reference Manual (r1p0) for more information. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-68 reserved. Non-Confidential...
  • Page 69 Memory offset and full register reset value 3.4.6 Secure Privilege Control Block on page 3-66. The following table shows the bit assignments of the SECMPCINTSTATUS Register. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-69 reserved. Non-Confidential...
  • Page 70 ™ for more information. Usage constraints This register is read-only. Memory offset and full register reset value 3.4.6 Secure Privilege Control Block on page 3-66. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-70 reserved. Non-Confidential...
  • Page 71 Memory offset and full register reset value 3.4.6 Secure Privilege Control Block on page 3-66. The following table shows the bit assignments of the SECPPCINTCLR Register. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-71 reserved. Non-Confidential...
  • Page 72 Controller for APB slaves within the base element. 0b0: No effect. 0b1: Clear interrupt. Reset value: 0b0. SECPPCINTEN Register The Secure Peripheral Protection Controller (PPC) Interrupt Enable Register characteristics are: 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-72 reserved. Non-Confidential...
  • Page 73 S_APBPPCMEM_EN Interrupt Enable of Peripheral Protection Controller for APB slaves within the memory subsystem: 0b0: Mask interrupt. 0b1: Enable interrupt. Reset value: 0b0. [3:2] Reserved. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-73 reserved. Non-Confidential...
  • Page 74 Clears the interrupts of the bridge between CPU1 and the system. See the Arm CoreLink ‑ 200 Subsystem for Embedded Technical Reference Manual (r1p0) ® ™ for more information. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-74 reserved. Non-Confidential...
  • Page 75 0b0: Disable (mask) interrupt. 0b1: Enable interrupt. Reset value 0b0. AHBNSPPCEXP0 Register The Expansion 0 Non-secure Access AHB slave Peripheral Protection Control Register characteristics are: 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-75 reserved. Non-Confidential...
  • Page 76 Memory offset and full register reset value 3.4.6 Secure Privilege Control Block on page 3-66. The following table shows the bit assignments of the APBNSPPCEXP0 Register. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-76 reserved. Non-Confidential...
  • Page 77 Memory offset and full register reset value 3.4.6 Secure Privilege Control Block on page 3-66. The following table shows the bit assignments of the APBNSPPCEXP1 Register. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-77 reserved. Non-Confidential...
  • Page 78 Reset value 0b0. NS_RTC Defines the security access setting for the Real Time Clock: 0b0: Secure access only. 0b1: Secure and Non‑secure access. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-78 reserved. Non-Confidential...
  • Page 79 0b1: Secure and Non‑secure access. Reset value 0b0. NS_UART0 Defines the security access setting for the UART0: 0b0: Secure access only. 0b1: Secure and Non‑secure access. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-79 reserved. Non-Confidential...
  • Page 80 Memory offset and full register reset value 3.4.6 Secure Privilege Control Block on page 3-66. The following table shows the bit assignments of the AHBSPPPCEXP0 Register. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-80 reserved. Non-Confidential...
  • Page 81 Defines the Secure Unprivileged access setting for the eMRAM Memory Protection Controller (MPC): 0b0: Secure Privileged access only. 0b1: Secure Unprivileged and Privileged access. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-81 reserved. Non-Confidential...
  • Page 82 The hardware bug in this register prevents it from enabling Unprivileged access, bit[n]= , for a peripheral. See B.1 S1 Secure and Non-secure privilege registers hardware bug on page Appx-B-184 the description of the workaround. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-82 reserved. Non-Confidential...
  • Page 83 S_PVT Defines the Secure access setting for the PVT sensor system: 0b0: Secure Privileged access only. 0b1: Secure Unprivileged and Privileged access. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-83 reserved. Non-Confidential...
  • Page 84 Reset value 0b0. S_SPI Defines the Secure access setting for the SPI: 0b0: Secure Privileged access only. 0b1: Secure Unprivileged and Privileged access. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-84 reserved. Non-Confidential...
  • Page 85 0x0000_0000 Non‑secure Unprivileged Access APB slave Peripheral Protection Control 1. See the Arm CoreLink ‑ 200 Subsystem for Embedded Technical ® ™ Reference Manual (r1p0) for more information. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-85 reserved. Non-Confidential...
  • Page 86 Memory offset and full register reset value 3.4.7 Non-secure Privilege Control Block on page 3-85. The following table shows the bit assignments of the AHBNSPPPCEXP0 Register. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-86 reserved. Non-Confidential...
  • Page 87 Defines the Non‑secure access settings for the eMRAM Memory Protection Controller (MPC): 0: Non‑secure Privileged access only. 1: Non‑secure Privileged and Unprivileged access. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-87 reserved. Non-Confidential...
  • Page 88 The hardware bug in this register prevents it from enabling Unprivileged access, bit[n]= , for a peripheral. See B.1 S1 Secure and Non-secure privilege registers hardware bug on page Appx-B-184 the description of the workaround. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-88 reserved. Non-Confidential...
  • Page 89 NS_PVT Defines the Non‑secure access setting for the PVT sensor system: 0: Non‑secure privileged access only. 1: Non‑secure Privileged and Unprivileged access. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-89 reserved. Non-Confidential...
  • Page 90 Reset value 0b0. NS_SPI Defines the Non‑secure access setting for the SPI: 0: Non‑secure privileged access only. 1: Non‑secure Privileged and Unprivileged access. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-90 reserved. Non-Confidential...
  • Page 91 0x0010 CPU1INTR_STAT RO 0x0000_0000 Core 1 interrupt status register. 0x0014 CPU1INTR_SET 0x0000_0000 Core 1 interrupt set register. 0x0018 CPU1INTR_CLR 0x0000_0000 Core 1 interrupt clear register. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-91 reserved. Non-Confidential...
  • Page 92 The following table shows the AHB5 TrustZone MPC registers in address offset order from the base memory address. Undefined registers are reserved. Software must not attempt to access these registers. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-92 reserved.
  • Page 93 A full word write or read to this register automatically increments the BLK_IDX by one if enabled by CTRL[8]. The upper bits are reserved if BLK_SIZE > ADDR_WIDTH - 11. 0x0020 INT_STAT 0x0000_0000 Bits[31:1]: Reserved. Bit[0]: mpc_irq triggered. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-93 reserved. Non-Confidential...
  • Page 94 0x0FE0 PIDR0 0x0000_0060 Peripheral ID 0. Bits [31:8]: Reserved Bits [7:0]. Part number [7:0]. 0x0FE4 PIDR1 0x0000_00B8 Peripheral ID 1. Bits[7:4] jep106_id_3_0. Bits[3:0] Part number[11:8]). 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-94 reserved. Non-Confidential...
  • Page 95 The AHB5 TrustZone MPC provides a configuration lockdown feature that prevents malicious software from changing the security configuration. Writing to the security lockdown bit, CTRL[31], enables the configuration lockdown feature. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-95 reserved. Non-Confidential...
  • Page 96 LUT autoincrement bit, CTRL[8], before enabling the configuration lockdown feature. When the feature is enabled, only LUT reading is available which is simpler when BLK_IDX increments automatically during the read sequence. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-96 reserved. Non-Confidential...

  • Page 97: System Control Element

    SRAM Bank 2 Power Policy Unit (PPU) 0x5002_D000 0x5002_DFFF 4KB RAM3_PPU SRAM Bank 3 system Power Policy Unit (PPU) This region is RZZ/WI. This region is RAZ/WI. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-97 reserved. Non-Confidential...
  • Page 98 PIDR3 0xFF0 0x0000_000D Component ID 0 CIDR0 0xFF4 0x0000_00F0 Component ID 1 CIDR1 0xFF8 0x0000_0005 Component ID 2 CIDR2 0xFFC 0x0000_00B1 Component ID 3 CIDR3 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-98 reserved. Non-Confidential...
  • Page 99 PD_SYS power domain sensitivity. 0x020C PDCM_PD_SRAM0_SENSE RW 0x0000_0000 Power Control Dependency Matrix. PD_SRAM0 power domain sensitivity. 0x0210 PDCM_PD_SRAM1_SENSE RW 0x0000_0000 Power Control Dependency Matrix. PD_SRAM1 power domain sensitivity. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-99 reserved. Non-Confidential...
  • Page 100 Function [31:21] - Reserved. [20:16] FCLKDIV_CUR Current value of FCLKDIV: The division value of FCLKDIV divider is FCLKDIV_CUR+1. These bits are read-only. Reset value 0b00000. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-100 reserved. Non-Confidential...
  • Page 101 The base memory addresses of the control registers of the CMSDK timer in the system control element are: • in the Non‑secure region. 0x4002_F000 • in the Secure region. 0x5002_F000 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-101 reserved. Non-Confidential...
  • Page 102 CMSDK timer control registers. See Arm Cortex ‑ M System Design Kit Technical Reference Manual for full descriptions of the CMSDK ® ® timer control registers. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-102 reserved. Non-Confidential...

  • Page 103: Subsystem Debug System

    CPU0 AHB-AP is for CPU0, primary core, debug access and also for certification access. It also maps a CoreSight ROM and a Granular Power Requester (GPR). The values of CERTDISABLE, CERTDISABLED, CERTREADEN, and CERTREADENABLED control the accessibility of the certification access path. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-103 reserved. Non-Confidential...
  • Page 104 CPU1 Access CoreSight ROM. 0xF000_9000 0xF000_9FFF 4KB CPU1GPR CPU1 Granular Power Requester (GPR). 0xF000_A000 0xFFFF_FFFF - System memory access by the CPU1 Debug Access Port. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-104 reserved. Non-Confidential...
  • Page 105 The PID values are dependent on the TARGETIDSYS[31:0] static configuration signal value. This is set by default. See Arm CoreLink ‑ 200 Subsystem for Embedded Technical Reference 0x0743_0477 ® ™ Manual (r1p0). 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-105 reserved. Non-Confidential...
  • Page 106 PIDR2[7:4]: Revision code. 0xFF0 CIDR0 0x0000_000D Component ID 0. 0xFF4 CIDR1 0x0000_0010 Component ID 1. 0xFF8 CIDR2 0x0000_0005 Component ID 2. 0xFFC CIDR3 0x0000_00B1 Component ID 3. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-106 reserved. Non-Confidential...

  • Page 107: Real Time Clock

    3 Programmers model 3.7 Real Time Clock Real Time Clock The Musca‑S1 test chip implements an Arm PrimeCell Real Time Clock. The base memory addresses of the Real Time Clock (RTC) control registers are: • 0x4010_8000 in the Non-secure region.

  • Page 108: General-Purpose Timer

    A write resets the general‑purpose timer counter to 1. • A read returns the current value of the general‑purpose timer counter. Usage constraints There are no usage constraints. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-108 reserved. Non-Confidential...
  • Page 109 Writing 1 to the relevant bit clears the ALARM0 or ALARM1 interrupt. • Reading a bit returns the current value of the bit. Usage constraints There are no usage constraints. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-109 reserved. Non-Confidential...
  • Page 110 There are no usage constraints. Memory offset and full register reset value 3.8 General-purpose timer on page 3-108. The following table shows the bit assignments of the GPTALARM1 Register. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-110 reserved. Non-Confidential...
  • Page 111 This register is read-only. Memory offset and full register reset value 3.8 General-purpose timer on page 3-108. The following table shows the bit assignments of the GPTCOUNTER Register. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-111 reserved. Non-Confidential...
  • Page 112 3 Programmers model 3.8 General-purpose timer Table 3-50 GPTCOUNTER Register bit assignments Bits Name Function [31:0] GPTCOUNTER Current value of 32-bit timer counter. Reset value 0000_0000. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-112 reserved. Non-Confidential...

  • Page 113: Pvt Sensor Registers

    SENSOR2_VAL Register on page 3-120. CTRL_REF_COUNTER Register The CTRL_REF_COUNTER Register characteristics are: Purpose Controls the PVT sensors reference counter. Usage constraints There are no usage constraints. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-113 reserved. Non-Confidential...
  • Page 114 Select operating mode of PVT sensors: 0b0: One-shot mode. 0b1: Repeat mode: Reset value 0b0. CTR_CNTR_EN Enable reference counter: 0b0: Not enabled. 0b1: Enabled: Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-114 reserved. Non-Confidential...
  • Page 115 0b0: Not enabled. 0b1: Enabled. Reset value 0x1FF. CTRL_CLKSEL Register The CTRL_CLKSEL Register characteristics are: Purpose Individually selects the nine PVT sensors input clocks. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-115 reserved. Non-Confidential...
  • Page 116 Memory offset and full register reset value 3.9.1 PVT sensor control registers summary on page 3-113. The following table shows the CTRL_PERIOD Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-116 reserved. Non-Confidential...
  • Page 117 This register is read-only. Memory offset and full register reset value 3.9.1 PVT sensor control registers summary on page 3-113. The following table shows the INTR_STATUS bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-117 reserved. Non-Confidential...
  • Page 118 Memory offset and full register reset value 3.9.1 PVT sensor control registers summary on page 3-113. The following table shows the SAMPLED_STATUS Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-118 reserved. Non-Confidential...
  • Page 119 Table 3-63 SENSOR0_VAL Register bit assignments Bits Name Function [31:0] SENSOR0_VAL Value measured by PVT sensor 0. Reset value 0x0000_0000. SENSOR1_VAL Register The SENSOR1_VAL Register characteristics are: 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-119 reserved. Non-Confidential...
  • Page 120 The following table shows the SENSOR2_VAL Register bit assignments. Table 3-65 SENSOR2_VAL Register bit assignments Bits Name Function [31:0] SENSOR2_VAL Value measured by PVT sensor 2. Reset value 0x0000_0000. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-120 reserved. Non-Confidential...

  • Page 121: Cryptocell -312 And One-Time Programmable (Otp) Secure Memory Locations

    -312 and One-Time Programmable (OTP) secure memory ™ locations The Musca‑S1 test chip implements an Arm CryptoCell‑312 (r1p0) security subsystem and emulates 1KB of One Time Programming (OTP) secure memory. 2.6 CryptoCell -312 and One Time Programmable security system on page 2-32 for more ™...

  • Page 122: Serial Configuration Control Registers

    The IOMUX registers, which are a subset of the SCC register bank, control the multiplexer logic that drives Musca‑S1 test chip I/O pins PA26-PA0. The multiplexer controlsMusca‑S1 test chip I/O PA26-PA0. The following figure shows the multiplexer logic. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-122 reserved. Non-Confidential...
  • Page 123 SCC base memory address of in the Non-secure region, or 0x4010_C000 in the Secure region. 0x5010_C000 Note 3.11.2 SCC registers summary on page 3-125 for the read/write access characteristics. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-123 reserved. Non-Confidential...
  • Page 124 0x08A8 IOMUX_ALTF2_INSEL IOMUX_ALTF2_INSEL Register Controls the Musca‑S1 test chip I/O PA31- on page 3-153 PA0. Routes connection from ALTF1 input multiplexers to either ALTF2_IN or ALTF3_IN. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-124 reserved. Non-Confidential...
  • Page 125 0x0000_7FFF 32 CLK_POSTDIV_CTRL_RTC Register on page 3-132. 0x081C CLK_POSTDIV_TEST 0x0000_000A 32 CLK_POSTDIV_CTRL_TEST Register on page 3-132. 0x0820 CTRL_BYPASS_DIV 0x0000_0001 32 CTRL_BYPASS_DIV Register on page 3-133 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-125 reserved. Non-Confidential...
  • Page 126 IOMUX_ALTF2_INSEL Register on page 3-153 3.11.1 IOMUX registers on page 3-122. 0x08B0 IOMUX_ALTF2_OUTSEL 0xFFFF_FFFF 32 IOMUX_ALTF2_OUTSEL Register on page 3-154 3.11.1 IOMUX registers on page 3-122. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-126 reserved. Non-Confidential...
  • Page 127 0x0000_0000 32 SPARE_CTRL1 Register on page 3-169. 0x0C00 CHIP_ID 0x0799_0477 32 CHIP_ID Register on page 3-169. 0x0C04 IO_IN_STATUS 0x05FF_FFE3 32 IO_IN_STATUS Register on page 3-170. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-127 reserved. Non-Confidential...
  • Page 128 Table 3-68 CLK_CTRL_SEL Register bit assignments Bits Name Function [31:13] - Reserved. [12] CTRL_PLL_MUX_CLK_SEL Select PLL MUX input: 0b0: PLL0 0b1: Not used Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-128 reserved. Non-Confidential...
  • Page 129 Reset value 0b00000. SEL_RM38P4_PREMUX_CLK Select RM38KPREMUX input: 0b0: SYSSYSSUGCLK. 0b1: NRM138P4 (not used). Reset value 0b1. SEL_SCCMUX_CLK Select SCCMUX input: 0b0: SCCCLK. 0b1: PRE_MUX_CLK. Reset value 0b1. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-129 reserved. Non-Confidential...
  • Page 130 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the CLK_PLL_PREDIV_CTRL Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-130 reserved. Non-Confidential...
  • Page 131 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the CLK_POSTDIV_CTRL_QSPI bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-131 reserved. Non-Confidential...
  • Page 132 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the CLK_POSTDIV_CTRL_TEST Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-132 reserved. Non-Confidential...
  • Page 133 Bypass clock divider RTCDIV: 0b0: Not bypass. 0b1: Bypass. Reset value 0b0. BYPASS_QSPI_DIV_CLK Bypass clock divider QSPIDIV: 0b0: Not bypass. 0b1: Bypass. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-133 reserved. Non-Confidential...
  • Page 134 0b111: PLL0_CLK=INT_OSC/128. Reset value 0b000. [11:0] PLL0_M Controls the feedback divider of PLL0 to set the target frequency of the internal oscillator: INT_OSC=4×PLL0_M×PRE_PLL_CLK. Reset value 0x5F4. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-134 reserved. Non-Confidential...
  • Page 135 Enable BBGEN clock gate: 0b0: Not enabled. 0b1: Enabled. Reset value 0b1. [10] CTRL_ENABLE_REFCLK Enable REFCLK clock gate: 0b0: Not enabled. 0b1: Enabled. Reset value 0b1. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-135 reserved. Non-Confidential...
  • Page 136 Enable I2SCLK0 SYSSYSUGCLK clock gate: 0b0: Not enabled. 0b1: Enabled. Reset value 0b1. CTRL_ENABLE_GPIOHCLK Enable GPIO SYSSYSUGCLK clock gate: 0b0: Not enabled. 0b1: Enabled. Reset value 0b1. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-136 reserved. Non-Confidential...
  • Page 137 0b1: Ready. Reset value 0b1. RESET_CTRL Register The RESET_CTRL Register characteristics are: Purpose Resets Musca‑S1 test chip peripherals. Usage constraints There are no usage constraints. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-137 reserved. Non-Confidential...
  • Page 138 Reset value 0b1. [12] PWM1_RESET Reset PWM1: 0b0: Reset. 0b1: No effect. Reset value 0b1. [11] PWM0_RESET Reset PWM0: 0b0: Reset. 0b1: No effect. Reset value 0b1. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-138 reserved. Non-Confidential...
  • Page 139 Reset value 0b1. I2S_RESET Reset I 0b0: Reset. 0b1: No effect. Reset value 0b1. I2C1_RESET Reset I 0b0: Reset. 0b1: No effect. Reset value 0b1. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-139 reserved. Non-Confidential...
  • Page 140 Reset value 0b0. [30:9] Reserved. TODBGENSEL1 Enable or mask, bypass, Flush input from the Cross Trigger Interface: 0b0: Enabled. 0b1: Mask, or bypass. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-140 reserved. Non-Confidential...
  • Page 141 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the SRAM_CTRL Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-141 reserved. Non-Confidential...
  • Page 142 0b0: Not enabled. 0b1: Enabled. Reset value 0b0. [24] CODE_SRAM24_PGEN 25th 64KB SRAM cell power gate enable: 0b0: Not enabled. 0b1: Enabled. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-142 reserved. Non-Confidential...
  • Page 143 0b0: Not enabled. 0b1: Enabled. Reset value 0b0. [16] CODE_SRAM16_PGEN 17th 64KB SRAM cell power gate enable: 0b0: Not enabled. 0b1: Enabled. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-143 reserved. Non-Confidential...
  • Page 144 10th 64KB SRAM cell power gate enable: 0b0: Not enabled. 0b1: Enabled. Reset value 0b0. CODE_SRAM8_PGEN 9th 64KB SRAM cell power gate enable: 0b0: Not enabled. 0b1: Enabled. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-144 reserved. Non-Confidential...
  • Page 145 2nd 64KB SRAM cell power gate enable: 0b0: Not enabled. 0b1: Enabled. Reset value 0b0. CODE_SRAM0_PGEN 1st 64KB SRAM cell power gate enable: 0b0: Not enabled. 0b1: Enabled. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-145 reserved. Non-Confidential...
  • Page 146 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the CPU0_VTOR Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-146 reserved. Non-Confidential...
  • Page 147 Reset vector for CPU1 Secure mode to external QSPI Flash when BOOT=0b0: Reset value 1020_0000. CPU1_VTOR_1 Register The CPU1_VTOR_1 Register characteristics are: Purpose Controls reset vector for CPU1 secure mode. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-147 reserved. Non-Confidential...
  • Page 148 Selects either MAIN_OUT or ALTF1 as output data for Musca‑S1 test chip I/O PA31‑PA0. 3.11.1 IOMUX registers on page 3-122 for information on the Musca‑S1 test chip I/O multiplexer. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-148 reserved. Non-Confidential...
  • Page 149 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the IOMUX_MAIN_OENSEL Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-149 reserved. Non-Confidential...
  • Page 150 2.2.2 Test chip multiplexed I/O on page 2-23 for the functions that are available on the multiplexed Musca‑S1 test chip I/O. IOMUX_ALTF1_INSEL Register The IOMUX_ALTF1_INSEL Register characteristics are: 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-150 reserved. Non-Confidential...
  • Page 151 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the IOMUX_ALTF1_OUTSEL Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-151 reserved. Non-Confidential...
  • Page 152 2.2.2 Test chip multiplexed I/O on page 2-23 for the functions that are available on the multiplexed Musca‑S1 test chip I/O. IOMUX_ALTF1_DEFAULT_IN Register The IOMUX_ALTF1_DEFAULT_IN Register characteristics are: 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-152 reserved. Non-Confidential...
  • Page 153 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the IOMUX_ALTF2_INSEL Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-153 reserved. Non-Confidential...
  • Page 154 2.2.2 Test chip multiplexed I/O on page 2-23 for the functions that are available on the multiplexed Musca‑S1 test chip I/O. IOMUX_ALTF2_OENSEL Register The IOMUX_ALTF2_OENSEL_0 Register characteristics are: 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-154 reserved. Non-Confidential...
  • Page 155 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the IOMUX_ALTF2_DEFAULT_IN Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-155 reserved. Non-Confidential...
  • Page 156 Table 3-99 IOPAD_DS0 Register bit assignments Bits Name Function [31:0] DRIVE_STRENGTH0 Least significant bits of the two-bit values that define drive strengths ofMusca‑S1 test chip I/O PA31‑PA0. Reset value 0x03F0_0000. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-156 reserved. Non-Confidential...
  • Page 157 Bits Name Function [31:0] PULL_SELECT Selects pull mode of pull resistors onMusca‑S1 test chip I/O PA31‑PA0. 0b0: Pull down. 0b1: Pull up. Reset value 0xF81F_FFFF. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-157 reserved. Non-Confidential...
  • Page 158 Reset value 0xFFFF_FFFF. SPARE0 Register The SPARE0 Register characteristics are: Purpose Spare read/write register for use by software. Usage constraints There are no usage constraints. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-158 reserved. Non-Confidential...
  • Page 159 0b0: Mask trigger input of associated Cross Trigger Interface output when NIDEN is LOW. 0b1: Not mask trigger output of associated Cross Trigger Interface output. Reset value 0x00. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-159 reserved. Non-Confidential...
  • Page 160 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the SCC_MRAM_CTRL0 Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-160 reserved. Non-Confidential...
  • Page 161 PG VDD: 0b0: Powered up. 0b1: Powered down. Reset value 0b0. PG_VDD18_0 eMRAM1 PG VDD18_0: 0b0: Powered up. 0b1: Powered down. Reset value 0b0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-161 reserved. Non-Confidential...
  • Page 162 Reset value 0b0. PROC_SPEC_CLK_EN Enable eMRAM controller clock: 0b0: Disabled. 0b1: Enabled. Reset value 0b1. MRAM_CLK_EN Enable eMRAM clock: 0b0: Disabled. 0b1: Enabled. Reset value 0b1. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-162 reserved. Non-Confidential...
  • Page 163 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the SCC_MRAM_CTRL2 Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-163 reserved. Non-Confidential...
  • Page 164 There are no usage constraints. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the SCC_MRAM_DIN0 Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-164 reserved. Non-Confidential...
  • Page 165 Reset value 0x0200_F2CE. SCC_MRAM_DOUT1 Register The SCC_MRAM_DOUT1 Register characteristics are: Purpose eMRAM memory data output[63:32]. Usage constraints This register is read-only. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-165 reserved. Non-Confidential...
  • Page 166 This register is read-only. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125. The following table shows the SCC_MRAM_STATUS Register bit assignments. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-166 reserved. Non-Confidential...
  • Page 167 Controls clock phase shift control signals. Usage constraints There are no usage register read or write constraints. Note Arm recommends that you do not alter the default values during normal operation. Memory offset and full register reset value 3.11.2 SCC registers summary on page 3-125.
  • Page 168 Name Function [31:8] Reserved. [7:5] N_CTRL Select VBBN_OUT range: 0b001: VBBN_OUT=-0.4V. 0b010: VBBN_OUT=-0.6V. 0b011: VBBN_OUT=-0.8V. 0b100: VBBN_OUT=-1.0V. 0b101: VBBN_OUT=-1.2V. 0b110: VBBN_OUT=-1.4V (recommended). Reset value 0b000. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-168 reserved. Non-Confidential...
  • Page 169 Table 3-118 SPARE_CTRL1 Register bit assignments Bits Name Function [31:0] SPARE_CTRL1 Spare control register. Software assigns the bit meanings. Reset value 0x0000_0000. CHIP_ID Register The CHIP_ID Register characteristics are: 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-169 reserved. Non-Confidential...
  • Page 170 Table 3-120 IO_IN_STATUS Register bit assignments Bits Name Function [31:0] IO_IN_STATUS Real time I/O pads input status. Bit number corresponds to pad number, bit[0]=PA0). Reset value 0x05FF_FFE3. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-170 reserved. Non-Confidential...

  • Page 171: Uart Control Registers

    Masked Interrupt Status Register. 0x0044 UART0ICR Interrupt Clear Register. 0x0048 UART0DMACR 0x0000_0000 32 DMA Control Register. 0x0FE0 UART0PeriphID0 0x0000_0011 32 UART0 peripheral ID Register 0. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-171 reserved. Non-Confidential...
  • Page 172 0x0000_0000 32 UART1 peripheral ID Register 3. 0x1FF0 UART1PCellID0 0x0000_000D 32 UART1 component ID Register 0. 0x1FF4 UART1PCellID1 0x0000_00F0 32 UART1 component ID Register 1. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-172 reserved. Non-Confidential...
  • Page 173 Offset Name Type Reset value Width Function 0x1FF8 UART1PCellID2 0x0000_0005 32 UART1 component ID Register 2. 0x1FFC UART1PCellID3 0x0000_00B1 32 UART1 component ID Register 3. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-173 reserved. Non-Confidential...

  • Page 174: Gpio Control Registers

    0x0000_0000 32 Polarity‑level, edge IRQ configuration. Clear interrupt polarity bit. Bits [31:16] are reserved. 0x0038 GPIOINTSTATUS 0x0000_0000 32 Clear interrupt request. INTCLEAR Bits [31:16] are reserved. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-174 reserved. Non-Confidential...
  • Page 175 Bits [31:8] are reserved. 0x0FF8 GPIOCID2 0x0000_0000 32 Component ID Register 2. Bits [31:8] are reserved. 0x0FFC GPIOCID3 0x0000_0000 32 Component ID Register 3. Bits [31:8] are reserved. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-175 reserved. Non-Confidential...

  • Page 176: Third-Party Ip

    0x4010_A000 — Base memory address in the Secure region. 0x5010_A000 Contact your local Cadence representative for information about the QSPI, I2C, I2S, PWM, and SPI. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights 3-176 reserved. Non-Confidential...
  • Page 177 It contains the following sections: • A.1 Arduino Expansion Shield connectors on page Appx-A-178. • A.2 Debug connector on page Appx-A-181. • A.3 USB connector on page Appx-A-182. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-A-177 reserved. Non-Confidential...

  • Page 178: Arduino Expansion Shield Connectors

    ALTF3. The IOMUX registers are part of the Serial Configuration Control (SCC) registers. See 3.11.1 IOMUX registers on page 3-122 2.2.2 Test chip multiplexed I/O on page 2-23. The following table shows the pin mappings for connector J11. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-A-178 reserved. Non-Confidential...
  • Page 179 Connector J14 provides six analog I/O for the Arduino Expansion Shield. The following table shows the pin mapping for connector J14. Table A-3 Analog I/O connector J14 signal list Signal AN[0] AN[1] AN[2] AN[3] 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-A-179 reserved. Non-Confidential...
  • Page 180 Signal IOREF Related information 1.3 The Musca ‑ S1 development board at a glance on page 1-14 2.10 Arduino Expansion Shield interface on page 2-38 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-A-180 reserved. Non-Confidential...

  • Page 181: Debug Connector

    Debug connector The Musca‑S1 development board provides one 3V3 10‑pin CoreSight debug connector. The connector supports Serial Wire or JTAG processor debug (SWJ - DP) to enable connection of a DSTREAM or Arm Keil ULINK-Plus debug adapter, or a compatible third‑party debugger.

  • Page 182: Usb Connector

    The GND_EARTH connection is the casing of the mini-B connector. Related information 1.3 The Musca ‑ S1 development board at a glance on page 1-14 2.8 Power on page 2-34 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-A-182 reserved. Non-Confidential...

  • Page 183: Appendix B Hardware Bug Software Workaround

    This appendix describes a software workaround for hardware bugs in Secure and Non‑secure privilege registers. It contains the following section: • B.1 S1 Secure and Non-secure privilege registers hardware bug on page Appx-B-184. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-B-183 reserved. Non-Confidential...

  • Page 184: S1 Secure And Non-Secure Privilege Registers Hardware Bug

    Correct access only. operation. Bit[n]=0b1 Write to the following Unprivileged and Incorrect registers: Privileged access operation. for selected AHBNSPPCEXP0[0]=0b0. Cannot select peripheral. Unprivileged AHBSPPPCEXP0[0]=0b1 access. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-B-184 reserved. Non-Confidential...
  • Page 185 Bit[n]=0b0 Privileged access Works access only. correctly Bit[n]=0b1 Write to the following Unprivileged and Incorrect registers: Privileged access. operation. AHBNSPPCEXP0[0]=0b1. Cannot select Unprivileged AHBNSPPPCEXP0[0]=0b1 access. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-B-185 reserved. Non-Confidential...

  • Page 186: Appendix Cpvt Sensors

    This appendix describes the Process, Voltage, and Temperature (PVT) sensors on the Musca‑S1 test chip. It contains the following section: • C.1 PVT sensors on page Appx-C-187. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-C-186 reserved. Non-Confidential...
  • Page 187 The reference counter initiates and controls the PVT measurements. It stores the programmed measurement time window and when the reference counter reaches the programmed value it: 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-C-187 reserved.
  • Page 188 Controlling and reading data from the PVT sensors The PVT sensor control registers control and read data from the active PVT sensor. See 3.9 PVT sensor registers on page 3-113. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-C-188 reserved. Non-Confidential...

  • Page 189: Appendix Dip Configuration

    IP configuration This appendix describes the IP configuration of the Musca‑S1 test chip. It contains the following section: • D.1 IP configuration on page Appx-D-190. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-D-189 reserved. Non-Confidential...
  • Page 190 D IP configuration D.1 IP configuration IP configuration The Musca‑S1 test chip implements Arm CoreLink SSE-200 Subsystem version r1p0. The following table shows the IP configuration of the Musca‑S1 test chip Table D-1 Musca-S1 test chip IP configuration Product code...

  • Page 191: Appendix E Specifications

    Appendix E Specifications This appendix contains electrical specifications of the Musca‑S1 development board. It contains the following section: • E.1 Electrical specifications on page Appx-E-192. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-E-191 reserved. Non-Confidential...

  • Page 192: Electrical Specifications

    The electrical specifications of the Musca‑S1 development board are as follows: 2.8 Power on page 2-34 for information on the Musca‑S1 development board power supply rails and maximum current loads. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-E-192 reserved. Non-Confidential...

  • Page 193: Appendix F Revisions

    Appendix F Revisions This appendix describes the technical changes between released issues of this book. It contains the following section: • F.1 Revisions on page Appx-F-194. 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-F-193 reserved. Non-Confidential...
  • Page 194 AHBNSPPCEXP0 Register on page 3-75 bit[0] in registers used in the software workaround versions AHBSPPPCEXP0 Register on page 3-80 for the software bug. AHBNSPPPCEXP0 Register on page 3-86 101835_0000_01_en Copyright © 2019, 2020 Arm Limited or its affiliates. All rights Appx-F-194 reserved. Non-Confidential...

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