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OPQ Programmer's Guide V 1.1
state logic implemented in hardware, but to my understanding it is not used when
accessing the OPQ chip. This gives some rough idea about the bus timing specifications.
The chip comes in a 40-pin DIP package and the pinout is:
Pin functions:
VDD, VSS
D7...D0
A7...A0
WR, RD
CS, EN, EN
IRQ
IC
SO, RSH, LSH
ø10
X1, X2
5V supply
Data bus from/to CPU
Address bus from CPU
Write/read signals from CPU
Chip select and enable signals from address decoding. In PSR-70
only CS is used, EN and EN are connected permanently active.
Interrupt request to CPU
Inital clear ( = reset) from reset logic
Serial data out to DAC. In YM3012, signals SD, SAM1, SAM2
respectively.
Clock out to DAC
Crystal. In PSR-70, a 3.579 MHz is used.
4
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