ARM lntegrator IM-PD1 User Manual

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Integrator/IM-PD1

User Guide

ARM DUI 0152C

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Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 5: Table Of Contents
Differences in signal naming between supported logic modules ....3-2 Smart card interface ..................3-3 IrDA interface ....................3-6 UART interface ................... 3-7 USB interface .................... 3-10 Audio CODEC ................... 3-12 ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 6 About the design example ................4-2 Design example ..................4-3 Appendix A Signal Descriptions EXPA ......................A-2 EXPB ......................A-4 EXPIM ......................A-6 Logic analyzer connector ................A-8 Appendix B Mechanical Specification Mechanical information ................B-2 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 7 Preface This preface introduces the Integrator/IM-PD1 interface module and its user documentation. It contains the following sections: • About this book on page viii • Feedback on page xii. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 8: Preface
This book is written for all developers who are using the Integrator/IM-PD1 interface module with an Integrator/LM-XCV600E+ or LM-EP20K600E+ logic module to develop ARM-based devices. It assumes that you are an experienced developer, and that you are familiar with the ARM development tools.
Page 9 Denotes language keywords when used outside example code. monospace bold Further reading This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors. ARM periodically provides updates and corrections to its documentation. See http://www.arm.com...
Page 10 Preface The following publication provide information about ARM PrimeCell devices that can be used to control the interfaces described in this manual: • ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183) • ARM PrimeCell Synchronous Serial Port Master and Slave (PL022) Technical Reference Manual (ARM DDI 0171) •...
Page 11 Preface http://www.infineon.com/cmc_upload/0/000/019/200/IRMS_T6400.pdf • PDIUSBP11A Universal Serial Bus Transceiver Data sheet (853-2008 21712) available at: http://www-us6.semiconductors.com/acrobat/data sheets/PDIUSBP11A_2.pdf • DAC-Controlled Boost/Inverter LCD Bias Supply with Internal Switch Data sheet (19-1327) available at: http://pdfserv.maxim-ic.com/arpdf/MAX686.pdf ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 12: Feedback
Preface Feedback ARM Limited welcomes feedback on both the Integrator/IM-PD1 and its documentation. Feedback on this document If you have any comments on this book, please send email to giving: errata@arm.com • the document title • the document number •...
Page 13: Introduction
This chapter introduces the Integrator/IM-PD1. It contains the following sections: • About the Integrator/IM-PD1 on page 1-2 • Interface module features and architecture on page 1-4 • Links on page 1-7 • Care of modules on page 1-8. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 14: About The Integrator/Im-Pd1
Figure 1-1 on page 1-3 shows the layout of the Integrator/IM-PD1. Circuit diagrams of the Integrator/IM-PD1 and third party data sheets are available as pdf files after installation from the CDROM. Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 15 Off-PCB smartcard Buzzer connector (J34) enable link (J23) Smart card voltage select link ( Buzzer Sharp 8.4” TFT (J14) Smart card RS232 socket (J10) (J12A and J12B) Figure 1-1 Integrator/IM-PD1 layout ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 16: Interface Module Features And Architecture
F bus connect to the GPIO bus on the Integrator/AP. This bus is routed between the system controller FPGA on the motherboard and the FPGA on the logic module. These signals are available for your own applications. Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 17 • The Multi-ICE connector enables you to gain access to the JTAG signals on the modules in the stack on which the interface module is mounted. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 18 LA connector (B bus) Push (J19) buttons Video Host Buffer Device UART 0 ON/OFF UART 1 Buffer Audio Codec Bias adjust Touchscreen controller IrDA transceiver Smartcard interface Figure 1-2 Integrator/IM-PD1 block diagram Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 19: Links
Smartcard voltage select link LK2 The smartcard voltage select link is a soldered link that is used to set the operating voltage of the smartcard interface (see Smart card interface on page 3-3). ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 20: Care Of Modules
Visually inspect the module to ensure that connector holes are clear before mounting it onto another board. • Observe ElectroStatic Discharge (ESD) precautions when handling any Integrator board. Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 21 This chapter describes how to set up and start using the logic module. It contains the following sections: • Setting up the logic module on page 2-2 • Fitting the interface module on page 2-3 • Connecting Multi-ICE or other JTAG equipment on page 2-5. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 22: Setting Up The Logic Module
FPGA programming tool connector. This means that the logic module FPGA must be configured from flash or directly using the Multi-ICE connector if the logic module supports direct Multi-ICE configuration. Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 23: Fitting The Interface Module
This option uses a core module at the bottom of a stack of one or more other modules. One logic module must be included that provides the system control function (for example, a system bus arbiter) normally provided by the motherboard. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 24 (see the user guide for your core module). • on any logic modules, set LK3 to the C-D position. • on one logic module, program and enable the CLK2 clock generator (see ARM Integrator/LM-XCV600E+ LM-EP20K600E+ User Guide). Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 25: Connecting Multi-Ice Or Other Jtag Equipment
Figure 2-2 Connecting Multi-ICE Note There are no components on the interface module that use the JTAG signals. The connector provides you with access to the JTAG signals on the modules below. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 27 MMC and SD flash card interface on page 3-14 • Display interface on page 3-17 • Touchscreen controller on page 3-21 • Backlight control on page 3-23 • Push buttons on page 3-24 • Buzzer on page 3-25. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 28: Differences In Signal Naming Between Supported Logic Modules
The logic module output voltage on these banks is adjustable. Ensure that the logic module selection link is set to the 3V3 position. Note These pin assignments are contained in the example pin constraints file on the CD that accompanies the interface module. Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 29: Smart Card Interface
SC_SCICLKIN SC_SCIDATAIN SC_PRESENT Figure 3-1 Smart card interface You can set the SCI to operate at 3.3V or at 5V by setting the solder link LK2. The default setting is 5V. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 30 The smart card is inserted into the smartcard socket with the contacts face down. Figure 3-3 on page 3-5 shows the pinout of the connector J34. This can be used to connect to an off-PCB smart card device. Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 32: Irda Interface
The signals associated with the infrared interface are assigned on the EXPIM socket pins as shown in Table 3-1. Table 3-2 IrDA interface signal assignment Signal name EXPIM connector Description SIR_SCLK IM_BBANK55 Serial clock SIR_TXD IM_BBANK56 Transmit data SIR_RXD IM_BBANK57 Receive data Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 33: Uart Interface
IM_BBANK49 Data terminal ready UART0_CTS IM_BBANK50 Clear to send UART0_DSR IM_BBANK51 Data set ready UART0_DCD IM_BBANK52 Data carrier detect UART0_RXD IM_BBANK53 Receive data UART0_RI IM_BBANK54 Ring indicator UART1_TXD IM_ABANK0 Transmit data ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 34 Table 3-4 on page 3-9 shows the signal assignment for the two connectors. The pinout shown in Figure 3-7 on page 3-9 is configured as a Data Communications Equipment (DCE) device. Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 35 Figure 3-7 Serial connector pinout Table 3-4 Serial plug signal assignment J12A J12B SER0_DCD SER1_DCD SER0_RX SER1_RX SER0_TX SER1_TX SER0_DTR SER1_DTR SER0_GND SER1_GND SER0_DSR SER1_DSR SER0_RTS SER1_RTS SER0_CTS SER1_CTS SER0_RI SER1_RI ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 36: Usb Interface
Gated version of D+ USB0_RCV IM_BBANK18 Receive data USB0_SUSPEND IM_BBANK19 Suspend for power save USB0_nOE IM_BBANK20 Output enable USB0_VMO IM_BBANK21 Differential input – USB0_VPO IM_BBANK22 Differential input + USB0_MODE IM_BBANK23 Mode 3-10 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 37 Berg. Figure 3-9 identifies the connectors for the host and device interfaces and shows how the pins are numbered. 1 2 3 4 Device Host Figure 3-9 Identifying the USB connectors ARM DUI 0152C Copyright © 2001. All rights reserved. 3-11...
Page 38: Audio Codec
Clock from the CODEC AAC_SYNC IM_ABANK10 Frame synchronization signal from the AACI AACI_SDATA_IN IM_ABANK11 Serial data from the CODEC to the AACI AACI_RESET IM_ABANK12 Reset signal from the PrimeCell AACI 3-12 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 39 For correct operation of the CODEC interface, you must mute the PC Beep input by setting bit 15 in the PC Beep register within the CODEC (see the LM4549 datasheet available from National Semiconductors). ARM DUI 0152C Copyright © 2001. All rights reserved. 3-13...
Page 40: Mmc And Sd Flash Card Interface
HIGH = power OFF • HIGH = power OFF MCI_1 IM_BBANK8 Card detect/Data(3) Chip select (active LOW) MCI_2 IM_BBANK9 Command/Response Command/Response MCI_5 IM_BBANK10 MCI_7 IM_BBANK11 Data(0) Data MCI_8 IM_BBANK12 Data(1) not used 3-14 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 41 Figure 3-14 with pin 9 next to pin 1 and pins 7 and 8 spaced more closely together than the other pins. Figure 3-15 shows an MMC card, with the contacts face up. 1 2 3 4 5 6 7 Figure 3-15 MMC card ARM DUI 0152C Copyright © 2001. All rights reserved. 3-15...
Page 42 The connector J33 enables you to access the signals for debugging or to an off-PCB card socket. The pinout of J33 is shown in Figure 3-16. MCI_1 MCI_2 MCI_PWR MCI_5 MCI_7 MCI_8 MCI_9 MCI_nCARDIN MCI_WPROT Figure 3-16 J33 pinout 3-16 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 43: Display Interface
J27 and B28 is used to enable the buffers for the Sharp display signals on J14. Video GREEN B[23:0] BLUE (U20) HSYNC VSYNC Buffers LCD1_[23:0] (U12/U13) Enable LCD0_CLK LCD0_HSYNC LCD0_VSYNC LCD0_R[5:0] Buffers LCD0_G[5:0] (U11/U12) LCD0_B[5:0] LCD0_ENAB LCD0_R/L LCD0_U/D Enable Figure 3-17 Display interfaces ARM DUI 0152C Copyright © 2001. All rights reserved. 3-17...
Page 44 The interface module provides two connectors. One (J14) is a dedicated connector for a 8.4 inch Sharp LCD display and the second (J27) provides a generic interface. Figure 3-19 on page 3-20 shows the pinout of connector J27. 3-18 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 45 Figure 3-19 on page 3-20 are connected to the PrimeCell. If you intend to use anything other than the shipped example then signal allocation is a user decision. ARM DUI 0152C Copyright © 2001. All rights reserved. 3-19...
Page 46 LCD1_22 LCD1_23 TS_XP TS_YP TS_XN TS_YN LCD1_BIAS LCD1_3V3 BL_ADJ Figure 3-19 J27 pinout Note The LCD1[23:0] signals are 3V3 buffered versions of B[23:0], see the schematic diagram for more details. 3-20 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 47: Touchscreen Controller
Serial data input to controller TS_nCS IM_BBANK42 Controller chip select TS_DCLK IM_BBANK43 Clock input to controller TS_DOUT IM_BBANK44 Data output from controller TS_BUSY IM_BBANK45 Busy indicator from controller TS_nPENIRQ IM_BBANK46 Interrupt from controller ARM DUI 0152C Copyright © 2001. All rights reserved. 3-21...
Page 49: Backlight Control
2k Ω potentiometer R153. This enables you to adjust the BL_ADJ output between 0V and 2.5V. This is available from the connector J32. Figure 3-22 shows the pinout of J32. BL_ADJ Figure 3-22 Backlight connector pinout ARM DUI 0152C Copyright © 2001. All rights reserved. 3-23...
Page 50: Push Buttons
Table 3-9 Push button interface signal assignment Signal name EXPIM connector Description IM_BBANK1 Input from S1 IM_BBANK2 Input from S2 IM_BBANK3 Input from S3 IM_BBANK4 Input from S4 IM_BBANK5 Input from S5 IM_BBANK6 Input from S6 3-24 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 51: Buzzer
The signal assignment is shown in Table 3-10. Table 3-10 Buzzer interface signal assignment Signal name EXPIM connector Description nBUZZER IM_BBANK0 Controls power to the buzzer: • LOW = power ON • HIGH = power OFF. ARM DUI 0152C Copyright © 2001. All rights reserved. 3-25...
Page 53: Chapter 4 Reference Design Example
This chapter describes how to set up and start using the logic module. It contains the following sections: • About the design example on page 4-2 • Design example on page 4-3. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 54: About The Design Example
The interface module is supplied with executable software that demonstrates the functionality of the PrimeCells included in the design example. The ARM PrimeCells are a range of synthesizable peripherals that are ideally suited for use in ARM-based designs. The interface module is supplied with an FPGA image containing PrimeCell peripherals for each supported interface on the board and the accompanying CD contains documentation for them.
Page 55: Design Example
System Unidirectional to bidirectional bridge UART0 interface USB host UART1 Vectored interrupt controller USB slave (PL190) GPIO0 Address GPIO1 decoder CLCD SSRAM MMCI controller controller AACI TSCI Figure 4-1 Design example ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 56 Limited. These blocks can be licensed from other IP providers. Vectored interrupt controller The PrimeCell PL190 Vectored Interrupt Controller (VIC) provides a software interface to the interrupt system. In an ARM system, two levels of interrupt are available: • Fast Interrupt Request (FIQ) for fast, low latency interrupt handling •...
Page 57 This file is the top-level VHDL that instantiates all of the PrimeCells for the example. The VHDL for AHBTop.vhd the PrimeCells themselves are not supplied but are available from ARM as separate products. The decoder block provides the high-speed peripherals with select lines. These are generated from AHBDecoder.vhd...
Page 58 It is important when implementing a logic module design, to ensure that the module responds to all memory accesses in the appropriate memory region (see the user guide for your motherboard). Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 59 Read Switches register 0x0000014 LM_CONTROL Read/write Control register 0x0000018 Oscillator divisor registers The oscillator registers control the frequency of the clocks generated by the two clock generators on the logic module. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 60 (V[8:0] +8) Frequency = 48MHz · (R[6:0] +2) · OD You must also observe the operating range limits: (V[8:0] +8) 10MHz < 48MHz · (R[6:0] +2) R[6:0] < 118 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 61 Write any other value to this register to lock the oscillator registers. User LEDs control register The LEDs register is used to control the user LEDs on the logic module. Writing a 0 to a bit lights the associated LED. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 62 This register controls the multiplexors that are used to select the: • display type • touchscreen controller (see Touch screen controller interface registers on page 4-12 for more information. Table 4-7 on page 4-11 describes the operation of this register. 4-10 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 63 Table 4-8 shows the assignment of the SSP signals to the prototyping grid when the TSCI is selected. Table 4-8 Assignment of SSP signals to module prototyping holes Prototyping Signal hole SSPTXD SSPCLKOUT SSPFSS SSPRXD ARM DUI 0152C Copyright © 2001. All rights reserved. 4-11...
Page 64 Touch screen X Y auto-read register Table 4-11 describes the operation of this register. Table 4-11 TS_AUTORDXY register Name Access Function 27:16 Read Last Y value 11:0 Read Last X value 4-12 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 65 The PENDOWN bit in the touchscreen control register will remain set until 0 is written. A pendown event will cause the X and Y registers to be updated. This can be used to generate an interrupt. ARM DUI 0152C Copyright © 2001. All rights reserved. 4-13...
Page 67: Expa
This appendix describes the Integrator/IM-PD1 interface connectors and signal connections. It contains the following sections: • EXPA on page A-2 • EXPB on page A-4 • EXPIM on page A-6 • Logic analyzer connector on page A-8. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 69 B[31:0] These signals connect to the FPGA on the logic module. They are used to carry display interface signals (see Display interface on page 3-17) C[31:0] Not used D[31:0] Not used ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 70 Table A-2 describes the signals on the pins labeled H[31:0], J[16:0]. Table A-2 EXPB signal assignment Pin label Name Description H[31:29] Not used SYSCLK System clock from the logic module. H[27:0] Not used J[16:14] Not used Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 71 If the logic module is mounted in the HDRA/HDRB position on the motherboard, these pins connect to the F bus that is routed between any modules in the stack. There are no signals from the motherboard present on these pins. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 72: Expim
IM_A61 IM_B61 EXP85 EXP185 EXP87 EXP187 EXP88 EXP188 EXP189 EXP89 EXP91 EXP191 EXP92 EXP192 EXP93 EXP193 EXP194 EXP95 EXP195 EXP96 EXP196 EXP197 EXP97 EXP98 EXP198 Figure A-3 EXPIM socket pin numbering Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 73 Not used (socket). Caution For correct operation of the interface module, VCCO_A and VCCO_B must be set to 3.3V. Ensure that the VCCO links are set correctly on the logic module. ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 74: Logic Analyzer Connector
Figure A-4 shows the pin numbers of this type of connector. Figure A-4 J19 pin locations Table A-4 shows the pinout of the logic analyzer connector. Table A-4 J19 connector pinout Signal Signal No connect No connect No connect SYSCLK CLK1 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 76 Figure A-5 shows the pinout of the Multi-ICE connector J21. For a description of the JTAG signals, see the user guide for your logic module. nTRST RTCK nSRST Figure A-5 Multi-ICE connector pinout A-10 Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 77: Appendix B Mechanical Specification
Appendix B Mechanical Specification This appendix contains the mechanical specification for Integrator/IM-PD1. It contains the following section: • Mechanical information on page B-2 ARM DUI 0152C Copyright © 2001. All rights reserved.
Page 78: Mechanical Information
(4 col x 50 row) (4 col x 30 row) Plug on top and Plug on top and socket on underside socket on underside EXPB EXPA 16.1 10.0 Detail A Figure B-1 Board dimensions Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 79 Mechanical Specification Note In Figure B-1 on page B-2, the 148.0 and 100.0 dimensions show the size of a standard module produced by ARM Limited. B.1.1 Connector part numbers The Samtec connector part numbers are listed in Table B-1. Table B-1 Samtec connector part numbers...
Page 81 This glossary lists all the abbreviations used in the Integrator/IM-PD1 User Guide. Advanced Audio CODEC Interface. AACI The ARM open standard for on-chip buses. AHB conforms to this standard. AMBA High-performance The ARM open standard for peripheral buses. APB conforms to this standard.
Page 82 24-bit parallel data into red, green, and blue signals for a display and generates horizontal and vertical synchronization signals from a clock input. Zero Bus Turnaround Synchronous Static Random Access Memory. ZBT SSRAM Copyright © 2001. All rights reserved. ARM DUI 0152C...
Page 83 CE Declaration of Conformity ii Display interface signal routing 1-4 Logic analyzer connector A-8 CONFIG link 1-3, 1-7 Display interface, description 3-17 Logic module registers 4-7 Connecting Multi-ICE 2-5 Display support 1-4 ARM DUI 0152C Copyright © 2001. All rights reserved. Index-1...
Page 84 Push button interrupt register 4-10 VGA socket 1-3 Registers LM_CONTROL 4-10 LM_INT 4-7 LM_LEDS 4-7 LM_LOCK 4-7 LM_OSC1 4-7 LM_OSC2 4-7 LM_SW 4-7 RS232 connectors 1-3 RS232 interface 3-7 SD flash card interface 3-14 Index-2 Copyright © 2001. All rights reserved. ARM DUI 0152C...

ARM lntegrator IM-PD1 User Manual

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