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Systran SCRAMNet+ VME3U Hardware Reference Manual

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SCRAMNet
Network
VME3U
Hardware Reference
Document No. D-T-MR-VME3U###-A-0-A2

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  • Page 1 ® SCRAMNet Network VME3U Hardware Reference Document No. D-T-MR-VME3U###-A-0-A2...
  • Page 3 SYSTRAN reserves the right to make changes without notice. SYSTRAN makes no warranty of any kind with regard to this printed material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.
  • Page 5 TABLE OF CONTENTS 1.0 HOW TO USE THIS MANUAL ....................5 1.1 Scope..........................5 1.2 Organization........................5 1.3 Appendices........................5 1.4 Related Documentation....................6 2.0 INTRODUCTION........................2-1 2.1 Overview........................2-1 2.1.1 Network Features..................2-1 2.1.2 Options..................... 2-2 2.1.3 VME3U Board Features ................. 2-2 2.2 VMEbus Specification Level ................... 2-3 2.3 Addressing Compatibility ..................
  • Page 6 HOW TO USE THIS MANUAL 3.10.4 Loopback Modes ................. 3-10 3.10.5 Write-Me-Last Mode ................3-11 3.11 Options........................3-11 3.11.1 Electronic Bypass Switch ..............3-11 3.11.2 Quad Switch..................3-12 3.11.3 Cabinet Kit................... 3-12 4 0 OPERATION ......................... 4-1 4.1 Introduction....................... 4-1 4.2 Shared Memory......................

  • Page 7: Table Of Contents

    APPENDICES APPENDIX A - CSR SUMMARY....................A-1 APPENDIX B - CABINET KIT ....................B-1 APPENDIX C - SPECIFICATIONS.....................C-1 APPENDIX D - HOST ACCESS TIMING ................. D-1 APPENDIX E - CONFIGURATION AIDS .................E-1 APPENDIX F - ACRONYMS ...................... F-1 APPENDIX G - GLOSSARY ...................... G-1 FIGURES Figure 2-1 VME3U Board......................
  • Page 8 HOW TO USE THIS MANUAL Table 5-7 CSR6 - Interrupt Vector (Memory Update) ............... 5-11 Table 5-8 CSR7 - Interrupt Vector (SCRAMNet Error) ............5-11 Table 5-9 CSR8 - General SCRAMNet Extended Control Register ........5-12 Table 5-10 CSR9 - SCRAMNet Interrupt On Error Mask .............
  • Page 9 1. HOW TO USE THIS MANUAL 1.1 Scope This document is a reference manual for the SCRAMNet VME3U host interface board. This document provides a physical and functional description of the SCRAMNet VME3U board designed for a VME based host system. This information is intended for systems designers, engineers and network installation personnel.
  • Page 10 HOW TO USE THIS MANUAL D - Host Access Timing: A discussion of timing coordination between the board and host. E - Configuration Aids: Control/Status Register (CSR) Reference Sheet and network configuration form. F - Glossary: A glossary of words, phrases and terms used in the reference manual.
  • Page 11 2. 0 INTRODUCTION 2.1 Overview SCRAMNet (Shared Common Random Access Memory Network) is a communications network geared toward real-time applications, and based on a replicated, shared-memory concept. The SCRAMNet VME3U host interface node board is backwards-compatible with the original SCRAMNet Classic product with the exception of the GOLD Ring communication protocol.
  • Page 12 INTRODUCTION Figure 2-1 VME3U Board 2.1.2 Options Optional paired fiber optic or coax transmission media Fiber Optic Bypass Switch for ring continuity when node power is off. Quad Switch—A switching control device that controls up to four nodes or sub- rings, eliminates the need for a separate Fiber Optic Bypass, and functions as a repeater.
  • Page 13 INTRODUCTION 2.2 VMEbus Specification Level The SCRAMNet VME3U host board was designed in accordance with the VMEbus specification Revision C.3, ANSI/IEEE Std 1014-1987. Slave device SADO24 (No UAT, no BLT) SRMW16 (D16, D08 (EO)) 8-bit vector ROAK 3U single height card size 2.3 Addressing Compatibility 2.3.1 Memory The shared memory resident on the SCRAMNet...
  • Page 14 INTRODUCTION during the interrupt acknowledge cycle. The 8-bit vector address is loaded at CSR6 - Memory, and CSR7 - Error. If Interrupt-on-Error is not used, CSR7 must contain the same vector as CSR6. 2.6 P1 Connector The SCRAMNet VME3U card’s P1 backplane connector is in accordance with the VMEbus specifications.
  • Page 15 3. 0 DESCRIPTION 3.1 Overview The SCRAMNet Network is a real-time communications network, based on a replicated, shared-memory concept. Each host processor on the network has access to its own local copy of shared memory which is updated over a high-speed, serial-ring network.
  • Page 16 Interrupt FIFO Replicated Shared Receiver Memory Host Interface Logic Tranceiver FIFO Network Control Logic Dual Port Transmitter Memory Controller Transmitt FIFO...
  • Page 17 DESCRIPTION cases, the mode of operation is set during initialization and remains unchanged during run time. The CSRs are described in detail in Section 5. 3.2.3 Virtual Paging All SCRAMNet nodes use the same 8 MB shared memory map. This feature permits different SCRAMNet boards with 4 MB of shared memory or less to be paged into different sections of the 8 MB memory map.
  • Page 18 DESCRIPTION 3.4 Network Ring The SCRAMNet Network is a ring topology network. Data is transmitted at a rate of 150 Mbits/s over dual fiber optic cables. The two lines together produce the incoming data clock. Due to the network speed and message slot size, the network can accommodate over 1,800,000 message slots passing by each node every second.

  • Page 19: Figure 3-2 Acr/Memory Access

    DESCRIPTION CSR0, bit 4 Shared Memory Byte 0 Byte 1 Byte 2 Byte 3 Host READ/WRITE request to a specific 32-bit memory address ACR Memory Byte 0 LEGEND DOES NOT PHYSICAL REALLY EXIST MEMORY CHIP Figure 3-2 ACR/Memory Access , host CPU READ/WRITE operations are channeled to either SCRAMNet Figure 3-2 memory or to the ACR.
  • Page 20 DESCRIPTION 3.6.1 Network Interrupt WRITEs FOREIGN MESSAGE The node can receive a message from another node with the interrupt bit set. If Receive Interrupt Enable (ACR, bit 0) and Interrupt Mask Match Enable (CSR0, bit 5) are enabled, the data is written to shared memory and the address is placed on the Interrupt FIFO.

  • Page 21: Figure 3-3 Outgoing Interrupt

    DESCRIPTION OUTGOING Address A22 - A0 D31 - D0 Data SHARED MEMORY D31 - D0 A22 - A0 Address Data D31 - D0 Interrupt Bit RING NETWORK RING LOGIC Figure 3-3 Outgoing Interrupt INCOMING INTERRUPT INTERRUPT FIFO A16 - A0 A22 - A16 SHARED MEMORY CSR 4...
  • Page 22 DESCRIPTION NETWORK ERRORS The Interrupt on (Network) Errors mode is enabled by setting CSR0, bit 7 ON. Network errors are defined in CSR1 according to an interrupt mask set in CSR9. When an incoming foreign message generates an interrupt, there is no way to mask the interrupt according to the content of the message.
  • Page 23 DESCRIPTION If the Trigger 2 event is the frame counter, the timers in the ring effectively become synchronized sub-frame timers, which can then be used to tag time-critical data or to measure and compare the completion time of various tasks within a distributed real-time system.
  • Page 24 DESCRIPTION EXAMPLE #2: The receiving node may otherwise try to use part or half of such a value before the entire 32 bits is received. HIPRO WRITE The SCRAMNet network message is based on 32-bit longword data. This means if any 8-bit field of the 32-bit buffer is changed the entire 32-bit message is transmitted.
  • Page 25 DESCRIPTION NOTE: If a node is inserted into the network while in wire loopback mode, it will create a break in the network ring, making all nodes down-line unreachable. MECHANICAL SWITCH (MEDIA CARD) LOOPBACK MODE Mechanical Switch (Media Card) Loopback mode is enabled by setting Mechanical Switch Override (CSR8, bit 11) to OFF.
  • Page 26 DESCRIPTION 3.11.2 Quad Switch The Quad Switch is a switching center and is used to dynamically configure active SCRAMNet Classic and SCRAMNet ring(s). The Quad Switch provides dynamic configuration of up to five separate rings. Each separate ring is connected to a port on the Quad Switch. Each ring can be isolated from the other rings or can be included with one or more of the other attached rings.
  • Page 27 4. 0 OPERATION 4.1 Introduction The SCRAMNet Network is a shared-memory system. Every computer on the network has a constantly updated local copy of all global data which is passed to all the network computers. The network protocol is implemented in the SCRAMNet hardware and therefore no software overhead is required to retrieve this information from the network.

  • Page 28: Figure 4-1 Memory Sharing With Virtual Paging

    OPERATION same as if Virtual Paging were disabled. The network address would be the same as the shared-memory address. NOTE: Virtual paging does not affect host access to shared memory. Virtual Paging only changes the network address. The HOST SPECIFIC logic always sees the base address of SCRAMNet shared memory as zero.
  • Page 29 OPERATION shares data with nodes 5, 6, 7, and 9. Node 8 shares data with nodes 1,3, and 9. Node 7 shares data with nodes 2, 5, and 9. Node 9 shares data with all nodes. 4.2.2 Memory Considerations When using SCRAMNet shared-memory, consider the following: PROGRAM AND DATA LIMITATIONS Limitations on application program size and data variable size for a host computer system...

  • Page 30: Table 4-1 Eeprom Table

    OPERATION 4.3 Initialization NOTE: The EEPROM initializes the RX_ID and AGE fields to 0. Therefore, upon power-up, READ the Node ID (TX_ID) CSR3, bits 15-8 and WRITE it back. This will set the RX_ID field equal to the TX_ID field. If this is not done, native messages will not be recognized and will never be removed from the network, and the time-out will not go into effect.

  • Page 31: Table 4-2 Scramnet+ Message Contents

    OPERATION Table 4-2 SCRAMNet+ Message Contents START CONTROL DATA ADDRESS DATA VALUE 5+P 8+P 8+P 8+P 8+P 8+P 8+P RES INT RTY For every 8 bits of data in the message there is a parity bit attached. SOURCE ID This 8-bit field contains the node ID of the originating node. Value ranges from 0 to 255, so there can be 256 nodes on the network ring.
  • Page 32 OPERATION Enable BURST PLUS by setting CSR2, bits 15, 14, and 12 ON, and selecting the desired maximum message packet size by setting CSR2, bit 11 to ‘1’ for 1024 bytes, or ‘0’ for 256 bytes. Both BURST modes are open loop, non-error-corrected modes of operation. Enable PLATINUM PLUS by setting CSR2, bit 15 OFF, CSR2, bits14, and 12 ON, and selecting the desired maximum message packet size by setting CSR2, bit 11 to ‘1’...
  • Page 33 OPERATION VME HOLDOFF If the Transmit FIFO becomes full, subsequent READ or WRITE cycles to SCRAMNet memory will be extended until the Transmit FIFO is no longer full (see paragraph 4.10.5 for more information). SHARED-MEMORY WRITE SCRAMNet shared-memory is based upon a 32-bit word. If an 8- or 16-bit WRITE occurs from the host system, then the 32-bit word that contains that 8- or 16-bit WRITE is sent on the network.

  • Page 34: Table 4-3 Acr Functions

    OPERATION Table 4-3 ACR Functions Function Receive Interrupt Enable (RIE) Transmit Interrupt Enable (TIE) External Trigger 1 External Trigger 2 HIPRO Location Enable Reserved If these ACR actions are disabled, then no action will be taken when an interrupt condition exists unless override bits are set in CSR0 or CSR8. The external trigger and/or interrupt action and/or HIPRO mode for a particular shared- memory location is defined by setting these bits.

  • Page 35: Table 4-4 Interrupt Controls

    OPERATION 4.6 Interrupt Controls SCRAMNet allows a processor to receive interrupts from and/or transmit interrupts to any other processors on the network, including the originating processor. Table 4-4 indicates the various sources for interrupt control. 4.6.1 Interrupt Options Table 4-4 Interrupt Controls CONDITION REGISTER DESCRIPTION...
  • Page 36 OPERATION SEND/RECEIVE WITH INTERRUPTS • Set CSR0 to ‘0010’ to enable the Auxiliary Control RAM (ACR). • Clear the SCRAMNet ACR by writing zeros to the entire address range. • Set the SCRAMNet ACR locations that you wish to receive and/or transmit interrupts.

  • Page 37: Figure 4-2 Transmit Interrupt Logic

    OPERATION HOST WRITE TRANSMIT ENABLE CSR0, BIT 1 MUST BE ACTIVE CSR0 BIT 9 OVERRIDE TIE BIT 1 CSR0 BIT 8 NETWORK INTERRUPT ENABLE TRANSMIT TRANSMIT INTERRUPT SLOT TO NON-INTERRUPT NETWORK SLOT TO NETWORK Figure 4-2 Transmit Interrupt Logic Copyright 1995, S Corp.
  • Page 38 OPERATION The host issues a WRITE to SCRAMNet shared memory. If Override TIE (CSR0, bit 9) or ACR TIE (ACR, bit 1) is set and Network Interrupt Enable (CSR0, bit 8) is set, then the interrupt message is transmitted (INT = 1). Otherwise, the message is transmitted without the interrupt bit set (INT = 0).

  • Page 39: Figure 4-3 Receive Interrupt Logic

    OPERATION RECEIVE ENABLE CSR0, BIT 0 MUST BE ACTIVE CSR1 NETWORK MESSAGE PACKET ERROR CSR0 CSR2 BIT 7 BIT 9 WRITE NATIVE INT ON ERRORS SLOT CSR2 BIT 10 ENB INT ON Rx IN OWN SLOT CSR0 BIT 6 OVERRIDE BIT 0 CSR0 BIT 5...

  • Page 40: Table 4-5 Interrupt Error Conditions

    OPERATION 4.7.2 Network Error The second interrupt condition is designed to intercept network errors. CSR1 contains the following error conditions which may be masked by CSR9: Table 4-5 Interrupt Error Conditions Interrupt Transmit FIFO Full Transmit FIFO Not Empty Transmit FIFO O Full (Not masked for errors) Interrupt FIFO Full Protocol Violation...
  • Page 41 OPERATION 4.7.3 Interrupt Handling The Interrupt FIFO is accessed via CSR4 and CSR5. CSR5 contains the most significant seven bits of the 23-bit SCRAMNet interrupt address and CSR4 contains the remaining 16 bits of the interrupt address. (The 23-bit address allows for future expansion of memory).

  • Page 42: Table 4-6 General Purpose Counter/Timer Modes

    OPERATION be set to override the counter/timer mode settings and allow the counter/timer to run free at 26.66 ns (37.5 MHz). CSR9, bit 12 can be set to generate an interrupt upon overflow of the counter/timer. The output from the event counter/timer is stored in CSR13. See Section 5, page 5-7, 5-13, and 5-16 for more information.
  • Page 43 OPERATION unchanged data values out on the network. This feature is a type of data filtering and can be enabled without affecting node latency while improving network throughput. See Figure 4-4, page 4-18. Two bits in CSR0 control the operation of data filtering (see Section 5 for details of CSR operation): •...

  • Page 44: Figure 4-4 Data Filter Logic

    OPERATION DATA FILTER LOGIC NOTHING WRITE HOST DATUM SAME DATUM WRITE TO MEMORY READ SHARED MEMORY NETWORK RING NETWORK RING NETWORK LOGIC Figure 4-4 Data Filter Logic Copyright 1995, S Corp. 4-18 VME3U H/W REFERENCE...
  • Page 45 OPERATION READ The HIPRO READ is controlled by CSR16. This register is CSR enabled and ACR location selectable. CSR16, bit 0 ON - HIPRO READ enabled for every longword address location. CSR16, bit 1 ON - HIPRO READ enabled for all ACR selected HIPRO WRITE locations only.

  • Page 46: Figure 4-5 Monitor And Bypass Mode

    OPERATION MONITOR AND BYPASS MODE This mode permits the node to receive data only. Network data is not re-transmitted. Table 4-7 Monitor and Bypass Mode States State Register Setting Receive Enable CSR0, bit 0 Transmit Enable CSR0, bit 1 Insert Enable CSR0, bit 15 Enable Wire Loopback CSR2, bit 7...

  • Page 47: Figure 4-6 Wire Loopback Mode

    OPERATION WIRE LOOPBACK MODE The Wire loopback permits testing of the internal circuitry and needs no manual external modifications to work. In this mode, the transmitted signal does not leave the board. Table 4-8 Wire Loopback Mode States State Register Setting Receive Enable CSR0, bit 0...

  • Page 48: Figure 4-7 Mechanical Switch Loopback Mode

    OPERATION MECHANICAL SWITCH LOOPBACK MODE This mode permits testing of all circuitry up to and including the Media Card. Table 4-9 Mechanical Switch Loopback Mode States State Register Setting Receive Enable CSR0, bit 0 Transmit Enable CSR0, bit 1 Insert Enable CSR0, bit 15 Enable Wire Loopback CSR2, bit 7...

  • Page 49: Table 4-10 Fiber Optic Loopback Mode States

    OPERATION FIBER OPTIC LOOPBACK When this mode is invoked, the output of the transmitter is connected by fiber optics directly to the input of the receiver, and the receiver is disconnected from the network. Table 4-10 Fiber Optic Loopback Mode States State Register Setting...

  • Page 50: Figure 4-8 Fiber Optic Loopback Mode

    OPERATION Figure 4-8 Fiber Optic Loopback Mode The optional Fiber Optic Bypass switch must be installed for this to work. However, in the absence of the Fiber Optic Bypass switch, fiber optic cables could be run from the node s transmitter output connectors to the receiver input connectors. This configuration, with Insert Node enabled, would constitute a fiber optic loopback mode for stand-alone testing.

  • Page 51: Figure 4-9 Insert Mode

    OPERATION Fiber Optic Bypass Switch Conv Conv Media Card Internal Figure 4-9 Insert Mode 4.10.5 VME Holdoff Mode To enable VME Holdoff, set CSR8, bit 1 OFF. The VME Holdoff feature automatically slows down CPU data WRITEs to the SCRAMNet memory when the Transmit FIFO becomes full.
  • Page 52 OPERATION Figure 4-10 Quad Switch Copyright 1995, S Corp. 4-26 VME3U H/W REFERENCE...
  • Page 53 OPERATION In the event that the Transmit FIFO becomes full, the hardware will automatically extend the next VME write cycle until the Shared-memory FIFO empties at least one message. This prevents the loss of any data and is transparent to the user. 4.10.6 Write-Me-Last Mode The Write-Me-Last mode of operation allows the originating node to be the last node in the ring to have the data deposited to its memory.

  • Page 54: Figure 4-11 Interrupt Service Routine

    OPERATION CSR0 MME and HIE must be set in order to re-arm interrupts. CSR1 Bits 0-15 contain various error and status conditions. Interrupts are re-armed whenever any value is written to CSR1. CSR4 Bits 0-15 contain the interrupt address bits A0-A15. CSR5 Bits 0-6 contain the interrupt address bits A22-A16.
  • Page 55 5. 0 CSR DESCRIPTIONS 5.1 Description This section describes each Control/Status Register and the function of each bit. The name of each bit is indicative of its set state. The registers are described using bit 0 as the Least Significant Bit (LSB). For example: Inserting A7C3 in a 16-bit register would set bits 0, 1, 6, 7, 8, 9, 10, 13, and 15 ON.
  • Page 56 CSR DESCRIPTIONS Table 5-1 CSR0 Bits General SCRAMNet+ Enable and Reset (READ/WRITE) Network Communications Mode - Bit 0 controls the receive enable, and Bit 1 controls the transmit enable. None - In this mode, all communications between the node shared memory and the network is inhibited.
  • Page 57 CSR DESCRIPTIONS Table 5- CSR0 (Continued) Bits General SCRAMNet+ Enable and Reset (READ/WRITE) Auxiliary Control RAM Enable - When this bit is set, the ACR bytes are swapped in place of the corresponding least-significant byte of every four-byte word in SCRAMNet memory.
  • Page 58 CSR DESCRIPTIONS Table 5-1 CSR0 (Continued) Bits General SCRAMNet+ Enable and Reset (READ/WRITE) Enable Transmit Data Filter - When clear, the entire address space is not filtered and the node is capable of transmitting all messages written to the node shared memory by the host on the network.
  • Page 59 CSR DESCRIPTIONS Table 5-2 CSR1 Bits Error Indicators (READ Only with WRITE/RESET for interrupts) Reading CSR1 will reset the latched error conditions by clearing bits 0,2,4,6,7,8,9,10,11,12,13. Transmit FIFO Full (Latched) - When this bit is set, the Transmit-FIFO-Full condition exists. This occurs when there is more data coming from the host to the network than the network can absorb.
  • Page 60 CSR DESCRIPTIONS Table 5-2 CSR1 (continued) Bits Error Indicators (READ Only with WRITE/RESET for interrupts) Redundant Transmit/Receive Fault (Latched) - This bit is set if the currently selected optional redundant transceiver has faulted and reverted to the other link. The default value is ‘0’ General Purpose Counter/Timer Overflow (Latched) - This bit toggles a 16-bit counter/timer.
  • Page 61 CSR DESCRIPTIONS Table 5-3 CSR2 Bits Node Control (READ/WRITE) These bits are related to lines connected through the MUX control port and are available to the host interface. They are not required to connect to anything Disable Fiber Optic Loopback - When this bit is ‘0’ (power up default), the output of the transmitter is connected by fiber optics directly to the input of the receiver, and the receiver is disconnected from the network.
  • Page 62 CSR DESCRIPTIONS Table 5-3 CSR2 (continued) Bits Node Control (READ/WRITE) Variable Length Messages on Network - When ON, this bit enables variable length messages. It is used in conjunction with CSR2, bits 11, 14 and 15 to enable PLUS mode communication protocols (see below).
  • Page 63 CSR DESCRIPTIONS Table 5-4 CSR3 Bits Node Information (READ ONLY) Node Number Count - These bits represent the total number of SCRAMNet nodes on the network. This value is dynamically determined by the hardware and ranges from 0 to 255 depending upon the number of nodes actually on the network.
  • Page 64 CSR DESCRIPTIONS Table 5-7 CSR6 Bits External Control Status Register (READ/WRITE) Interrupt Vector - This host specific register stores the VMEbus interrupt vector for the interrupt generated by a Memory Update. This register must be pre-loaded with the vector before interrupt processing can occur. * 15-0 Reserved.
  • Page 65 CSR DESCRIPTIONS Table 5-9 CSR8 Bits General SCRAMNet+ Extended Control Register ID Multiplex - When set to 1, CSR3 contains the T_AGE and RXID fields. Disable Holdoff - When set, this bit disables the HOLDOFF feature. These bits are used for programming the EEPROM. CSR Reset - Setting this bit will cause bus errors.
  • Page 66 CSR DESCRIPTIONS Table 5-10 CSR9 Bits SCRAMNet Interrupt On-Error Mask* Transmit FIFO Full Mask Transmit FIFO not Empty Mask Transmit FIFO 7/8 Full Mask Built In Self Test Stream (BIST) - Internal 82-bit BIST shift register output. Interrupt FIFO Full Mask Protocol Violation Mask Carrier Detect Fail Mask Bad Message Mask...
  • Page 67 CSR DESCRIPTIONS Table 5-11 CSR10 Bits SCRAMNet+ Replicated Shared Memory Address (LSW) SMA_ENABLE Shared Memory Address Enable. This bit enables the on-ASIC comparator for shared-memory access. 11-1 Always zero SMA12 SMA13 Shared Memory Address SMA14 SMA15 Table 5-12 CSR11 Bits SCRAMNet+ Replicated Shared Memory Address (MSW) SMA16 SMA17...
  • Page 68 CSR DESCRIPTIONS Table 5-13 CSR12 Bits SCRAMNet Virtual Paging Register Virtual Paging Enable. When ON, this bit enables Virtual Paging. Always zero VP_A12 VP_A13 VP_A14 VP_A15 VP_A16 Virtual Page number. The significance of this register is dependent on the VP_A17 memory size.
  • Page 69 CSR DESCRIPTIONS Table 5-14 CSR13 Bits General Purpose Counter/Timer RD_COUNT[0] RD_COUNT[1] RD_COUNT[2] RD_COUNT[3] RD_COUNT[4] RD_COUNT[5] RD_COUNT[6] This is a General Purpose Counter/Timer register. It can be used to RD_COUNT[7] count trigger 1 and 2 events, count errors, or other events as RD_COUNT[8] programmed by CSR9, bits 13 and 14.
  • Page 70 CSR DESCRIPTIONS Table 5-15 CSR14 Bits External Control Status Register 15-0 Reserved Table 5-16 CSR15 Bits VME Interrupt Priority Level (IRQ) External Control Status Register Not Used This is a 7-bit wide, host-specific, READ/WRITE register that holds the VME Interrupt Priority Level (IRQ) Bits reflect the Interrupt Priority Level.
  • Page 71 CSR DESCRIPTIONS Table 5-17 CSR16 Bits HIPRO READ Control Bits Register (External Control Status Register) This is a 2-bit wide, High Performance (HIPRO) READ Control Bits Register. Only bits 1 and 0 are valid. BIt 1 BIt 0 HIPRO READ enabled HIPRO READ ACR enabled Bit 0 is CSR enabled.
  • Page 72 CSR DESCRIPTIONS This page intentionally left blank. Copyright 1995, S Corp. 5-18 VME3U H/W REFERENCE...

  • Page 73: Figure 6-12 Vme3U Layout

    6. 0 PHYSICAL FEATURES Figure 6-12 VME3U Layout Copyright 1995, S Corp. VME3U H/W REFERENCE...
  • Page 74 PHYSICAL FEATURES 6.1 CSR Address Switches (S1-S5) Hexadecimal rotary switches S1 through S5 are used to set the CSR address. Switch S1 contains the Most Significant Byte (MSB) and switch S5 contains the Least Significant Byte (LSB). 6.2 Resolution Bus Switch (S6) The Hexadecimal rotary switch S6 is used to designate the host interface bus to be used for CSR addressing and the bus to be used for memory.
  • Page 75 PHYSICAL FEATURES 6.9 EEPROM READ (J304) Enable to READ EEPROM on power-up. Disable to prevent READ. 6.10 Mezzanine Memory Card Connection (J305) Shared memory is mounted on a mezzanine board. If no additional memory was ordered, there will not be a mezzanine board. 6.11 LED Status Indicators 6.11.1 Insert The green Insert LED is ON when the node is Inserted into the SCRAMNet...
  • Page 76 PHYSICAL FEATURES This page intentionally left blank. Copyright 1995, S Corp. VME3U H/W REFERENCE...

  • Page 77: Appendix Acsr Summary

    APPENDIX A CSR SUMMARY TABLE OF CONTENTS A.1 CSR0 - General SCRAMNet Enable and Reset..........A-1 A.2 CSR1 - SCRAMNet Error Indicators..............A-2 A.3 CSR2 - General SCRAMNet Control ..............A-3 A.4 CSR3 - Number of Nodes & Node ID ..............A-4 A.5 CSR4 - Interrupt FIFO Address (LSW)..............
  • Page 79 CSR SUMMARY A.1 CSR0 - General SCRAMNet Enable and Reset Function Name Receive Enable RX_ENB Transmit Enable TXEN Redundant TxRx Toggle Host Interrupt Enable Auxiliary Control RAM Enable ACRE Interrupt on Memory Mask Match Enable IMME Override RIE Flag Interrupt on Errors Network Interrupt Enable Override TIE Flag Enable Tx Data Filter...
  • Page 80 CSR SUMMARY A.2 CSR1 - SCRAMNet Error Indicators Function Name Transmit FIFO Full TXFF Transmit FIFO Not Empty TXFNE Transmit FIFO _ Full TXFAF (Always 0) Not Used Interrupt FIFO Full Protocol Violation Carrier Detect Failure Bad Message Receiver Overflow Transmit Retry TXRTY Transmit Retry Time-out...
  • Page 81 CSR SUMMARY A.3 CSR2 - General SCRAMNet Control Function Name Available to Host Disable Fiber Optics Loopback FO_DIS Enable Wire Loopback EN_WR_LPB Disable Host to SM Write DIS_H_M_WR Enable Write of Our Own Slot to Memory WOSEN Enable Interrupt on Receipt of Own Interrupt IOSEN Slot 1024 vs 256 variable size max (bytes)
  • Page 82 CSR SUMMARY A.4 CSR3 - Number of Nodes and Node ID Function Name Node Number Count (Valid After a Transmission from the Node) NID0 NID1 NID2 Node ID Number NID3 NID4 NID5 NID6 NID7 Copyright 1995, S Corp. VME3U H/W REFERENCE...
  • Page 83 CSR SUMMARY A.5 CSR4 - Interrupt Address (LSW) Function Name Always = 0 Always = 0 RFA2 RFA3 RFA4 RFA5 Interrupt FIFO Address Field (LSW) RFA6 RFA7 RFA8 RFA9 RFA10 RFA11 RFA12 RFA13 RFA14 RFA15 Copyright 1995, S Corp. VME3U H/W REFERENCE...
  • Page 84 CSR SUMMARY A.6 CSR5 - Interrupt Address (MSW) and Status (READ Only*) Function Name RFA16 RFA17 RFA18 Interrupt FIFO Address Field (MSW) RFA19 RFA20 RFA21 RFA22 13-7 Reserved Retry Bit in Interrupt FIFO (RF_RETRY) Interrupt FIFO Not Empty (~RX_F_E) WRITE the Transmit Time-out value to CSR5 and it will be stored in shadow memory.
  • Page 85 CSR SUMMARY A.9 CSR8 - General SCRAMNet Extended Control Register Function Name 1 is CSR3=T_AGE & RXID fields ID_MUX Disable HOLDOFF feature DIS_HOLD Chip select to EEPROM CSR_CS0 Ext. Chip Select for AUX MICROWIRE CSR_CS1 peripheral MICROWIRE DOUT pin CSR_DOUT EEPROM program enable E_PRE CLK line to MICROWIRE port...
  • Page 86 CSR SUMMARY A.10 CSR9 - SCRAMNet Interrupt-On-Error Mask Function Name Transmit FIFO Full mask M_TX_F_F Transmit FIFO Not Empty mask M_TX_F_E Transmit FIFO 7/8 Full Mask M_TX_F_AF Internal 82 bit BIST shift register output BIST_STREAM Receiver FIFO Full Mask M_RX_F_F Protocol Violation mask M_PV Carrier Detect Fail mask...
  • Page 87 CSR SUMMARY A.11 CSR10 - SCRAMNet Shared Memory Address (LSW) Function Name Enable comparator for SM access SMA_ENABLE 11-1 Reserved SMA12 Shared Memory Address SMA13 SMA14 SMA15 A.12 CSR11 - SCRAMNet Shared Memory Address (MSW) Function Name SMA16 SMA17 SMA18 Shared Memory Address SMA19 SMA20...
  • Page 88 CSR SUMMARY A.13 CSR12 - SCRAMNet Virtual Paging Register (Refer to Section 4, paragraph 4.2.1, and Section 5, page 5-15 for additional information) Function Name Enables Virtual Paging when set Always ‘0’ VP_A12 VP_A13 VP_A14 VP_A15 Virtual Page Number VP_A16 VP_A17 VP_A18 VP_A19...
  • Page 89 Counter/Timer register RD_COUNT[15] A.15 CSR14 - External Control Status Register A 16-bit, READ Only SYSTRAN reserved register. A.16 CSR15 - VME Interrupt Priority Level (IRQ) External Control Status Register A 7-bit, READ/WRITE register that holds the VME Interrupt Priority Level (IRQ).
  • Page 90 CSR SUMMARY A.18 Auxiliary Control RAM (R/W) Function Name Receive Interrupt Enable Transmit Interrupt Enable External Trigger 1 (Host Read/Write) External Trigger 2 (Network Write) HIPRO HIPRO Reserved Copyright 1995, S Corp. A-12 VME3U H/W REFERENCE...
  • Page 91 APPENDIX B CABLE KIT TABLE OF CONTENTS B.1 Introduction ..........................B-1 B.2 Cable Connections ........................B-1 B.2.1 Cabinet Kit Connections..................B-2...
  • Page 93 CABINET KIT B.1 Introduction The cabinet kit for the SCRAMNet+ Network board permits adapting the node to the host cabinet while still maintaining the shielding of the chassis. B.2 Cable Connections Connections between the cabinet kit bulkhead plate and the SCRAMNet+ Network board are shown in Figure B-1.
  • Page 94 CABINET KIT B.2.1 Cabinet Kit Connections Figure B-1 Cabinet Kit Connections Copyright 1995, S Corp. VME3U H/W REFERENCE...

  • Page 95: Appendix Cspecifications

    APPENDIX C SPECIFICATIONS TABLE OF CONTENTS C.1 Hardware Specifications ........................C-1 C.2 Bus Voltage Specifications ........................C-2 C.3 Part Number ............................C-2 C.4 Board Dimensions..........................C-3 C.5 Fiber Optic Bypass Switch........................C-4...

  • Page 97: Hardware Specifications

    SPECIFICATIONS C.1 Hardware Specifications Hardware Compatibility: VMEbus Physical Dimensions: VME3U Card 6.299" x 3.937" 3U Eurocard, one slot Weight: VME3U Card 0.3 lbs (W/O SIMMs and Media Card, W/face plate) Media Card, Fiber Optic 0.0915 lbs Electrical Requirements: +5 VDC, 1.5 Amps max. Storage Temperature Range: -40°...

  • Page 98: Bus Voltage Specifications

    -0.60 V/+0.36 V 50 Mv +5 V STDBY * +5 V dc standby +0.25 V/-0.125 V 50 Mv Ground Reference Not used by SCRAMNet+ VME3U C.3 Part Number The VME3U adapter part number is in the form: H-AS-D3VMEL2M-00 where: CODE DEFINITION Hardware...

  • Page 99: Board Dimensions

    SPECIFICATIONS C.4 Board Dimensions 6.299 1.300 .093 .100 .400 3.937 5.059 Figure C-1 VME3U Board Dimensions Copyright 1995, S Corp. VME3U H/W REFERENCE...

  • Page 100: Fiber Optic Bypass Switch

    SPECIFICATIONS C.5 Fiber Optic Bypass Switch Copyright 1995, S Corp. VME3U H/W REFERENCE...
  • Page 101 SPECIFICATIONS Figure C-2 Fiber Optic Bypass Switch Copyright 1995, S Corp. VME3U H/W REFERENCE...
  • Page 102 SPECIFICATIONS Figure C-3 Housing Dimensions Copyright 1995, S Corp. VME3U H/W REFERENCE...

  • Page 103: Appendix Dhost Access Timing

    APPENDIX D HOST ACCESS TIMING TABLE OF CONTENTS D.1 Introduction ........................... D-1 D.2 Dual-Port RAM Controller Module..................D-1 D.2.1 Contention ........................D-1 D.3 Host Interface Logic to Shared Memory/CSR............... D-2 D.3.1 ASIC-Internal CSR READ ..................D-2 D.3.2 ASIC-Internal CSR WRITE ..................D-3 D.4 Host Interface Logic to Host Specific CSR ................

  • Page 105: Introduction

    HOST ACCESS TIMING D.1 Introduction The SCRAMNet+ host access timing is comprised of three separate module timings. • Dual-Port RAM Controller (DPRC). • Host Interface Logic to shared memory/CSR. • Host Interface Logic to host-specific CSR. The first module allows shared memory to be updated by the high speed serial network without utilizing valuable CPU bus bandwidth.

  • Page 106: Host Interface Logic To Shared Memory/Csr

    HOST ACCESS TIMING D.3 Host Interface Logic to Shared Memory/CSR The second module is the actual host interface logic needed to interface the ASIC resources (memory and internal CSR) to the host CPU bus. This is the logic that translates all VME host transactions to SCRAMNet .

  • Page 107: Asic-Internal Csr Write

    HOST ACCESS TIMING DSx* HREQ HACK DTACK* AS to DSx 10 ns (per VME Spec.) DSx to HREQ 80 ns (Host Adapter time) HREQ 53 ns (Host Adapter time) End of HREQ to HACK 106 ns (DPRC thru HACK = 133 ns) HACK to DTACK 22 ns (Host Interface)

  • Page 108: Host Interface Logic To Host Specific Csr

    HOST ACCESS TIMING D.4 Host Interface Logic to Host Specific CSR ASIC RESOURCES HOST LOGIC HOST DTACK SPECIFIC RESOURCES Figure D-4 Non-ASIC Resources The third module is the actual host logic needed to interface the non-ASIC resources (external host-specific CSR) to the host CPU as depicted in Figure D-4. The Interrupt Vector register is a non-ASIC resource.

  • Page 109: Access Times

    HOST ACCESS TIMING DSx* HREQ HACK DTACK* AS to DSx 10 ns (per VME Spec.) DSx to DTACK 186 ns (Host Adapter time) DTACK to End of Cycle 0 ns (per VME Spec.) 196 ns NOTE: There is no Host Request (HREQ) because this is not an ASIC resource Figure D-5 READ From External CSR D.5 Access Times Host access to shared memory is affected by two things:...

  • Page 110: Worst-Case Condition

    HOST ACCESS TIMING • Release bus (DTACK) • Requester/Host CPU de-assert DSx and AS (End of Cycle) WRITE • Address Strobe (AS) and Data Strobe fall (Start of cycle) • Host Request (HREQ) asserted • DPRC buffer data and address •...

  • Page 111: Back-To-Back Host Reads

    HOST ACCESS TIMING GENERATED EFFECTS The effect of the above setup will result in: • Back-to-Back Host READs. In this case, the “worst case” timing would occur where two Network WRITE operations will stretch the second host READ operation. The third and fourth host READ operations will toggle between network WRITE operations.
  • Page 112 HOST ACCESS TIMING DSx* HREQ HACK DTACK* Cycle #1 1. AS to DSx 10 ns (per VME Spec.) 2. DSx to HREQ 80 ns (Host Adapter time) 3. HREQ 6 ns (Host Adapter time) 4. End HREQ to End HACK 133 ns DPRC) 5.

  • Page 113: Back-To-Back Host Writes

    HOST ACCESS TIMING DTACK is de-asserted; AS, DSx de-asserted - End of Cycle. SECOND CYCLE AS, DSx fall - Start of Cycle (80 ns delay to decode address). HREQ asserted - READ request to DPRC. Host interface logic sleeps until HACK is received from DPRC (Maximum READ Time) DPRC is processing two Network WRITEs.
  • Page 114 HOST ACCESS TIMING FIRST CYCLE AS, DSx fall - Start of Cycle (106 ns delay to decode address). HREQ asserted - WRITE request to DPRC DPRC asserts HREQ_PEND Request accepted DPRC buffers data DPRC asserts HACK. Host linterface logic generates DTACK 53 ns later. AS and DSx are de-asserted.

  • Page 115: Appendix Econfiguration Aids

    APPENDIX E CONFIGURATION AIDS TABLE OF CONTENTS...
  • Page 117 CONFIGURATION AID SCRAMNet CONTROL/STATUS REGISTERS REFERENCE SHEET CSR 0 CSR 2 CSR 4 CSR 6 always 0 RX ENB available to host data intrpt vector always 0 TX ENB available to host data intrpt vector REDUND LINK TOGGLE available to host RFA 2 data intrpt vector HOST INT ENB...
  • Page 118 CONFIGURATION AID CSR 8 CSR 10 CSR 12 CSR 14 AGE & RXID MUX SM ACCESS ENB VIRT PG ENB reserved HOLDOFF DISABLE reserved always 0 reserved CHP SELECT EEPROM reserved always 0 reserved AUX MICROWIRE reserved always 0 reserved MICROWIRE DOUT reserved always 0...
  • Page 119 CONFIGURATION AID SCRAMNet NETWORK CONFIGURATION DATA SHEET MEMORY NODE HOST MEMORY SCRAMNet ADDRESS ADDRESS MACHINE SIZE LEVEL SERIAL # & BUS & BUS Copyright 1995, S Corp. VME3U H/W REFERENCE...
  • Page 120 CONFIGURATION AID This page intentionally left blank. Copyright 1995, S Corp. VME3U H/W REFERENCE...

  • Page 121: Appendix Facronyms

    APPENDIX F ACRONYMS...
  • Page 123 ACRONYM Acknowledge or acknowledgment Auxiliary Control RAM Address Strobe number BIST Built-In Self Test Block Transfer Control/Status Register DPRC Dual Port RAM Controller Data Strobe # DTACK Data Transfer Acknowledgment Data Transfer Bus Error Correction Mode FDDI Fiber Distributed Data Interface FIFO First-In, First-Out data buffer Fiber Optic Bypass...
  • Page 124 ACRONYM This page intentionally left blank. Copyright 1995, S Corp. VME3U H/W REFERENCE...

  • Page 125: Appendix Gglossary

    APPENDIX G GLOSSARY...
  • Page 127 GLOSSARY A16. A type of module that provides or decodes an address on address lines A01 through A15. A24. A type of module that provides or decodes an address on address lines A01 through A23. A32. A type of module that provides or decodes and address on address lines A01 through A31. auxiliary control RAM (ACR).
  • Page 128 GLOSSARY master does not release the DTB until all of the bytes have been transferred. It differs from a string of read cycles in that the master broadcasts only one address and address modifier (at the beginning of the cycle.) Then the slave increments this address on each transfer so that the data for the next cycle is retrieved from the next higher location.
  • Page 129 GLOSSARY (3) An interrupt handler that receives 32-bit status/ID over D00-D31, or (4) An interrupter that sends 32-bit daisy-chain. A special type of signal line that is used to propagate a signal level from board to board, starting with the first slot and ending with the last slot. These are four bus grant daisy-chains and one interrupt acknowledge daisy-chain on the backplane.
  • Page 130 GLOSSARY interrupt acknowledge cycle. A DTB cycle, initiated by an interrupt handler, that reads a status/ID from an interrupter. An interrupt handler generates this cycle when it detects an interrupt request from an interrupter and it has control of the DTB. interrupter.
  • Page 131 GLOSSARY platinum+. (Also platinum plus). A variable packet size enhancement for the platinum protocol. Maximum packet size may be set to either 256 bytes or 1024 bytes. power monitor. A functional module that monitors the status of the primary power source to the system and signals when the power has strayed outside the limits required for reliable system operations.
  • Page 132 GLOSSARY serial clock driver. A functional module that provides a periodic timing signal that synchronizes the operation of the IEEE 1132* serial bus. Timing specifications for the serial clock driver of the IEEE 1132 are given in Appendix C. Two backplane signal lines are reserved for use by a serial bus. However, the protocols of the serial bus are completely independent of the IEEE 1014, and the inclusion of a serial bus is not a required feature of the IEEE 1014.
  • Page 133 GLOSSARY VME address space. The VME address space varies according to specific VME device and is identified as A16, A24, or A32 space. A32 is the largest address space; it allows up to 4 gigabytes of space using 32 bit addresses. A24 space uses 24 bit addresses, and A16 space uses 16 bit addresses. VMEbus.
  • Page 134 GLOSSARY This page intentionally left blank. Copyright 1995, S Corp. VME3U H/W REFERENCE...

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