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Synaptic Labs'
HyperBus Memory Controller (HBMC)
Tutorial
T001A: A Qsys based Nios II Reference design with a
simple self test of the HyperFlash and HyperRAM device
using S/Labs' HBMC IP
This tutorial describes a simple reference design for S/Labs HBMC IP targeted specifically to Intel
Cyclone 10LP evaluation board or devboards GmbH HyperMAX 10M25 and 10M50 boards. Most
HBMC customers using any of these boards board will want to start with this tutorial. This tutorial
describes key aspects of a pre-configured .qsys reference project and then walks through the process of
generating and compiling that .Qsys project. This tutorial then describes how to compile the example
Nios II source code, integrate the firmware into the FPGA bitstream and then run the reference design
on the development board.
After completing this tutorial, readers may like to proceed to the second tutorial called "T001B: A
Qsys based Nios II reference design with a simple Memory Bandwidth Benchmark of the HyperRAM
device usng S/Labs' HBMC IP". This tutorial shows how to download the Nios II firmware into the
FPGA device using the Nios II development environment.
Synaptic Labs 2017
i nfo@synaptic-labs.com
V5.3
page 1
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Table of Contents
Summary of Contents for Synaptic Laboratories HyperBus
- Page 1 Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial T001A: A Qsys based Nios II Reference design with a simple self test of the HyperFlash and HyperRAM device using S/Labs' HBMC IP This tutorial describes a simple reference design for S/Labs HBMC IP targeted specifically to Intel Cyclone 10LP evaluation board or devboards GmbH HyperMAX 10M25 and 10M50 boards.
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Page 2: Table Of Contents
4. Explore and configuring the reference Qsys project................8 4.1 Components employed in the reference project...................8 4.2 Nios II/f processor configuration......................9 4.3 Configuring S/Labs HyperBus Memory Controller................10 4.4 Configuration of Altera’s On-Chip Memory..................16 5. Generating the Qsys Design.........................17 6. Preparing the firmware.........................18 6.1 Open the NIOS II Software Built Tools for Eclipse................18... -
Page 3: Set-Up Requirements
◦ Extract to: C:\HyperMAX_lab\ Step 2: License Setup 1. Next you need to apply for Synaptic Labs' HyperBus Memory Controller license. You can skip this step if you already installed the license at some earlier stage. Free enrollment can be obtained from: http://opencore_license_001.synaptic-labs.com/... -
Page 4: Step 3: Install Hbmc Qsys Component Into The Project Ip Folder
Instructions. Step 3: Install HBMC Qsys Component into the project IP Folder 1. In this tutorial we assume that S/Labs HyperBus Memory Controller (HBMC) will be located in the Project directory. a. Other Qsys component installation methods are described in the above mentioned installation Guides. - Page 5 Step 4: Cyclone 10 LP Development Board DIP Switches You have the Cyclone 10 LP evaluation board and mini USB cable provided. Note: the board is powered over USB so no power supply is required. Ensure that DIP Switch 4 on the Cyclone 10 board is set to ON, this bypasses the virtual JTAG system and simplifies board programming.
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Page 6: Contents Of The Reference Project
S/Labs’ TestMbs memory bandwidth benchmark for HyperRAM program which is used • in the HBMC Tutorial 002. Note: Synaptic Labs' HyperBus Memory Controller (HBMC) IP can ONLY be simulated with Altera's Modelsim Simulator. Please contact Synaptic Labs for a simulation model if required. Synaptic Labs 2017 i nfo@synaptic-labs.com... -
Page 7: Open The Reference Quartus Project
2. Open the reference Quartus Project In the menu bar of Quartus Prime, select File → Open Project… • Select the file NIOS_HyperRAM.qpf in the project directory • Click the [ Open ] button. • 2.1 Check the correct FPGA device is selected Every Quartus project is targeted to a specific FPGA device. -
Page 8: Open The Reference Qsys Project
3. Open the reference Qsys project In the menu bar of Quartus Prime, select Tools→Qsys • Select the file hypernios.qsys in the project directory • Click the [ Open ] button. • Synaptic Labs 2017 i nfo@synaptic-labs.com V5.3 page 8... -
Page 9: Explore And Configuring The Reference Qsys Project
The reference Qsys project in this tutorial employs a NiosII/f processor, Synaptic Labs' HyperBus Memory Controller (HBMC) IP, Altera’s On-chip Memory module to store code and data in on chip SRAM, and various peripherals such as Altera’s JTAG UART and timer modules as illustrated below. -
Page 10: Nios Ii/F Processor Configuration
This is done because: (a) the HyperBus protocol employs burst memory transfer requests with closed page mode of operation; and (b) SLL’s HBMC employs an Avalon interface with burst mode of operation. -
Page 11: Configuring S/Labs Hyperbus Memory Controller
HBMC IP supports any combination of HyperFlash and HyperRAM. Both editions offer preconfigured memory options for supported COTS FPGA development boards. The full edition of SLL HBMC IP also includes the option to manually configure the HyperBus devices. To configure the project to just use HyperRAM on the Intel C10LP/HyperMAX board: The FPGA board type field is set to either: •... - Page 12 …...for Devboards HyperMAX board …...for Intel Cyclone 10LP Evaluation Kit Synaptic Labs 2017 i nfo@synaptic-labs.com V5.3 page 12...
- Page 13 In the Clock and PLL Configuration Tab (Basic Edition (OpenCore) The Avalon and HyperBus clock configuration field is set to One clock • The HyperBus channel clock frequency field is set to 100 MHz • In the Clock and PLL Configuration Tab (Full Featured edition)
- Page 14 In the Ingress Avalon Slave 0 (IAVS0) configuration tab The IAVS0 port is used to access all HyperBus memories connected to the HyperBus Memory Controller IP. The most common configuration of the IAVS0 port is as follows: IAVS0: Ingress Avalon port stage...
- Page 15 HyperRAM), the following table will show the parameters, configuration and timing for the HyperFlash memory. Device 0 Configuration In this tutorial the Use factory default settings for this HyperBus device field is left • checked Synaptic Labs 2017 i nfo@synaptic-labs.com V5.3...
- Page 16 The Device1 Info Tab The table below will show the parameters, configuration and timing for the HyperRAM memory. Device 1 Configuration In this tutorial the Use factory default settings for this HyperBus device field is left • checked The exact parameters on your screen may be different because: The HyperMAX 10M25 board employs a 64 Megabit HyperRAM device.
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Page 17: Configuration Of Altera's On-Chip Memory
4.4 Configuration of Altera’s On-Chip Memory In this reference project, Altera's On-Chip Memory is configured as a 40 Kilobyte single port RAM. We will setup this memory to be initialized by the Nios II SBT for Eclipse Please ensure that: •... -
Page 18: Generating The Qsys Design
5. Generating the Qsys Design Once the Qsys project has been correctly configured, press the [ Generate HDL… ] button on the bottom right hand side of the Qsys window. Synaptic Labs 2017 i nfo@synaptic-labs.com V5.3 page 18... - Page 19 In the Synthesis section, set the Create HDL design files for synthesis field to Verilog. • In the Simulation section, set the Create simulation model field to None. • Then click on the [ Generate ] button. • You may see a Save System window. Click the [ Close ] button to close the save window. •...
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Page 20: Preparing The Firmware
6. Preparing the firmware 6.1 Open the NIOS II Software Built Tools for Eclipse In Quartus Prime, go to the menu bar and select • Tools → NIOS II Software Built Tools for Eclipse. MAX10_HyperNios_Project/software Click the [Browse…] button. A new file selector window will open. In this tutorial we •... -
Page 21: Create A Simple Application And Bsp
6.2 Create a simple application and BSP The software folder in the reference project is empty. This is because problems can be experienced when moving the Eclipse Workshop folder between Windows and Linux Systems. We need to create a Nios II application, and Nios II board support package for that Nios II application: In the Eclipse window, go the menu bar and select: •... - Page 22 hypernios.sopcinfo In the Target hardware information, click on the […] button • A file browser window will open. Locate and select the hypernios.sopcinfo file • generated by Qsys and stored in the project directory. Click [Open]. It may take around 30 seconds for the Eclipse application to parse the .sopcinfo file. •...
- Page 23 a HelloWorld application folder that contains the hello_world.c file. We will replace • that hello_world.c file with a custom program that tests the HyperRAM device later in this tutorial. a HelloWorld_bsp folder that contains the Nios II Board Support Package (BSP) •...
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Page 24: Configure The Board Support Package (Bsp)
6.3 Configure the Board Support Package (BSP) The Nios II BSP must be configured before we can compile the source code. In the Project Explorer tab, right click on: • HelloWorld_bsp → Nios II -> BSP Editor... Synaptic Labs 2017 i nfo@synaptic-labs.com V5.3 page 24... - Page 25 In the Main Tab of the BSP editor, in the panel on the left hand side, select: Settings → Common Set the sys_clk_timer field to timer_0 • This is used to generate a recurring system clock interrupt for the hardware abstraction layer.
- Page 26 In the Main Tab of the BSP editor, in the panel on the left hand side, select: Settings → Advanced → hal.linker For the purpose of this tutorial, the following configuration will generally work: Tick [x] allow_code_at_reset • Tick [x] enable_alt_load •...
- Page 27 Select the Linker Script Tab of the BSP editor. For this tutorial example, we are going to: Map the reset vector (.reset) to the onchip memory (onchip_memory2_0) . • This is generated by Qsys and depends on the location of the Nios II reset vector. Map the exception vector (.exceptions) to the onchip memory (onchip_memory2_0).
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Page 28: Generate The Bsp And Clean The Project
6.4 Generate the BSP and clean the project The software developer must re-generate the BSP every time the Qsys project is regenerated. This ensures that the device drivers and addresses of peripherals are reflected correctly in the hardware abstract library. To (re)generate the BSP: Go to the Nios II eclipse window. -
Page 29: Copy The Memory Testing Source Code
6.5 Copy the memory testing source code We now want to replace the original HelloWorld.c source code with software that checks • the HyperRAM. Copy and replace the files located in: ◦ HyperNios_Project/source/TestHyperRAM ◦ HyperNios_Project/software/HelloWorld In the project explorer window of Eclipse, right click on the HelloWorld folder. Then •... -
Page 30: Build The Nios Ii Application
6.6 Build the Nios II Application We now want to run the compiler and linker: Go to the Nios II eclipse window. • Go to the menu bar and select: • Project ->Build All If the project produces warning / error messages, you may need to build the project •... -
Page 31: Generate Memory Initialization Files
6.7 Generate memory initialization files If we want to embed the firmware into the on-chip SRAM when configuration the FPGA device using a FPGA bitstream, or if we wish to program the HyperFlash memories, we need to generate “memory initialisation” .hex files from the .elf file. In the Project Explorer tab, right click on: •... -
Page 32: Update The Memory Initialization Field(S) In Qsys
7. Update the memory initialization field(s) in Qsys Before synthesizing the design, it is important to ensure that the initialization file for the onchip- memory is set to the exact path of the .hex file in the Qsys project. This is because it is possible to create multiple applications within a Nios II Eclipse workspace. -
Page 33: Synthesize And Assemble The Design
8. Synthesize and assemble the Design Go to the Quartus Prime window. • In the menu bar, select: • Processing → Start Compilation Windows users, please note: If the compilation fails to start you may need to reduce the path length of your project folder. This is because some versions of Windows have a maximum path length of 260 characters which can be exceeded when compiling projects in Quartus Prime. -
Page 34: Program The Fpga Bitstream Into The Fpga Device
9. Program the FPGA Bitstream into the FPGA device Connect the HyperMAX/Intel C10LP Evaluation kit to the USB port of your computer • Open the Quartus Prime window • In the menubar, click on Tools then Programmer to start the Altera Programmer •... -
Page 35: Run The Nios2-Terminal Application
10. Run the nios2-terminal application In Linux: Open a Linux command shell / terminal • In Windows: Run the Nios II Command Shell application from the Windows start • menu. Run the nios2-terminal command from the terminal. • Messages similar to the one below should be displayed in the command shell. •...
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