Analog output & digital i/o module for the pc/104 bus (43 pages)
Summary of Contents for VersaLogic SPX-2
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Reference Manual DOC. REV. 4/7/2008 SPX-2 Sixteen-line Digital I/O Serial Peripheral Expansion (SPX™) Board...
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All Rights Reserved Notice: Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.
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Data sheets and manufacturers’ links for chips used in this product Utility routines and benchmark software This is a private page for SPX-2 users that can be accessed only be entering this address directly. It cannot be reached from the VersaLogic homepage.
Introduction Description The VersaLogic SPX-2 is a 16-channel digital I/O expansion module designed to be used with any SPX™ enabled base board. Its features include: Microchip MCP23S17 16-bit I/O Expander Compatible with any SPX enabled base board VersaLogic SPX boards are a line of I/O expansion boards using the industry standard Serial Peripheral Interface (SPI) bus.
Introduction Technical Specifications Specifications are typical at 25°C with 5.0V supply unless otherwise noted. Board Size: 1.2" x 3.775", SPX compliant Storage Temperature: -40° C to 85° C Free Air Operating Temperature: -40° C to +85° C Power Requirements: +5.0V ± 5% @ 9.0 mA (45 mW) typ., 155 mA (773 mW) max.
(PBDE) flame retardants, in certain electrical and electronic products sold in the European Union (EU) beginning July 1, 2006. VersaLogic Corporation is committed to supporting customers with high-quality products and services meeting the European Union’s RoHS directive.
If you are unable to solve a problem with this manual please visit the SPX Product Support web page listed below. If you have further questions, contact VersaLogic technical support at (541) 485-8575. VersaLogic technical support engineers are also available via e-mail at Support@VersaLogic.com.
Physical Details SPX-2 Board Layout The figure below shows the dimensions of the SPX-2 board, as well as the location of connectors, jumpers, and mounting holes. 3.775” 3.375” Slave Select 1.2” SPX to Base Board 0.39” Figure 1. SPX-2 Board Layout (Not to scale.
Physical Details ARDWARE SSEMBLY The SPX-2 mounts on two hardware standoffs using the corner mounting holes. These standoffs are secured to the board, typically across the PC/104 and PC/104-Plus stack locations, using pan head screws. Standoffs and screws are available as part number VL-HDW-101.
Physical Details Connector Functions and Interface Cables The following table shows the function of each connector, as well as mating connectors and cables. Table 1: Connector Functions and Interface Cables Mating Transition Cable Connector Function Connector Cable Description SPX to Base FCI 89361-714LF or CBR-1401 2 SPX Module Cable...
Input data can be inverted through register settings. Any I/O pin(s) can generate an interrupt on change of state. As outputs, the I/O pins drive at 3.3 volt CMOS levels. The SPX-2 I/O inputs are not 5 volt tolerant. Inputs have external 10k pull-ups to 3.3 volts.
RITING TO A IGITAL The SPX-2 can take advantage of the EBX-11 Rev 6 and above as well as the EBX-22 Rev 3 and above data streaming capability. See the MCP23S17 datasheet for information on Sequential Mode. The following code example initiates a write of 55h to SPX-2 I/O port bits GPA7-GPA0 using the standard 24-bit SPI frame with auto slave select.
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Digital I/O AL, 00h ;SPIDATA2: MCP23S17 register address 00h DX, AL DX, 1DDh AL, 40h ;SPIDATA3: MCP23S17 write command DX, AL CALL BUSY ;Poll busy flag to wait for SPI transaction ;Write 55h to MCP23S17 register GPIOA DX, 1DBh AL, 55h ;SPIDATA1: data to write DX, AL DX, 1DCh...
The following tables describe the SPI control and data registers of the EBX-11 Rev. 6.00 and later. This is the standard set of SPI registers for VersaLogic CPU boards with an SPX interface. See the reference manual for details and updates.
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Base Board SPI Registers SPISTATUS (READ/WRITE) 1D9h IRQSEL1 IRQSEL0 SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY Table 6: SPI Control Register 2 Bit assignments Mnemonic Description D7-D6 IRQSEL IRQ Select – These bits select which IRQ will be asserted when a hardware interrupt from a connected SPI device occurs.
Base Board SPI Registers SPI D EGISTERS SPIDATA0 (READ/WRITE) 1DAh MSbit LSbit SPIDATA1 (READ/WRITE) 1DBh MSbit LSbit SPIDATA2 (READ/WRITE) 1DCh MSbit LSbit SPIDATA3 (READ/WRITE) 1DDh MSbit LSbit SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this register will initiate the SPI clock and, if the MAN_SS bit = 0, will also assert a slave select to begin an SPI bus transaction.
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