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Summary of Contents for Vaisala MPU112
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TECHNICAL REFERENCE Main Processor Unit MPU112 M210829EN-A...
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The contents are subject to change without prior notice. Please observe that this manual does not create any legally binding obligations for Vaisala towards the customer or end user. All legally binding commitments and agreements are included exclusively in the applicable supply contract or Conditions of...
General Safety Considerations ..........4 ESD Protection..............5 Recycling .................. 5 CHAPTER 2 PRODUCT OVERVIEW.................. 7 Introduction to MPU112 Main Processor Unit ....... 7 CHAPTER 3 FUNCTIONAL DESCRIPTION............... 9 PC Core module ............... 9 Flash Disk ................10 CHAPTER 4 SYSTEM LOGIC PLD...................
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CHAPTER 8 TECHNICAL DATA ..................23 Control Processor ..............23 General ..................24 Connector Signal Layout ............25 CHAPTER 9 DIAGRAMS AND BOARD LAYOUTS ............27 Main Processor MPU112............27 CHAPTER 10 PARTS LIST ....................37 APPENDIX A CONNECTOR SIGNAL LIST................41 APPENDIX B FRONT PANEL CONNECTORS..............45 COM1 Connector ..............45 ETH1 and ETH2 Connectors..........45...
CHAPTER 1 GENERAL INFORMATION This chapter provides general notes for the product. About This Manual This manual provides information for the Vaisala Main Processor Unit MPU112. Contents of This Manual This manual consists of the following chapters: - Chapter 1, General Information, provides general notes for the product.
- Appendix B, Front Panel Connectors describes the MPU112 connectors. - Appendix C, List of Signals lists the signals used in the MPU112. Feedback Vaisala Customer Documentation Team welcomes your comments and suggestions on the quality and usefulness of this publication. If you find errors or have other suggestions for improvement, please indicate the chapter, section, and page number.
Chapter 1 ________________________________________________________ General Information ESD Protection Electrostatic Discharge (ESD) can cause immediate or latent damage to electronic circuits. Vaisala products are adequately protected against ESD for their intended use. However, it is possible to damage the product by delivering electrostatic discharges when touching, removing, or inserting any objects inside the equipment housing.
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Main Processor Unit MPU112. Introduction to MPU112 Main Processor Unit The MPU112 is an E1-sized module that controls the system functions and external communication. It comprises an E1-sized main circuit board and a Computer Module which is installed on the Carrier Board.
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TECHNICAL REFERENCE___________________________________________________________ Serial communication channels COM1-4 are used for external communication. The COM1-2 channels are from Computer module and COM3-4 channels are from PLD logic. ARCNET type local area network is used for the connection to other sounding system units. 8 ___________________________________________________________________ M210829EN-A...
The ISA bus is used for a flash type BIOS memory and system logic PLD connections. The IDE bus connects to an onboard ATA flash disk memory. The serial channel COM1 is used for diagnostics and the channel COM2 is used as a system interface. VAISALA ________________________________________________________________________ 9...
TECHNICAL REFERENCE___________________________________________________________ After reset, the processor starts the operation by executing the BIOS code in its internal flash memory. First, the BIOS code verifies the correct operation of the main system components. Then it transfers the further code execution to the SDRAM system memory. After BIOS is complete, the processor boots from ATA flash disk memory, loads code to PLD (Programmable Logic Device), and starts the execution of the actual application program.
This chapter provides information about the Programmable Logic Devices of the MPU112. Programmable Logic Device (PLD) The MPU112 contains two Programmable Logic Devices (PLDs) D14 and D17. Both devices are in-circuit configurable. The main device is D14 which is used to implement all required custom logic functions.
The resistors R64, R65, R79 and R73, R90, R94 are used to allow overriding of D16 outputs. The PLD D14 is used to implement the main timing, control, and interface logic functions in the MPU112. The PLD D14 includes the following main functions: ISA Bus Interface...
The PLD D14 contains a register for the device code (fixed to 13 hex) of the MPU112. The slot code and rack code of the MPU112 are read from the D14 inputs. The slot and rack codes depend on the external connections and are used to define the ARCNET node address of the MPU112.
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PCI bus connection; D21-B for Ethernet line connections; and D21-C for power connections. The controller is directly connected to the PCI bus of the Computer Module. The 25 MHz clock is connected from the 25 MHz clock oscillator Z2. VAISALA _______________________________________________________________________ 15...
TECHNICAL REFERENCE___________________________________________________________ The receive (E5ATD+/-) and transmit (E5ARD+/-) pairs of the Ethernet line are connected directly to the port 5 of the Ethernet switch. The EEPROM D11 is for programmable initialization parameters, which are automatically loaded to the controller registers at system reset or power up.
PWR# controls determine the data direction on the bus. Interrupt signal PINT# is connected to the PLD D14. The controller is connected to the network through the bi-directional differential Line Transceiver D2. The line is protected against voltage transients by bi-directional transient suppressors. VAISALA _______________________________________________________________________ 17...
(ARCTXEN# and ARCTX) are connected to the transmitter via PLD D14. Serial Channels The MPU112 has four serial channels for external serial communication. All channels have RS232 compatible line drivers and receivers. - Channels 1 and 2 are provided by the Computer Module. Both channels are supported by the internal baud rate generators.
The PLL D6 is not used. Its clock input, clock output and programming inputs are connected to the PLD D14 for possible future use. VAISALA _______________________________________________________________________ 19...
TECHNICAL REFERENCE___________________________________________________________ Voltage Regulators The linear voltage regulator A1 is used to generate required +2.5 V internal operating voltages from the +3.3 V system voltages. The linear voltage regulator A2 generates +3.3 V operating voltage (signal +3.3VCLK) for clock frequency components D6, D8, D27 and Test Input Input signal TESTX# from X1/b39 is connected via D9 to the PLD.
After the BIOS is complete, the processor boots from onboard ATA flash disk memory, loads the code to a PLD (Programmable Logic Device), changes the LED color from yellow to green and starts the execution of the actual application program. VAISALA _______________________________________________________________________ 21...
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Chapter 8 ____________________________________________________________ Technical Data CHAPTER 8 TECHNICAL DATA This chapter contains the MPU112 technical specifications. Control Processor Table 1 Technical Data for Control Processor Part Specification PC Module Processor type AMD Geode LX800 Clock rate 500 MHz Memory DDR SODIMM...
TECHNICAL REFERENCE___________________________________________________________ General Table 2 General Specifications Feature Specification Power requirements +3.3 V (±5%) 700 mA +5 V (±5%) 1600 mA Operating conditions Temperature 0 ... +55ºC standard –30 ... +55ºC extended Humidity Non-condensing Storage conditions Temperature –55 ... +80ºC Humidity Non-condensing Dimensions and mass...
FWGATE# O FHDSEL# +3.3 V +3.3 V +3.3 V +3.3 V +3.3 V FMTR0# O FDR0# O FDIR# O FSTEP# O FWDATA# +5 V +5 V +5 V +5 V +5 V FINDEX FTRK0 FWRPRT FRDATA FDCHG VAISALA _______________________________________________________________________ 25...
+5 V PDIAG# HD Pass Diagnostic +5 V c,d12 HCS0-1 HD Chip Select 0-1 +5 V DASP# HD Disk Active +5 V a,b18,d30,d31 ARC+/- ARCNET differential line Arcnet TxD6 Data output for serial channel 6, RS232 optional VAISALA _______________________________________________________________________ 41...
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TECHNICAL REFERENCE___________________________________________________________ Signal Description Level RxD6 Data input for serial channel 6, RS232 optional TxD5 Data output for serial channel 5, RS232 optional RxD5 Data input for serial channel 5, RS232 optional a,b24 E3Rx+/- Ethernet data input channel 3, Ethernet differential line d,e24 E3Tx+/-...
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Floppy Disk Write Protected, +5 V Rack2# for Arcnet address FRDATAR3# Floppy Disk Read Data, +5 V Rack3# for Arcnet address FDCHGR4# Floppy Disk Change, +5 V Rack4# for Arcnet address NOTE Signal marked by # are 0-level active. VAISALA _______________________________________________________________________ 43...
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Appendix B ____________________________________________________ Front Panel Connectors APPENDIX B FRONT PANEL CONNECTORS This chapter describes the MPU112 connectors. COM1 Connector Serial port COM1 Type of connector: 9 pin male D connector Corresponding cable connector: 9 pin female D connector Table 1...
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Appendix C ____________________________________________________________ List of Signals APPENDIX C LIST OF SIGNALS This chapter lists the signals used in the MPU112. The following signal names and abbreviations are used throughout the text and drawings of the MPU112: +2.5V +2.5 V operating voltage +3.3V...
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TECHNICAL REFERENCE___________________________________________________________ OCS0..2 Frequency setting input S0...2 OCV0...8 Frequency setting input V0...8 OP1...2P Output 1...2 from Computer Module OPX1...2 Output 1...2 OUTA...E3CP Serial data 3 output A...E from Computer Module PA0...2 Peripheral address 0 - 2 PAD0...7 Peripheral data 0 - 7 Parity Personal Computer PCAD00...31...
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VGAHXR VGA horizontal from buffer VGAR VGA red VGARR VGA red from Computer Module VGAV1 VGA vertical from Computer Module VGAVX VGA vertical sync VGAVXR VGA vertical from buffer VREF1...4 Voltage reference 1...4 ZWS# Zero wait state VAISALA _______________________________________________________________________ 51...
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