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PCI GRL-PCIE5-CEM-RXA Manual

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Granite River Labs
GRL-PCIE5-CEM-RXA PCI Express Card Electromechanical (CEM)
5.0 (32 GT/s)
Receiver Compliance Test Automation Solution User Guide and
MOI
Using GRL-PCIE5-CEM-RXA Automation Test Software,
Anritsu MP1900A BERT,
and
High Performance Oscilloscope
Published on 29 June 2022

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Summary of Contents for PCI GRL-PCIE5-CEM-RXA

  • Page 1 Granite River Labs GRL-PCIE5-CEM-RXA PCI Express Card Electromechanical (CEM) 5.0 (32 GT/s) Receiver Compliance Test Automation Solution User Guide and Using GRL-PCIE5-CEM-RXA Automation Test Software, Anritsu MP1900A BERT, High Performance Oscilloscope Published on 29 June 2022...
  • Page 2 All product names are trademarks, registered trademarks, or service marks of their respective owners. Copyright © 2022 Granite River Labs. All rights reserved. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 3: Table Of Contents

    TABLE OF CONTENTS 1 INTRODUCTION 2 RESOURCE REQUIREMENTS ....................12 QUIPMENT EQUIREMENTS ....................14 OFTWARE EQUIREMENTS 3 SETTING UP GRL-PCIE5-CEM-RXA AUTOMATION SOFTWARE GRL-PCIE5-CEM-RXA S ............... 15 OWNLOAD OFTWARE .................... 15 AUNCH AND OFTWARE ............18 ONFIGURE OFTWARE EFORE ALIBRATION ESTING 3.3.1...
  • Page 4 Test Summary Table ....................54 6.1.3 Test Results ......................54 ......................55 ELETE ESULTS 7 SAVING AND LOADING GRL-PCIE5-CEM-RXA TEST SESSIONS 8 APPENDIX A: METHOD OF IMPLEMENTATION (MOI) FOR MANUAL PCIE CEM 5.0 RECEIVER MEASUREMENTS ......................56 ERFORM ALIBRATION 8.1.1 Calibration Settings ....................
  • Page 5 Configuration of Re-Driver .................. 111 10.3.2 Connection Diagram ................... 111 10.3.3 Operation Guide ....................112 10.4 EQ S ....................113 ETTING PTIMIZATION GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 5 of 123...
  • Page 6 APPENDIX D: SIGTEST TOOL TAB APPENDIX E: DEBUG TOOL TAB APPENDIX F: CONNECTING KEYSIGHT OSCILLOSCOPE TO PC APPENDIX G: CONNECTING TEKTRONIX OSCILLOSCOPE TO PC GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...
  • Page 7 Figure 29. Recommended Setup for DUT Rx Compliance Testing (PCIe Gen 5 System Board) ..43 Figure 30. Recommended Setup for DUT Rx Compliance Testing (PCIe Gen 5 Add-In Card) ... 44 Figure 31. Set Up Test Requirements ....................45 GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 8 Figure 61. Setup Configuration Page ....................116 Figure 62. Perform Tx Link EQ Time Response Offline Tests Debugging ......... 116 Figure 63. Initiate Tx Link EQ Time Response Preset/Cursor Test ........... 117 GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 9 Figure 68. Oscilloscope’s VISA Address ..................... 121 Figure 69. OpenChoice Instrument Manager In Start Menu ............. 122 Figure 70. OpenChoice Instrument Manager Menu ................123 GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...
  • Page 10 Table 4. Calibration Parameters Description ..................30 Table 5. Test Parameters Description ....................48 Table 6. Calibration Settings ....................... 57 Table 7. Calibration Targets ......................... 57 GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 11: Introduction

    1 Introduction This user manual provides information using the GRL-PCIE5-CEM-RXA test automation solution to set up and test an electrical receiver (Rx) device to meet PCI Express Card Electromechanical (CEM) 5.0 compliance for 32 GT/s as per PCI Express (PCI-SIG) Standards.

  • Page 12: Resource Requirements

    56Gbaud Differential Linear Amplifier MACOM Technology Solutions Re-Driver For Return Path optimization in the System Tx/Rx Link Equalization Test GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 12 of 123...

  • Page 13: Table 2. Equipment Requirements - Cables

    Oscilloscope with scope bandwidth as specified in vendor specific MOI’s. MU181000B Option 02 is required for testing the System Board DUT. The GRL-PCIE5-CEM-RXA software supports PAM4 PPG in NRZ mode. The J1890A and AH54192A are packaged separately. Check the contents of both boxes. The AH54192A is supplied as a set with dedicated power supply AH54192A-01.

  • Page 14: Software Requirements

    EQUIREMENTS Software Description/Source GRL-PCIE5-CEM-RXA Granite River Labs PCI Express Card Electromechanical 5.0 (32 GT/s) Automated Receiver Calibration and Compliance Test Solution – www.graniteriverlabs.com VISA Software is required to be installed on the controller PC running GRL-PCIE5-CEM-RXA software. GRL’s software framework has been...

  • Page 15: Setting Up Grl-Pcie5-Cem-Rxa Automation Software

    Download and install the GRL software as follows: 1. If the GRL software is to be installed on a PC (where it is referred to as ‘controller PC’), install VISA (Virtual Instrument Software Architecture) on to the PC where GRL-PCIE5-CEM-RXA is to be used (see Section 2.2).

  • Page 16: Figure 2. Start Pcie Cem 5.0 Rx Test Application

    NSTALLED PPLICATIONS b) Activate a License: • If you have an Activation Key, enter it in the field provided and select “Activate”. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 16 of 123...
  • Page 17 ) for each connected instrument. The “lightning” button should turn green ( ) once the software has successfully established connection with each instrument. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 18: Pre-Configure Software Before Calibration/Testing

    • The fields under DUT Info and Test Info are defined by the user. • The Software Info field is automatically populated by the software. 6. S IGURE ESSION GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 18 of 123...

  • Page 19: Calibrating Using Grl-Pcie5-Cem-Rxa Software

    For the Long Channel TP2 calibration, a PCI-SIG compliance load board (CLB) test fixture will be used for the host system board or a PCI-SIG compliance base board (CBB) test fixture for the add- in card. The board will be connected between the BERT noise generator output and the oscilloscope which will validate the test pattern of the signal and measure for stress tolerance to final stressed eye compliance.

  • Page 20: Set Up Automated Rx Calibration For Tp3

    4.1.1 TP3 Calibration Setup with Tektronix ATI Based Oscilloscope If the Tektronix ATI based oscilloscope is being used, proceed with the following TP3 calibration setup. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 21: Figure 9. Recommended Setup For Tp3 Rx Calibration Using Tektronix Ati Scope

    1. Follow back the same connections from step 1 to 3 in Section 4.1 above. 2. Then using phase matched K-K coaxial cables, connect the MU195050A data outputs to Channels 1 and 2 on the Tektronix ATI based oscilloscope through 6 dB attenuators. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 22: Set Up Automated Rx Calibration For Tp2

    4. Using 1 ft cables, connect between both the CBB Tx Lane and Variable ISI (Nominal 13.0 dB). 5. Connect the Variable ISI (Nominal 13.0 dB) to Channels 1 and 3 on the oscilloscope. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 ©...

  • Page 23: Figure 11. Recommended Setup For Tp2 Long Channel Rx Calibration (Pcie Gen 5 System Board) Using Tektronix Ati Scope

    1. Follow back the same connections from step 1 to 4 in Section 4.2.1 above. 2. Then connect the Variable ISI (Nominal 13.0 dB) to Channels 1 and 2 on the Tektronix ATI based oscilloscope through 6 dB attenuators. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 24: Connect Equipment For Add-In Card Calibration

    4. Using 1 ft cables, connect between both the CLB Tx Lane and Variable ISI (Nominal 2.5 dB). 5. Connect the Variable ISI (Nominal 2.5 dB) to Channels 1 and 3 on the oscilloscope. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 ©...

  • Page 25: Set Measurement Conditions

    SJ frequencies. Recommended procedure: • Step 1: When calibrating, select all conditions that may be used for testing, and perform the calibration. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 26: Set Up Calibration Requirements

    Select to use a compliant PCIe System Board or Add-In Card as the calibration device. 16. S IGURE ELECT EVICE FOR ALIBRATION GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 26 of 123...

  • Page 27: Select Pci Ecem 5.0 R Xcalibration

    Seasim eye calibration (for preset EQ optimization and final eye calibration) can be toggled using the Configurations page “Eye Calibration Method” parameter. See Section 4.6 for more details. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 28: Configure Calibration Parameters

    Configurations page. Set the required parameters for calibration as described below. To return all parameters to their default values, select the ‘Set Default’ button. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 29: Figure 21. Calibration Parameters Configuration Page

    21. C IGURE ALIBRATION ARAMETERS ONFIGURATION GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 29 of 123...

  • Page 30: Table 4. Calibration Parameters Description

    Select the range of presets to be applied for stressed eye calibration. Preset for Eye Calibration Preset to Exclude Specify the preset that is not used for calibration. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 30 of 123...

  • Page 31: Configure Calibration Target Values

    For debugging purposes ONLY, the default calibration target values can be changed for the RJ, SJ, DM and CM calibration. To do this, select from the menu to access the Calibration page. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 32: Run Automation Calibration

    Once calibration have been selected and set up from the previous sections, the calibration are now ready to be run. Select from the menu to access the Run Tests page. The GRL-PCIE5-CEM-RXA software automatically runs the selected calibration when initiated. Before running the calibration, select the option to: •...

  • Page 33: Figure 23. Run Tests Page

    Rx TP3 calibration. 24. E TP3 C IGURE XAMPLE ONNECTION IAGRAM FOR ALIBRATION GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 33 of 123...

  • Page 34: Testing Using Grl-Pcie5-Cem-Rxa Software

    5 Testing Using GRL-PCIE5-CEM-RXA Software The GRL-PCIE5-CEM-RXA test solution supports automated Rx compliance testing as well as optional SJ margin search testing for PCIe Gen 5 system board and add-in card DUT’s. Rx compliance testing includes Tx preset test, initial Tx equalization test, Tx link equalization response test, and Rx link equalization test performed at 32.0 GT/s.

  • Page 35: Overview Of Dut Initial Tx Equalization Test

    The PCIe Gen 5 system board or add-in card DUT will be tested for Tx link equalization response as defined by the PHY Test Specification at 32.0 GT/s. This will ensure the DUT can accurately GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 ©...

  • Page 36: System Board Tx Link Equalization Response Test At 32.0 Gt/S

    • Connect the 100 MHz reference clock output from the BERT to the clock input on the CBB. • Connect the Tx lane under test on the CBB main board to the input of the BERT error detector. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 37: Overview Of Dut R Xlink Equalization Test

    Once the system board DUT is powered on, it should start link training and equalization sequence by the BERT at 32.0 GT/s, which should eventually place the DUT in the loopback state. The GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 38: Add-In Card Rx Link Equalization Test At 32.0 Gt/S

    5.4.3 Link Training During link training process, the DUT basically goes through multiple states via the status state machine (SSM) method to enter Loopback mode as shown below. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 39: Figure 25. Main State Diagram For Link Training And Status State Machine

    2.5 GT/s. 5. The DUT will finally switch to the Loopback mode after having two consecutive TS1 at the requested speed with Loopback bit asserted. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 40: Set Up Automated Dut Txrx Link Equalization Test

    5.5.1 Connect Equipment for System Board TxRx Link EQ Testing The following link EQ test setup uses a PCI-SIG compliance load board (CLB) test fixture for the PCIe Gen 5 System Board DUT. Note: Use logical Lane 0 for the following test setup.

  • Page 41: Connect Equipment For Add-In Card Txrx Link Eq Testing

    6. Using the J1627A GND connection cable, connect the CLB to ground. 5.5.2 Connect Equipment for Add-In Card TxRx Link EQ Testing The following link EQ test setup uses a PCI-SIG compliance base board (CBB) test fixture for the PCIe Gen 5 Add-In Card DUT.

  • Page 42: Set Up Automated Dut Rx Compliance Test

    DUT Rx compliance with the following setup. 5.6.1 Connect Equipment for System Board Rx Compliance Testing The following Rx compliance test setup uses a PCI-SIG compliance load board (CLB) test fixture for the PCIe Gen 5 System Board DUT. Note: Use logical Lane 0 for the following test setup.

  • Page 43: Connect Equipment For Add-In Card Rx Compliance Testing

    MU195040A data inputs for loopback error detection. 5.6.2 Connect Equipment for Add-In Card Rx Compliance Testing The following Rx compliance test setup uses a PCI-SIG compliance base board (CBB) test fixture for the PCIe Gen 5 Add-In Card DUT. Note: Use logical Lane 0 for the following test setup.

  • Page 44: Figure 30. Recommended Setup For Dut Rx Compliance Testing (Pcie Gen 5 Add-In Card)

    3. Connect the Variable ISI to the CBB Rx Lane with the 1 ft cables. 4. Using coaxial cables, connect the CBB Tx Lane directly to the MU195040A data inputs for loopback error detection. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 45: Set Up Test Requirements

    If calibration is not completed, attempting to run the Rx tests will throw errors. 33. S IGURE ELECT ESTS GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 45 of 123...

  • Page 46: Select To Run Dut Link Training And Rx Compliance Test

    The GRL software will automatically run the selected test when initiated. 35. S SJ M IGURE ELECT ARGIN EARCH GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 46 of 123...

  • Page 47: Configure Test Parameters

    To return all parameters to their default values, select the ‘Set Default’ button. 36. T IGURE ARAMETERS ONFIGURATION GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 47 of 123...

  • Page 48: Table 5. Test Parameters Description

    Set the delay/buffer in seconds after power is reset for the system under test. Link Training Wait Time (s) Set the delay/buffer in seconds before initiation of each link training step. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...
  • Page 49 Select the preset co-efficient to be used after link training is successful for the final BER test. If ‘Auto’ is selected, a negotiated preset will be applied during the final BER test. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 50: Enable Loopback Ber Test

    Anritsu PCIe Link Sequencer software loopback mode. Additional configurations can also be made through this page. 38. S BER L IGURE ELECT OOPBACK ETHOD GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 50 of 123...

  • Page 51: Run Automation Tests

    Once tests have been selected and set up from the previous sections, the tests are now ready to be run. Select from the menu to access the Run Tests page. The GRL-PCIE5-CEM-RXA software automatically runs the selected tests when initiated. Before running the tests, select the option to: •...

  • Page 52: Figure 40. Example Connection Pop-Up Diagram For Rx Compliance Test

    40. E IGURE XAMPLE ONNECTION IAGRAM FOR OMPLIANCE GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 52 of 123...

  • Page 53: Interpreting Grl-Pcie5-Cem-Rxa Test Report

    6 Interpreting GRL-PCIE5-CEM-RXA Test Report When all calibration and test runs have completed from the previous section, the GRL-PCIE5-CEM- RXA software will automatically display the results on the Report page. Select from the menu to access the Report page for a quick view of all results.

  • Page 54: Test Summary Table

    This portion displays the results in detail along with supporting data points and screenshots for each calibration/test run. 44. T IGURE ESULTS XAMPLE GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 54 of 123...

  • Page 55: Delete Test Results

    ESULTS 7 Saving and Loading GRL-PCIE5-CEM-RXA Test Sessions The usage model for the GRL-PCIE5-CEM-RXA software is that the test results are created and maintained as a ‘Live Session’ in the application. This allows the user to quit the application and return later to continue where the user left off.

  • Page 56: Appendix A: Method Of Implementation (Moi) For Manual Pcie Cem 5.0 Receiver Measurements

    • BER compliance checking for <1E-12 with stressed eye • SJ marginal testing (optional) Note: Existing PCI-SIG Compliance Load Boards (CLB’s) and Compliance Base Boards (CBB’s) will be used as test fixtures for system host and device DUT’s respectively. Perform Calibration This section describes how to calibrate for the stressed test signal before testing the receiver for compliance.

  • Page 57: Calibration Settings

    An adjustable CEM connector will be used along with the calibration channel for testing the receiver. This will need to adjust the eye amplitude to GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 58: Channel Loss Calibration

    For the Long Channel TP2 calibration, an existing PCI-SIG CBB test fixture will be used as the host system board or PCI-SIG CLB test fixture for the add-in card device. The board will be connected between the BERT noise generator output and the oscilloscope which will validate the test pattern of the signal and measure for stress tolerance to final stressed eye compliance.

  • Page 59: Figure 48. Connection Diagram For Channel Loss Calibration (Add-In Card)

    3. Using 1 m cables, connect between both the VNA Ports 1 & 3 and the CLB Variable ISI and between both the CBB Variable ISI and the VNA Ports 2 & 4. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 60: Amplitude, Preset, Sj And Rj Calibration Setup

    MP1900A BERT. 1. On the BERT’s Applications screen, select the MX190000A Standard Bert application for SI (if using SI-PPG) or Standard Bert application for SI and PAM4 (if using PAM4-PPG). GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 61: Amplitude Calibration Adjustment

    • Select the Pattern tab- Test Pattern: Using Preset 4, with 64 ones followed by 64 zeros followed by 128 bits of a 1010 clock pattern at 32.0 GT/s • Select the Misc1 tab- Aux Output: Pattern Sync GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 62 Scope Settings: • Averaging: 256 points • Horizontal Scale: 100 ns/div • Bandwidth: 50 GHz • Sampling Rate: 128 GS/s GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 62 of 123...

  • Page 63: Preset Calibration Adjustment

    • Select the Pattern tab- Test Pattern: Using Preset 4, with 64 ones followed by 64 zeros followed by 128 bits of a 1010 clock pattern at 32.0 GT/s • Select the Misc1 tab- Aux Output: Pattern Sync GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 64 Scope Settings: • Averaging: 256 points • Horizontal Scale: 1 ns/div • Bandwidth: 50 GHz • Sampling Rate: ≥128 GS/s GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 64 of 123...
  • Page 65 • Sampling Rate: ≥128 GS/s c) SigTest Settings: • Select Technology as ‘PCIe’ • Select Generation as “5_0” • Select Test as “Preset_TestAC_SingleRun” GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 65 of 123...
  • Page 66 “Ref Waveform” is the Preset 4 waveform. o Test Waveform is the new waveform saved to measure Preshoot/De-Emphasis • Select Template as “No_CTLE” • Run Test GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...
  • Page 67 GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 67 of 123...

  • Page 68: Sj Calibration

    • Select Jitter Modulation Source- SJ1: ON • SJ1 Frequency and Amplitude: 100 MHz, 0.000 UIpp, Measure Total Jitter as TJ(Base) • SJ1 Frequency and Amplitude: 100 MHz, 0.100 UIpp, Measure Total Jitter as TJ(Jittered) GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 69 • Select Test as “RXCal” • Click “Confirm” • Browse to the saved waveform file • Select Template as “Rj_SJ_Cal” • Run Test GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 69 of 123...

  • Page 70: Rj Calibration

    BERT Settings: • General Output: ON • Select SI-PPG and Emphasis tab- Emphasis Function: OFF • Select the Pattern tab- Test Pattern: Toggle_1bit GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...
  • Page 71 • Select Test as “RXCal” • Click “Confirm” • Browse to the saved waveform file • Select Template as “Rj_SJ_Cal” • Run Test GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 71 of 123...
  • Page 72 SigTest Results: • Read ‘Random Jitter (RMS)’ value • Adjust RJ until RJ = 0.5 ps (RMS) GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 72 of 123...
  • Page 73 GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 73 of 123...

  • Page 74: Dm & Cm Amplitude And Eye Height/Eye Width Calibration Setup

    MP1900A BERT and a digital oscilloscope. 51. C 5 DM-I, CM-I EH/EW TP2 C IGURE ONNECTION IAGRAM FOR ALIBRATION YSTEM OARD GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 74 of 123...

  • Page 75: Dm-I Calibration Adjustment

    • PPG Data Output: OFF • Select Noise Generator- DM: ON • Differential mode noise Amplitude and Frequency: 10 mVpp and 2.1 GHz GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 76: Cm-I Calibration Adjustment

    Adjust the CM Amplitude using the Scope RMS function with the following configuration. Compute Vpp = RMS/0.707. a) BERT Settings: • Loss Channel GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...
  • Page 77 • Averaging: OFF • Horizontal Scale: 12.5 µs/div • Bandwidth: 8 GHz Measure RMS on (CH1+CH3)/2 and calculate Vpp = RMS/0.707. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 77 of 123...

  • Page 78: Eh/Ew Calibration Adjustment

    2.0 ps. ▪ The waveform is considered an outlier if the Eye Height is < 1.0 mV or deviates from the median by 5.0 mV. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 79 • Browse to the saved waveform file • Select Template as “Eye_Cal” • Set CTLE Gain, for example: -5 • Run Test GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 79 of 123...
  • Page 80 The Eye Height @BER and Eye Width @BER must fall within the following target values: Target Minimum Eye Width: 9.375 +0.5/-0.5 ps Target Extrapolated Eye Height: 15 +1.5/-1.5 mV GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 81: Perform Initial Tx Equalization & Tx Link Equalization Response Tests

    Note: Use logical Lane 0 for the following test setup. 53. C DUT I EQ / T EQ R IGURE ONNECTION IAGRAM FOR NITIAL ESPONSE GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 81 of 123...

  • Page 82: Equipment Setup For System Board Dut Tx Link Eq Response Test

    PCIe Gen 5 system board DUT. This setup is using the MP1900A BERT that includes the MU195040A SI Error Detector module and a compliant CLB test fixture for the DUT. Note: Use logical Lane 0 for the following test setup. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 83: Figure 54. Connection Diagram For Pcie Gen 5 System Board Dut Tx Link Eq Response Test

    J1632A coaxial terminator due to differential signal output (not shown in above setup). 7. Using coaxial cables, connect the CLB Tx Lane 0 to any of the pick-off tee input ports. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 84: Initial Tx Eq Startup And Testing

    ▪ To account for measurement noise, a tolerance of ±1.0 dB is used for measured preshoot and de-emphasis that are defined as 0.0 dB in the PCI Express Base Specification. ▪ Due to measurement sensitivity having more impact on higher boost preset, a tolerance of ±1.5 dB is used for P10 preshoot.
  • Page 85 7. When the LEQ Test pane appears, select the Initial Tx LEQ tab. Set the “DUT Initial Preset (Preset Hint Tx)” to Preset 0 (P0). Then select “Apply”. 8. Press the Power Reset button on the CBB test fixture to reset the DUT. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 86 Template drop-down field. Then select the “Test” button at the bottom to start the test run. All preset numbers must turn green once the test completes to indicate a Pass. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 87: Tx Link Eq Time Response (With Presets/Cursors) Startup And Testing

    ▪ To account for measurement noise, a tolerance of ±1.0 dB is used for measured preshoot and de-emphasis that are defined as 0.0 dB in the PCI Express Base Specification. ▪ Due to measurement sensitivity having more impact on higher boost preset, a tolerance of ±1.5 dB is used for P10 preshoot.
  • Page 88 (Preset Hint Tx)” to Preset 4 (P4) and the “DUT Target Preset (Change Preset)” to P0. Note: Use the following “DUT Initial Preset (Preset Hint Tx)” and “DUT Target Preset (Change Preset)” combinations for this step: GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 89 7. Press the Power Reset button on the CBB test fixture to reset the DUT. 8. In the MX183000A - PCIe Link Training window, select ‘Link Start’ in the Link Training tab. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 90 14. In the PCIe Preset Decoder screen, verify that the Electrical transition time is showing < 1 µs to pass the test. Note: The Decoded transition time serves as an informative value only and is not required for compliance. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 91: Perform Rx Link Eq Test

    PCIe Gen 5 add-in card DUT. This setup is using the MP1900A BERT that includes the MU195040A SI Error Detector module and a compliant CBB test fixture for the DUT. Note: Use logical Lane 0 for the following test setup. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 92: Equipment Setup For System Board Dut Loopback Test

    PCIe Gen 5 system board DUT. This setup is using the MP1900A BERT that includes the MU195040A SI Error Detector module and a compliant CLB test fixture for the DUT. Note: Use logical Lane 0 for the following test setup. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 93: Figure 56. Connection Diagram For Pcie Gen 5 System Board Dut Loopback Test

    3. Using coaxial cables, connect the MU195020A/MU196020A data outputs to the MU195050A data inputs. 4. Using coaxial cables, connect the MU195050A data outputs to the Variable ISI (Nominal 4.9 – 7.9 dB). GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 94: Link Training Initialization And Testing

    3. In the MX183000A - Selector pop-up, select ‘PCIe Link Training’ and then ‘Start’. 4. In the next window, select the network address of the MX190000A BERT application followed by ‘Connect’ to link up with the MX190000A. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 95 6. Press the Power Reset button on the CBB test fixture to reset the DUT. 7. In the MX183000A - PCIe Link Training window, select ‘Link Start’ in the Link Training tab. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 96: Link Training Failure Troubleshooting

    • Remove the ISI channel and connect data signals to the DUT directly. • Press the Power Reset button on the CBB or reboot the DUT. • Ensure the PPG Output setting is ON. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 97: Perform Dut R Xcompliance Testing

    1. Continuing from the same Rx compliance test window, select the Run Test tab. Select ‘Run Test’ to start running measurements for jitter tolerance. 2. When completed, select the Graph tab to view a data plot from the measurement results. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 98 GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 98 of 123...

  • Page 99: Appendix B: Return Path Optimization Using Anritsu J1890A Pcie5 Re-Driver Set

    • CMI 3. Select the ‘LEQ Test Setting’ checkbox in the MX183000A Main Window and set the following: i) Set ‘PPG Starting Preset’ to ‘P5’ GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...
  • Page 100 Note: If Loopback cannot be established by the procedure up to this point, the measurement environment may be incorrect (cable connection error, etc.) or it may be a DUT problem, so review the measurement environment again. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 101 • Click on the ‘Auto Search’ button. • Execute ‘Auto Search’ using the following settings: o Mode: Fine(NRZ) o Item: Threshold&Phase o CTLE Auto Adjust:ON GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 101 of 123...
  • Page 102 By applying the above settings to the following parameters of MX183000A, optimization of Return Path is completed. CTLE setting Clock Delay Preset setting GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 102 of 123...

  • Page 103: J1890A Pcie5 Re-Driver Set Setup & Configuration

    9.3.2 Connections Refer to the following picture for the appearance of each part and displayed labels. From DUT To ED GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 103 of 123...

  • Page 104: Setting Of Power Supply Ah54192A-01

    The electrical characteristics of the AH54192A are guaranteed. Power Supplies Specifications Items Conditions Units min. typ. max. +4.2 +4.4 Supply Voltage (×2) Supply Current Power Consumption GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 104 of 123...

  • Page 105: Voltage Setup Steps Of Ah54192A-01

    3. Turn off the power and connect the dedicated DC power cable to the AH54192A. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 106: Appendix C: Return Path Optimization Using Macom Technology Solutions Re-Driver

    3. Select the ‘LEQ Test Setting’ checkbox in the MX183000A Main Window and set the following: i) Set ‘PPG Starting Preset’ to ‘P5’ ii) Set ‘DUT Initial Preset (Preset Hint Tx)’ to ‘P9’ GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 107 If Loopback cannot be established up to step 6 iv), remove ISI from the measurement system and execute steps 6 i) to 6 iv). GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...
  • Page 108 EQ presets, use the central EQ preset as the optimum setting. vi) Execute Auto Search in step 7 iii) again. vii) Execute CDR Tune. (This step is Optional) GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.
  • Page 109 • Threshold, Phase, and EQ settings confirmed in step 7. By applying the above settings to the following parameters of MX183000A, optimization of Return Path is completed. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...
  • Page 110 Clock Delay Preset setting GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 110 of 123...

  • Page 111: Macom Re-Driver Setup & Configuration

    DC power ON to +3.3 V. Unused channels (Ch0 and Ch3) do not need to be terminated. USB Cable Power Supply GND Cable J1728A From DUT (Differential) To ED (Differential) K220B GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 111 of 123...

  • Page 112: Operation Guide

    1 to 127. Channel control also allows control over the settings like, low frequency boost, bias control, and disabling the channel. All four channels can be configured differently, by selecting the individual channel tab. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 113: Eq Setting Optimization

    EQ_P2 EQ_P3 EQ_P4 EQ_P5 EQ_P6 EQ_P7 EQ_P8 EQ_P9 EQ_P10 EQ_P11 EQ_P12 EQ_P13 EQ_P14 EQ_P15 EQ_P16 EQ_P17 EQ_P18 EQ_P19 EQ_P20 GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 113 of 123...

  • Page 114: Figure 57. Setup Configuration Page

    4. Then select the ‘Run SigTest’ button to perform SigTest using a selected saved offline waveform file. When selected, the GRL software will automatically run the SigTest for the waveform as shown in below example. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 115: Figure 59. Running Offline Sigtest Verification

    5. Once test is completed, the results will be displayed like in the following example. 60. V IGURE IEWING NALYSIS ESULTS GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 115 of 123...

  • Page 116: Figure 61. Setup Configuration Page

    3. Select the ‘Tx Response Preset’ or ‘Tx Response Cursor’ button to initiate the respective Tx link EQ time response test. The Select Waveforms pop-up will appear as below. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 117: Figure 63. Initiate Tx Link Eq Time Response Preset/Cursor Test

    To quickly determine at which point the Tx equalization change starts to happen in the DUT, select the ‘Show’ button which will display the row highlighted in yellow. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 118: Figure 65. Viewing Tx Link Eq Time Response Preset/Cursor Test Results

    6. For further analysis of the test results, respective traces for the decoded and electrical transition times can be viewed by selecting the ‘Show Image’ button for each category. An example is shown below. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 119: Figure 66. Viewing Tx Link Eq Time Response Preset/Cursor Test Trace For Transition Time

    RACE FOR RANSITION Note: The Decoded transition time serves as an informative value only and is not required for compliance. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022 Page 119 of 123...

  • Page 120: Figure 67. Keysight Connection Expert

    XPERT 5. Refresh the system. The Keysight Scope is shown on the left pane and the VISA address is shown on the right pane. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 121: Figure 68. Oscilloscope's Visa Address

    “TCPIP0::192.168.0.110::inst0::INSTR”. Note to omit the Port number from the address. If there is error in connection, type in the Scope IP address as “TCPIP0::192.168.0.4::5025::SOCKET”. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

  • Page 122: Figure 69. Openchoice Instrument Manager In Start Menu

    “Instrument Identify”: Select to use a supported programming language to send a query to identify the selected instrument. d) “Properties”: Select to display and view the selected instrument properties. GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022.

  • Page 123: Figure 70. Openchoice Instrument Manager Menu

    “GPIB8::1::INSTR”. If the GRL software is installed on the PC to control the Scope, type in the Scope IP address, for example “TCPIP0::192.168.0.110::inst0::INSTR”. Note to omit the Port number from the address. END_OF_DOCUMENT GRL-PCIE5-CEM-RXA User Guide and MOI Rev7.0 © Granite River Labs 2022 Version 7.0, June 2022. Updated 06.29.2022...

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