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VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
MAIN C.B.A.
IC3201 (FORMATTING/EQUALIZER)
TO/FROM VIDEO
86
SIGNAL PROCESS I
DBR (0-3)
MODULATOR
BLOCK DIAGRAM
/DEMODULATOR
89
RESET(L)
RESET(L)
109
39
FROM SYSTEM
RESET(L)
CONTROL
BLOCK DIAGRAM
ADDA (0-3)
27MHz CLOCK
TO/FROM VIDEO
SIGNAL PROCESS I
READ(H)
BLOCK DIAGRAM
VAL
HEAD SW PULSE 1
REC CLOCK
AGC CONTROL
VITERBI
EQUALIZER
A/D CONVERTER
AMP
ATF DET
BPF
A/D CONVERTER
AMP
REC-C CONTROL
REC CONTROL
HEAD SW PULSE 2
HEAD SW PULSE 1
REC ON/OFF CONTROL
D/A CONVERTER
MICROCONTROLLER
INTERFACE
27MHz
CLOCK
READ(H)
VAL
74 76
78
84
81
79
REC VIDEO SIGNAL
IC5001 (HEAD AMP)
50
8
LOGIC
DRIVE
GCA
51
10
AGC
33
3
DET
AGC
9
6
1
43
AMP
AMP
11
39
LPF
34
35
EQ HOLD
49
11
53
15
45
16
44
17
LOGIC
PB(H)
54
18
48
19
(FROM SAFETY TAB SW)
14
S-TAB ON(L)
23
V1
0.1 V
PB Mode (SP)
91
PB VIDEO SIGNAL
REC AUDIO SIGNAL
PB AUDIO SIGNAL
CYLINDER UNIT
FP5
27
CH1
6
CH 1
26
HEAD
FP5
HEAD
28
AMP
7
29
FP5
31
CH2
5
CH 2
30
HEAD
HEAD
FP5
AMP
32
AMP
4
33
41
B2
ENVELOPE
14
B2
TO INTERFACE BOARD
HEAD SW
(FOR EVR ADJUSTMENT)
15
PULSE
B2
ATF
13
0.30 Vp-p
V1
2.0 Vp-p
1 V
2 ms
5 ms
VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
PV-GS19PL/PV-GS31PL/PV-GS35PL
PV-GS19PL / PV-GS31PL / PV-GS35PL
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