LG 50UH5500 Service Manual page 42

Close to Main chip
GND pattern should be
connected with 75ohm reg
of Component Jack
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2016 LG Electronics Inc. All rights reserved.
Only for training and service purposes
TXDBN2_L
TXDBP2_L
TXDBN3_L
TXDBP3_L
EPI Share Lane TXDBN4_L
For 51p location TXDBP4_L
TXDBN5_L
TXDBP5_L
TXDBN6_L
TXDBP6_L
TXDBN7_L
TXDBP7_L
Level Shifter
EO_A
DATA_FORMAT_0
GST_A
TXDBN0_L
TXDBP0_L
MCLK_A
TXDBN1_L
TXDBP1_L
EPI Share Lane
For 41p location
I2C_SDA6
I2C_SCL6
0.047uF
COMP1_PbP
COMP1_Pb
R610 100 COMP1_PbP
0.047uF
COMP1_Y/CVBSP
R611 100 0.047uF
C603
COMP1_PrP
5pF 0.047uF
COMP1_YPbPrN
50V
0.047uF
TU_CVBS
0.047uF
COMP1_YPbPrN SC_CVBS_IN
0.047uF
C606
5pF
COMP1_Y/CVBS COMP1_Y/CVBSP
R612 100
50V
R613 100
C604
5pF
GND pattern should be
50V
connected with 75ohm reg
of SCART Jack
COMP1_YPbPrN
COMP1_Pr
COMP1_PrP
R614 100 SC_CVBS_IN
R615 100
C605
5pF
50V
COMP1_YPbPrN
IC100
LGE6551-CA1
B25 B29
LVDS_AAN LVDS_CAN
A25 A29
LVDS_AAP LVDS_CAP
B24 B28
LVDS_ABN LVDS_CBN
A24 A28
LVDS_ABP LVDS_CBP
B23 AJ30
LVDS_ACN LVDS_CCN
A23 AJ29
LVDS_ACP LVDS_CCP
B22 AK31
LVDS_ADN LVDS_CDN
A22 AK30
LVDS_ADP LVDS_CDP
B21 AL31
LVDS_AEN LVDS_CEN
A21 AK29
LVDS_AEP LVDS_CEP
B20 AL30
LVDS_AFN LVDS_CFN
A20 AL29
LVDS_AFP LVDS_CFP
AF28 AF31
LOCKAn LVDS_BAN LVDS_DAN
AF27 AF30
HTPDAn
LVDS_BAP LVDS_DAP
AG28 AF29
EO_A LVDS_BBN LVDS_DBN
AG27 AG30
BIT0
LVDS_BBP LVDS_DBP
AH28 AG29
GST_A LVDS_BCN LVDS_DCN
AH27 AH31
BIT6
LVDS_BCP LVDS_DCP
AJ28
AH30
LVDS_BDN LVDS_DDN
AJ27 AH29
BIT5
LVDS_BDP LVDS_DDP
B27 B31
LVDS_BEN LVDS_DEN
A27 A31
LVDS_BEP LVDS_DEP
B26 B30
LVDS_BFN LVDS_DFN
A26 A30
LVDS_BFP LVDS_DFP
IC100
LGE6551-CA1
C1 A4
COMP1/AV1/DVI_L_IN
VINRP AI1L
D1 C654
B4 2.2uF
VINRN AI1R COMP1/AV1/DVI_R_IN
B1 A5 2.2uF C655
VX1_MSE
VINGP AI2L
C2 B5
VINGN AI2R AMP_RESET_N
A1
VINBP
C3
VINBN
D4
AI4L BIT7
D5
BIT8
AI4R
E4
AIO2L
B2 E5
VSYNC AIO2R
A2 F4
HP_LOUT
HSYNC HPOL
F5
HP_ROUT
HPOR
G2
DTV/MNT_V_OUT
VDACOUT
C629 D2 G3
VIN3P FSW0
C630
E2
VIN4P
C631 E3 C5
port changed
VIN5P SPDIF_OUT BIT9
C632
D3 (SPDIF noise issue)
VINY0N
C633 F3
VIN10P
C634
F1 C4
VIN13P MICBAIS
C635 F2
VINA0N L600 PZ1608U121-2R0TF
AB5
ADCG
L601 PZ1608U121-2R0TF
AG5
BBG
C657
AF5 0.1uF
VCMBB
16V
C656
1uF
EPI Lane
For 41p location
TXDAN2_L
TXDAP2_L
TXDAN3_L
TXDAP3_L
GCLK_A
MCLK_A
L/D_VSYNC Level Shifter
GCLK_A
L/D_DO
L/D_CLK
VID_CPU
DATA_FORMAT_1
VID_CORE
AGP_CTRL Default Low Set!
TXDAN2_L
TXDAP2_L
TXDAN3_L
TXDAP3_L
TXDAN0_L
TXDAP0_L
TXDAN0_L
TXDAN1_L
TXDAP0_L
TXDAP1_L
TXDAN1_L
TXDAP1_L
EPI Lane
For 41p location
Internal Analog Demod Test Point
DTV/MNT_V_OUT
K2L
MAIN4_EXT_IN/OUTPUT
15/04/27
04
LGE Internal Use Only