Shivaki STV-24LEDGR7 Service Manual
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Shivaki STV-24LEDGR7 Service Manual

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  • Page 8 Please sw set the GPIO to control system for operation Generated by Foxit PDF Creator © Foxit Software GPIO Table Please note GPIO state that affects consumetion http://www.foxitsoftware.com For evaluation only. GPIO # Signal Function Note(description) GPIO_A6 I2S OUT MCK HD RESET LOW Sheet Index GPIO_B5...
  • Page 9 Generated by Foxit PDF Creator © Foxit Software 外置电源部分 http://www.foxitsoftware.com For evaluation only. 100nF/X7R 100nF/X7R R1 12R R1 12R R0402 R0402 C0402 C0402 立式 立式 外置电源输入及控制电路 33uH/ 33uH/ DVD Power Interface TI12-L TI12-L 100nF/X7R 100nF/X7R R3 12R R3 12R SY8133 SY8133 820K±1% 820K±1%...
  • Page 10 MSD309PX Generated by Foxit PDF Creator © Foxit Software http://www.foxitsoftware.com For evaluation only. U7 B U7 B M SD3 09PX M SD3 09PX TS back from CI TS to CI U7 C U7 C M SD3 09PX M SD3 09PX PCM _OE_N PCM _OE_N SCH6 PC M C I A...
  • Page 11 Generated by Foxit PDF Creator © Foxit Software RN19 RN19 MIUA_DQS0B MA_DQSB0 RN20 RN20 SCH3 MIUA_DQS0B http://www.foxitsoftware.com For evaluation only. MIUA_DQS0 MA_DQS0 MA_MCLKZ SCH3 MIUA_MCLKZ SCH3 MIUA_DQS0 1.8VA MA_MCLK SCH3 MIUA_MCLK RN21 RN21 RP0402 RP0402 MIUA_DQS1B MA_DQSB1 RP0402 RP0402 SCH3 MIUA_DQS1B MIUA_DQS1 MA_DQS1...
  • Page 12 馈电部分 RF AGC Switch DVB-T TUNER Generated by Foxit PDF Creator © Foxit Software http://www.foxitsoftware.com For evaluation only. FUSH 3.3VA R113 R113 Q16 close to tuner RFAGC 2N5401/NC 2N5401/NC 5V_B1 ANT_5V 22R/NC 22R/NC ANT_5V ANT_VDD 5V_B1 T_RF_AGC RF_AGC RF_AGC SCH3 0.1u 0.1u 5VB1...
  • Page 13 Generated by Foxit PDF Creator © Foxit Software VCC-PCMCIA VCC-PCMCIA http://www.foxitsoftware.com For evaluation only. TP26 TP26 TP24 TP24 PCMCIA_CNT PCMCIA_CNT TP27 TP27 TP25 TP25 PCM_CD1_N PCM_D3 CD1# TS_MDO3 PCM_D4 MDO3 TS_MDO4 PCM_D5 MDO4 TS_MDO5 PCM_D6 MDO5 TS_MDO6 PCM_D7 MDO6 TS_MDO7 PCM_CE_N MDO7 CE1#...
  • Page 14 HDMI Input HDMI Input Generated by Foxit PDF Creator © Foxit Software close to MSD309PX close to MSD309PX http://www.foxitsoftware.com For evaluation only. CN10 CN10 DC2+ R168 R168 RXC2P DATA2+ DB2+ R169 R169 RXB2P R170 R170 RXC2N DATA2+ DATA2 SHIELD R171 R171 RXB2N DC2-...
  • Page 15 VGA INPUT FULL SCART Generated by Foxit PDF Creator © Foxit Software TP19 TP19 TP18 TP18 R213 R213 SC1_FB SCH3 CN 12 CN 12 R214 R214 C166 C166 AV1-V http://www.foxitsoftware.com For evaluation only. AV1-Vin+ SCH3 CN 13 CN 13 C168 C168 AV1-V R216...
  • Page 16 Generated by Foxit PDF Creator © Foxit Software http://www.foxitsoftware.com For evaluation only. VCC-OP2 VCC_AMP VCC-OP VCC-OP R305 R305 R306 R306 220R/0805/5% 220R/0805/5% C220 C220 VCC-OP MMBT3904 MMBT3904 220uF/16V/RK 220uF/16V/RK R307 R307 SK-L SCH3 AUOUTL0 MMBT3904 MMBT3904 AMP-L R360 0R/ NC R360 0R/ NC R358 R358...
  • Page 17 SERVICE MANUAL Model: LCD TV WITH MSD306 Ver1.0 SOLUTION Contents Index Safety Precaution………………………………………………….page 2 to 3 Technical Specifications…………………………………………..page 4 to 7 Block Diagram……………………………………………………page 8 to 10 Circuit Diagram…………………………………………………page 11 to 18 Main IC Specifications ………………………………………..page 19 to 131 PCB Information……………………………………………..page 132 to 143 Software Upgrade…………………………………………...page 144 to 148 MSD306 Factory Menu……………………………………..page 149 to 152 This manual is the latest at the time of printing, and does not...
  • Page 18 This symbol indicates ＂ dangerous voltage ＂ inside the product that presents a risk of electric shock or personal injury This symbol indicates important instructions accompanying product. Plese read this manual carefully before using this product. Before connecting the AC power cord to the DC adapter outlet , make sure the voltage designation of the LCD TV corresponds to the local electrical supply .
  • Page 19 Do not place the LCD TV/monitor on an unstable cart, stand, tri[od, bracket, table or floor where it can fall. It is damaged if dropped, hit or scratched. Do not clean the front with keton-type materials(e.g.Acetone), ethyl alcohol, toluene. Ethy lacid, methyl, or chloride-these may damage the panel.
  • Page 20 MODEL: Technical Specifications 18.5’’/21.6/23.6’’ Icd combo Display DATA FIRST ISSUED ISSUE RAISED BY CHECKED BY REVISIONS ISSUED DATE DESCRIPTION RAISED BY: SPECIFICATION AGREED: SIGNATURE DATE R & D DEPARTMENT ………………………………………………………. ……………………… …… …… COMMERCIAL DEPARTMENT ……………………………………………………… ………………………. PRODUCTION DEPARTMENT …… …….
  • Page 21 TECHNICAL SPECIFICATIONS OF LCD TV WITH MSD306 Ver1.0 SOLUTION ITEM Details Descriptions LCD TV with MSD306 Ver1.0 solution with PAL BG/DK/I,SECAM BG/DK/L/L' and Terrestial Digital Video Broadcasting (DVB-T) RF receiving system,divx DVD player Feature Multi-system video input, SCART interface, 750 pages Europe Text, BG/DK/I digital Description NICAM decoding,A2 stereo,Multi-mode PC signal display.
  • Page 22 Antenna 75Ohm Unbalanced Impedance ～110V—240V 50Hz/60Hz AC Input Range Input Main TV control keys: Standby, Source, Menu, Programme+/-, Key Control Volume+/- DVD control keys: Eject/Player&pause/Stop DVD Function DVD disc notch Standby(Red)/O Facing viewing LED Indicators & Remote Sensor n(Green); Video&Audio Input (1 Φ3.5 Jack) CVBS Video(Ypbpr) Input (1 Φ3.5 Jack) YPBPR...
  • Page 23 Transmission Main Electrical 2K,8K Mode Specification For Code Rate 1/2,2/3,3/4,5/6 & 7/8 DVB-T Section Suitable Signal From -10dBm to -70dBm Level Transport stream MPEG-2 ISO/IEC 13818 RF Bandwidth 7 or 8 MHz Active Resolution Supports resolution up to 720p PAL or SECAM CVBS/S-Video 16:9 & 4:3 Video Format Mode MPEG-1/ MPEG-2 Layer Ⅰ,Ⅱ...
  • Page 24 BLOCK DIAGRAM Power System Block POWER AUDIO P-MOS P-MOS PANNEL MSD306 3.3V DC-DC 1.32V DC-DC MSD306 1.8V DC-DC 3.3V IN4001 MSD306 2.5V P-MOS MSD306 3.3V MAX3543 DVD MAIN DC-DC BOARD Page 8 of 152...
  • Page 25 BLOCK DIAGRAM Block Diagram Of MSD306 Solution DVD CONNECTOR KEY CONNECTOR & REMOTE INSTRUCTION BACK LIGHT CONNECTOR SCART LVDS CONTOLLOR ADDRESS CONNECTOR CONTROLLOR PCMICA DATA AUDIO AMP DDR*1 SPEAKER AUDIO L/R R2A15120 MUTE MSD306 FLASH DIF+/DIF- TUNER MAX3543 SPDIF Page 9 of 152...
  • Page 26 BLOCK DIAGRAM DVD System Block Diagram Page 10 of 152...
  • Page 27 Pin22_EC_ SPDCO A+5V CLKOUT MGND TRAY_SW1 DISC_IS_IN 0.047uF 0.047uF CLKIN TRAY_SW2 TRAYOUT MGND 27MHz 27MHz DAC_VREF V_COMP 10uF 10uF VVCC3 LOAD+ SLED+ 4.7K 4.7K LOAD- SLED- EC10c EC10c CVB1 TV_DAC0 TRAY_SW3 TRAYIN HOME VREF2 LDSW C26c C26c C28c C28c TV_DAC1 SP_BRAKE 10uF/16V 10uF/16V...
  • Page 28 Circuit of DVD-2 CARD_SENSE VFD_CLK P+5V A+5V SD_CLK IR_IN P+5V VCC5 VFD_STB SD_CMD TX_IR V_V_SYNC V_H_SYNC TR_B1 1N4001 1N4001 SD_D0 VCC3 A_FR VCC3 STB_IO VFD_DATA 2SS8550D(EBC,1.5A,1W) 2SS8550D(EBC,1.5A,1W) M+3.3V EC1c EC1c BC2c BC2c A_FL CVBS_B/U_O SD_VCC3 P+5V 220uF/16V 220uF/16V 0.1uF 0.1uF 0.1uF 0.1uF USB_DM...
  • Page 29 DC/DC CONVERTER PANEL POWER SUPPLY For big size PSU DVD INTERFACE SW3.3V VCC-PANEL SW3.3V 3-Pin/2.54MM 1.32V TO-252-78MXX 1.32V Main DC-DC 700mA LCR645-5.6uH LM7805 5V_SW 12V_SW 100nF AP2305 5V_TUNER SW3.3V 2-Pin-2.54MM R384 R118 R119 240K_1% 0.1u 0.1u 2.2K 2.2K SY8008A C115 470uF/16V 100K 100K...
  • Page 30 RP13 22RX4 TS1_D7 TS_MDI7 LVDS INVERFACE U2-B MSD306 U2-C MSD306 TS1_D6 TS_MDI6 PCMCIA TS1_D5 TS_MDI5 HDMI AUDIO TS1_D4 TS_MDI4 RXE3/- TS1_D3 TS_MDI3 RXE3/+ RXE3/- PCM_D0 R182 TS1_D0 HDMI1_0- SCRTL PAD_PCM_D[0] PAD_TS1_D[0] TS1_D2 TS_MDI2 HDMI1_0- PAD_RX0N_A PAD_LINEIN_L0 SCRTL PCM_D1 R179 TS1_D1 RXEC/- HDMI1_0+ SCRTR...
  • Page 31 USB CONNECTOR PCMCIA Connector RP50 22RX4 CONN1 VCC-PCMCIA VCC-PCMCIA PCMCIA_CNT MIUA_DQS0 MA_DQS0 MIUA_DQS0 MA_MCLK MIUA_MCLK MIUA_DQS0B MA_DQSB0 SW1.8V MIUA_DQS0B MA_MCLKZ SW1.8V MIUA_MCLKZ A_MVERF PCM_CD1_N PCM_D3 CD1# TS_MDO3 PCM_D4 R107 MDO3 RP57 22RX4 RP39 TS_MDO4 PCM_D5 MDO4 22RX4 MIUA_DQS1 MA_DQS1 TS_MDO5 PCM_D6 MIUA_DQS1 MDO5...
  • Page 32 HEADPHONE HEADPHONE OUT A12V AMP_LIN BOM需更新 此区域器件值 AMP_LIN AMP_L MMBT3904 FB19R R327 15R AUOUTL0 R278 CA92 AMP_RIN 47uF/16V AMP_R C236 R288 HP-ST025A 200p R142 200K 220R C129 10nF R126 R124 A12V J116 AMP_RIN C130 10nF MMBT3904 R294 R328 15R CA93 AUOUTR0 47uF/16V R143...
  • Page 33 CT25 33nF SDA_MXA CT24 AGND 1500pF VCCA VCCA IF_TV AIFA CT28 IF_OUT DIF1A 22pF $$$23296 #IF_OUT DIF2A AGND CT23 1000pF AGND CT29 CT27 AGND CT21 CT26 8.2pF NC 22pF 1000pF 22pF DIF_AGC AGND AGND 1OOOPF LT11 CT22 AGND 0.47uF $$$4 150nH SCL_MXA AGND...
  • Page 34 AMPK_L+ ASPK_L- C193 C226 470nF/25V/0603/X 470nF/25V/0603/X 12V_SW 33uH 33uH C207 L-10UH(R11) L-10UH(R11) 470nF/25V/0603/X C230 470nF/25V/0603/X 1000uF/16V/NC C227 470nF/25V/0603/X 470uF/16V/NC C213 C192 AMPK_L+ OUT1 470F/25v AMP_L C203 R155 AMP_R TDA1517P AMPK_R+ OUT2 C216 SVRR MUTE SGND 470uF/16V/NC VSA1 VSB1 12V_SW R490 12V_SW 12V_SW STBY...
  • Page 35 MAIN IC SPECIFICATIONS Page 19 of 152...
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  • Page 43 D-class power amplifier CONFIDENTIAL R2A15120FA 2ch x 15W / 8ohm D-class power amplifier R2A15120FA R2A15120FA 　 1. General Description R2A15120FA is standard IC of D-class power amplifier developed for FPD or Home audio etc. R2A15120FA can realize maximum Power 15W x 2ch　(VD=15V,THD=10%,BTL) at 8Ω load. It is possible to construct the D-class amplifier system easily.
  • Page 44 D-class power amplifier CONFIDENTIAL R2A15120FA 4．Internal Block Diagram figure 36 35 32 31 26 25 OUTB1 OUTB2 OUTB1 OUTB2 VDB1 VDB2 VDB1 VDB2 HBB1 HBB2 HBA1 HBA2 VDA1 VDA2 VDA1 VDA2 OUTA1 OUTA2 OUTA1 OUTA2 11 12 Page 28 of 152...
  • Page 45 D-class power amplifier CONFIDENTIAL R2A15120FA 5. Terminal Descriptions NAME Description － VSA1 CH1-A block: GND terminal for power output stage 　 STBYL Stand-by control terminal. “L”: Stand-by status. This terminal has pull-down 50 kΩ(typ). MUTEL Mute control terminal. “L”: Mute status. INA1 CH1-A block: Analog signal input terminal INB1...
  • Page 46 D-class power amplifier CONFIDENTIAL R2A15120FA 7． Absolute maximum ratings Symbol Parameter Condition Value Unit VDmax Maximum VD VD voltage(*1) Voltage (External power supply) HBmax Maximum HB HB voltage(*2) Voltage HB-OUT voltage(*3) DVDDmax Maximum DVDD Built-in power supply DVDD terminal Voltage (Internal typ:10V) AVCCmax Maximum AVCC...
  • Page 47 D-class power amplifier CONFIDENTIAL R2A15120FA Notes:1. This product may generate heat, even while operating normally, and it may become high temperature. If there is defect of characteristic or failure including peripheral parts, this product and peripherals may become more high temperature. Moreover, since it is used at the last stage of a product, it may be damaged according to an external factor.
  • Page 48 D-class power amplifier CONFIDENTIAL R2A15120FA 8. Heat decrease curve At use PKG 48pin HTQFP Thermal De-rating High heat radiation QFP：7mm□ Exposure Die-pad(solder connection) Board Using an ideal Heat Sink 7.00W (θjc=17.86 ºC/W ： Simulation value) board mounting 4.20W Exposed Die-pad(solder connection)　 　...
  • Page 49 D-class power amplifier CONFIDENTIAL R2A15120FA 9. Recommended Operating condition Parameter Symbol Condition Unit Supply Voltage VD terminal voltage(*1) AVCC Control voltage of high level STBYL,MUTEL Control voltage of low level STBYL,MUTEL ｆ Carrier Frequency Terminal name(In parentheses, pin number.) 　　 (*1) 　VDA1(45, 46), VDB1(39, 40), VDA2(15, 16), VDB2(21, 22) 10.
  • Page 50 D-class power amplifier CONFIDENTIAL R2A15120FA 11．Functional Explanation 11-1. Gain Setting The total gain of this system can be set to four stages with the terminal of GAIN1 and GAIN2. Terminal Item Symbol GAIN GAIN1 GAIN2 Value GAIN 19.5 dB 25.5 dB 29.5 dB Terminal GAIN setting 33.5 dB...
  • Page 51 D-class power amplifier CONFIDENTIAL R2A15120FA 11-2. Output clip function Output clip voltage can be set by external resistance value. Clip voltage is defined by voltage at terminal RLMT(33pin):VLMT as shown below. VRMT can be set from 0V to 5V by external resistor. This IC can adjust the clip output power by using external resistor as shown fig.
  • Page 52 D-class power amplifier CONFIDENTIAL R2A15120FA 11-4. Carrier I/O control Carrier I/O condition is controllable by external condition of terminal ROSE. Setting ROSC condition State of Operating condition terminal CLK Master Resistor connected Output Operating by the clock mode ROSC to RREF signal of internal oscillator.
  • Page 53 D-class power amplifier CONFIDENTIAL R2A15120FA 11-6.Soft mute By using the CR filter circuit connected to MUTEL terminal, output signal can be smooth slope when mute mode is turned on or off. MUTEL MUTE Control circuit MUTEL Input signal Output signal Soft Mute Mute Soft Mute...
  • Page 54 D-class power amplifier CONFIDENTIAL R2A15120FA 11-8. Remarks of power ON and OFF Please follow the following sequence when the power is turned on. And, please follow by the opposite sequence when the power is turned off.　 Recommended power on/off sequence Power ON Power off Power ON...
  • Page 55 D-class power amplifier CONFIDENTIAL R2A15120FA 11-9　Protection functions (1) Over Current Protection Circuit This circuit detects the unusual over current of Output Power FETs and protects IC. The detection current value will be set 7.5A (typ). (2) Over Temperature Protection Circuit This circuit detects unusual over temperature of IC(chip) and protects it.
  • Page 56 D-class power amplifier CONFIDENTIAL R2A15120FA 12. Notes The PWM output stage of a D-class amplifier treat a large current of the high frequency. So,please note the following points besides a basic matter in board such as "Shortest wiring", "Low parasitic impedance making", and "Part use with an excellent high frequency characteristic".
  • Page 57 Rev. 1.0, Mar. 2010 K4T51043QI K4T51083QI K4T51163QI 512Mb I-die DDR2 SDRAM 60 & 84FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS"...
  • Page 58 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI Revision History Revision No. History Draft Date Remark Editor - First Spec. Release Mar. ’10 S.H.Kim Page 42 of 152...

  • Page 59: Table Of Contents

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI Table Of Contents 512Mb I-die DDR2 SDRAM 1. Ordering Information ..............................4 2. Key Features................................. 4 3. Package pinout/Mechanical Dimension & Addressing....................5 3.1 x4 Package Pinout (Top view) : 60ball FBGA Package ..................5 3.2 x8 Package Pinout (Top view) : 60ball FBGA Package ..................

  • Page 60: Ordering Information

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 1. Ordering Information Org. DDR2-1066 7-7-7 DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 5-5-5 Package 128Mx4 K4T51043QI-HC(L)E7 K4T51043QI-HC(L)F7 K4T51043QI-HC(L)E6 60 FBGA 64Mx8 K4T51083QI-HC(L)E7 K4T51083QI-HC(L)F7 K4T51083QI-HC(L)E6 60 FBGA 32Mx16 K4T51163QI-HC(L)F8 K4T51163QI-HC(L)E7 K4T51163QI-HC(L)F7 K4T51163QI-HC(L)E6 84 FBGA NOTE : 1.

  • Page 61: Package Pinout/Mechanical Dimension & Addressing

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 3. Package pinout/Mechanical Dimension & Addressing 3.1 x4 Package Pinout (Top view) : 60ball FBGA Package SSDL A10/AP NOTE : 1. Pin B3 has identical capacitance as pin B7. 2. V and V are power and ground for the DLL.

  • Page 62: X8 Package Pinout (Top View) : 60Ball Fbga Package

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 3.2 x8 Package Pinout (Top view) : 60ball FBGA Package RDQS RDQS SSDL A10/AP NOTE : 1. Pins B3 and A2 have identical capacitance as pins B7 and A8. 2. For a read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input masking function is disabled. 3.

  • Page 63: X16 Package Pinout (Top View) : 84Ball Fbga Package

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 3.3 x16 Package Pinout (Top view) : 84ball FBGA Package UDQS DQ14 UDQS DQ15 DQ12 DQ11 DQ10 DQ13 LDQS LDQS SSDL A10/AP NOTE : 1. VDDL and VSSDL are power and ground for the DLL. 2.

  • Page 64: Fbga Package Dimension (X4/X8)

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 3.4 FBGA Package Dimension (x4/x8) Units : Millimeters 7.50 ± 0.10 0.80 x 8 = 6.40 # A1 INDEX MARK 1.60 0.80 MOLDING AREA (Datum A) (Datum B) (0.95) 60-∅0.45 Solder ball (1.90) (Post reflow 0.50 ±...

  • Page 65: Fbga Package Dimension (X16)

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 3.5 FBGA Package Dimension (x16) Units : Millimeters 7.50 ± 0.10 0.80 x 8 = 6.40 # A1 INDEX MARK MOLDING AREA 3.20 0.80 1.60 (Datum A) (Datum B) (0.95) 84-∅0.45 Solder ball (Post reflow 0.50 ±...

  • Page 66: Input/Output Functional Description

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 4. Input/Output Functional Description Symbol Type Function Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the CK, CK Input positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).

  • Page 67: Ddr2 Sdram Addressing

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 5. DDR2 SDRAM Addressing 512Mb Configuration 128Mb x4 64Mb x 8 32Mb x16 # of Bank Bank Address BA0,BA1 BA0,BA1 BA0,BA1 Auto precharge A10/AP A10/AP A10/AP Row Address A0 ~ A13 A0 ~ A13 A0 ~ A12 Column Address A0 ~ A9,A11...

  • Page 68: Absolute Maximum Ratings

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 6. Absolute Maximum Ratings Symbol Parameter Rating Units NOTE Voltage on V pin relative to V - 1.0 V ~ 2.3 V Voltage on V pin relative to V - 0.5 V ~ 2.3 V Voltage on V pin relative to V - 0.5 V ~ 2.3 V...

  • Page 69: Operating Temperature Condition

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 7.2 Operating Temperature Condition Symbol Parameter Rating Units NOTE °C Operating Temperature 0 to 95 1, 2 OPER NOTE : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2.

  • Page 70: Differential Input Ac Logic Level

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 7.6 Differential input AC logic Level Symbol Parameter Min. Max. Units NOTE (AC) AC differential input voltage (AC) 0.5 * V - 0.175 0.5 * V + 0.175 AC differential cross point voltage NOTE : 1.

  • Page 71: Ocd Default Characteristics

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 9. OCD default characteristics Description Parameter Unit NOTE 18ohm at norminal condition Output impedance See full strength default driver characteristics on device operation specification Output impedance step size for OCD calibration Pull-up and pull-down mismatch 1,2,3 Output slew rate Sout...

  • Page 72: Idd Specification Parameters And Test Conditions

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 10. IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes 1 - 5) Symbol Proposed Conditions Units NOTE Operating one bank active-precharge current; IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);...
  • Page 73 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI NOTE : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4.

  • Page 74: Ddr2 Sdram Idd Spec Table

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 11. DDR2 SDRAM IDD Spec Table 128Mx4 (K4T51043QI) Symbol 800@CL=5 800@CL=6 667@CL=5 Unit NOTE IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5 IDD6 IDD7 64Mx8 (K4T51083QI) Symbol 800@CL=5 800@CL=6 667@CL=5 Unit Notes...
  • Page 75 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 32Mx16 (K4T51163QI) Symbol 1066@CL=7 800@CL=5 800@CL=6 667@CL=5 Unit NOTE IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5 IDD6 IDD7 Page 59 of 152...

  • Page 76: Input/Output Capacitance

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 12. Input/Output capacitance DDR2-667 DDR2-800 DDR2-1066 Parameter Symbol Units Input capacitance, CK and CK Input capacitance delta, CK and CK CDCK 0.25 0.25 0.25 Input capacitance, all other input-only pins 1.75 1.75 Input capacitance delta, all other input-only pins 0.25 0.25...

  • Page 77: Timing Parameters By Speed Grade

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 13.3 Timing Parameters by Speed Grade (For information related to the entries in this table, refer to both the general notes and the specific notes following this table.) DDR2-1066 DDR2-800 DDR2-667 Parameter Symbol Units NOTE...
  • Page 78 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI DDR2-1066 DDR2-800 DDR2-667 Parameter Symbol Units NOTE Four Activate Window for 1KB page size products tFAW 37.5 Four Activate Window for 2KB page size products tFAW CAS to CAS command delay tCCD Write recovery time Auto precharge write recovery + precharge time tDAL...

  • Page 79: General Notes, Which May Apply For All Ac Parameters

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 14. General notes, which may apply for all AC parameters 1. DDR2 SDRAM AC timing reference load Figure 3 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise repre sentation of the typical system environment or a depiction of the actual load presented by a production tester.
  • Page 80 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen- dent.

  • Page 81: Specific Notes For Dedicated Ac Parameters

    Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 15. Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing.
  • Page 82 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI [ Table 3 ] DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table) DQS Single-ended Slew Rate 2.0 V/ns 1.5 V/ns 1.0 V/ns...
  • Page 83 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min to ac region (DC)min nominal slew rate (DC) nominal slew rate (DC)max to ac region (AC)max tVAC ΔTF ΔTR (DC) - V (AC)max (AC)min - V (DC) Setup Slew Rate Setup Slew Rate ΔTF Rising Signal ΔTR...
  • Page 84 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min (DC)min Note1 (DC) (DC)max (AC)max (AC)min to ac region (DC)min nominal slew rate (DC) nominal slew rate (DC)max to ac region (AC)max ΔTF ΔTR (DC) - V (AC)max (AC)min - V (DC) Setup Slew Rate Setup Slew Rate...
  • Page 85 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI nominal line (AC)min to ac region (DC)min tangent line (DC) tangent line (DC)max to ac region (AC)max nominal line ΔTR tangent line[V (AC)min - V (DC)] Setup Slew Rate ΔTF Rising Signal ΔTR tangent line[V (DC) - V...
  • Page 86 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min (DC)min Note1 (DC) (DC)max (AC)max nominal line (AC)min to ac region (DC)min tangent line (DC) tangent line (DC)max to ac region (AC)max nominal ΔTR line tangent line[V (AC)min - V (DC)] Setup Slew Rate Rising Signal ΔTR...
  • Page 87 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min (DC)min dc to V nominal region slew rate (DC) nominal dc to V slew rate region (DC)max (AC)max ΔTF ΔTR (DC) - V (DC)max Hold Slew Rate (DC)min - V (DC) Hold Slew Rate Rising Signal ΔTR...
  • Page 88 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min (DC)min Note1 (DC) (DC)max (AC)max (AC)min (DC)min dc to V nominal region slew rate (DC) nominal dc to V slew rate region (DC)max (AC)max ΔTF ΔTR (DC) - V (DC)max Hold Slew Rate (DC)min - V (DC) Hold Slew Rate...
  • Page 89 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min nominal line (DC)min dc to V tangent region line (DC) tangent dc to V line region nominal line (DC)max (AC)max ΔTF ΔTR Hold Slew Rate tangent line [ V (DC) - V (DC)max ] ΔTR Rising Signal...
  • Page 90 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min (DC)min Note1 (DC) (DC)max (AC)max (AC)min nominal line (DC)min dc to V tangent region line (DC) tangent dc to V line region nominal line (DC)max (AC)max ΔTF ΔTR tangent line [ V (DC) - V (DC)max ] Hold Slew Rate...
  • Page 91 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 9. tIS and tIH (input setup and hold) derating Derating values for DDR2-400, DDR2-533 [ Table 4 ] ΔtIS, ΔtIH Derating Values for DDR2-400, DDR2-533 CK, CK Differential Slew Rate 2.0 V/ns 1.5 V/ns 1.0 V/ns Units...
  • Page 92 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI [ Table 5 ] Derating values for DDR2-667, DDR2-800, DDR2-1066 ΔtIS and ΔtIH Derating Values for DDR2-667, DDR2-800, DDR2-1066 CK, CK Differential Slew Rate 2.0 V/ns 1.5 V/ns 1.0 V/ns Units NOTE ΔtIS ΔtIH ΔtIS...
  • Page 93 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min to ac region (DC)min nominal slew rate (DC) nominal slew rate (DC)max to ac region (AC)max ΔTF ΔTR (DC) - V (AC)max (AC)min - V (DC) Setup Slew Rate Setup Slew Rate ΔTF Rising Signal ΔTR...
  • Page 94 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI nominal line (AC)min to ac region (DC)min tangent line (DC) tangent line (DC)max to ac region (AC)max nominal line ΔTR tangent line[V (AC)min - V (DC)] Setup Slew Rate ΔTR ΔTF Rising Signal tangent line[V (DC) - V (AC)max]...
  • Page 95 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min (DC)min dc to V nominal region slew rate (DC) nominal dc to V slew rate region (DC)max (AC)max ΔTF ΔTR (DC) - V (DC)max Hold Slew Rate (DC)min - V (DC) Hold Slew Rate Rising Signal ΔTR...
  • Page 96 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI (AC)min nominal line (DC)min dc to V tangent region line (DC) tangent dc to V line region nominal (DC)max line (AC)max ΔTF ΔTR tangent line [ V (DC) - V (DC)max ] Hold Slew Rate Rising Signal ΔTR...
  • Page 97 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
  • Page 98 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V (AC) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V (AC) level to the differential data strobe crosspoint for a falling signal applied to the device under test.
  • Page 99 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 24. tWTR is at lease two clocks (2 x tCK or 2 x nCK) independent of operation frequency. 25. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input signal crossing at the V (AC) level to the sin- gle-ended data strobe crossing V (DC) at the start of its transition for a rising signal, and from the input signal crossing at the V...
  • Page 100 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI Definitions : - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. ∑ tCK(avg) = j = 1 N = 200 where - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
  • Page 101 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) Parameter Symbol Units...
  • Page 102 Rev. 1.0 K4T51043QI datasheet K4T51083QI DDR2 SDRAM K4T51163QI 44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH of 0.45, the tAOFmin should be derated by subtracting 0.05 x tCK from it, whereas if an input clock has a worst case tCH of 0.55, the tAOFmax should be derated by adding 0.05 x tCK to it.
  • Page 103 PRELIMINARY KH25L1605D KH25L3205D KH25L6405D 16M-BIT [x 1 / x 2] CMOS SERIAL FLASH 32M-BIT [x 1 / x 2] CMOS SERIAL FLASH FEATURES 64M-BIT [x 1 / x 2] CMOS SERIAL FLASH GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 •...
  • Page 104 KH25L1605D KH25L3205D KH25L6405D • Status Register Feature • Electronic Identification JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - Both REMS and REMS2 commands for 1-byte manufacturer ID and 1-byte device ID HARDWARE FEATURES •...
  • Page 105 KH25L1605D KH25L3205D KH25L6405D To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details.
  • Page 106 KH25L1605D KH25L3205D KH25L6405D PIN CONFIGURATIONS 16-PIN SOP (300mil) 8-PIN SOP (200mil, 150mil) HOLD# SCLK SI/SIO0 SO/SIO1 HOLD# WP#/ACC SCLK SI/SIO0 SO/SIO1 WP#/ACC 8-PIN PDIP (300mil) 8-LAND WSON (8x6mm, 6x5mm) for KH25Lxx05D SO/SIO1 HOLD# HOLD# SO/SIO1 WP#/ACC SCLK SCLK WP#/ACC SI/SIO0 SI/SIO0 PIN DESCRIPTION PACKAGE OPTIONS...
  • Page 107 KH25L1605D KH25L3205D KH25L6405D BLOCK DIAGRAM Address Generator Memory Array Page Buffer Data SI/SIO0 Register Y-Decoder SO/SIO1 SRAM Buffer Sense CS#, Amplifier Mode State WP#/ACC, Logic Machine HOLD# Generator SCLK Clock Generator Output Buffer Page 91 of 152...
  • Page 108 KH25L1605D KH25L3205D KH25L6405D ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature 0°C to 70°C for commercial grade Storage Temperature -55°C to 125°C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V NOTICE: 1.
  • Page 109 KH25L1605D KH25L3205D KH25L6405D Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level Output timing referance level 0.8VCC 0.7VCC Measurement 0.5VCC Level 0.3VCC 0.2VCC Note: Input pulse rise and fall time are <5ns Figure 7. OUTPUT LOADING DEVICE UNDER 2.7K ohm +3.3V TEST...
  • Page 110 KH25L1605D KH25L3205D KH25L6405D Table 9. DC CHARACTERISTICS (Temperature = 0° ° ° ° ° C to 70° ° ° ° ° C for Commercial grade, VCC = 2.7V ~ 3.6V) SYMBOL PARAMETER NOTES MIN. MAX. UNITS TEST CONDITIONS ± 2 Input Load VCC = VCC Max Current...
  • Page 111 KH25L1605D KH25L3205D KH25L6405D Table 10. AC CHARACTERISTICS (Temperature = 0° ° ° ° ° C to 70° ° ° ° ° C for Commercial grade, VCC = 2.7V ~ 3.6V) Symbol Alt. Parameter Min. Typ. Max. Unit fSCLK Clock Frequency for the following instructions: 1KHz FAST_READ, PP, SE, BE, CE, DP, RES,RDP (Condition:15pF)
  • Page 112 KH25L1605D KH25L3205D KH25L6405D Symbol Alt. Parameter Min. Typ. Max. Unit Write Status Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time Block Erase Cycle Time Chip Erase Cycle Time 64Mb 32Mb 16Mb Notes: 1. tCH + tCL must be greater than or equal to 1/ fC 2.
  • Page 113 KH25L1605D KH25L3205D KH25L6405D Table 11. Power-Up Timing and VWI Threshold Symbol Parameter Min. Max. Unit tVSL(1) VCC(min) to CS# low tPUW(1) Time delay to Write instruction VWI(1) Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh).
  • Page 114 KH25L1605D KH25L3205D KH25L6405D Figure 8. Serial Input Timing tSHSL tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH High-Z Figure 9. Output Timing SCLK tCLQV tCLQV tSHQZ tCLQX tCLQX tQLQH tQHQL ADDR.LSB IN Page 98 of 152...
  • Page 115 KH25L1605D KH25L3205D KH25L6405D Figure 10. Hold Timing tHLCH tCHHL tHHCH SCLK tCHHH tHLQZ tHHQX HOLD# * SI is "don't care" during HOLD operation. Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 tSHWL tWHSL SCLK High-Z Page 99 of 152...
  • Page 116 KH25L1605D KH25L3205D KH25L6405D Figure 12. Write Enable (WREN) Sequence (Command 06) SCLK Command High-Z Figure 13. Write Disable (WRDI) Sequence (Command 04) SCLK Command High-Z Figure 14. Read Identification (RDID) Sequence (Command 9F) 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK...
  • Page 117 KH25L1605D KH25L3205D KH25L6405D Figure 15. Read Status Register (RDSR) Sequence (Command 05) 9 10 11 12 13 14 15 SCLK command Status Register Out Status Register Out High-Z Figure 16. Write Status Register (WRSR) Sequence (Command 01) 9 10 11 12 13 14 15 SCLK command Status...
  • Page 118 KH25L1605D KH25L3205D KH25L6405D Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B) 9 10 28 29 30 31 SCLK Command 24 BIT ADDRESS 22 21 High-Z 32 33 34 36 37 38 39 40 41 42 43 44 45 46 SCLK Dummy Byte DATA OUT 2...
  • Page 119 KH25L1605D KH25L3205D KH25L6405D Figure 19. 2 x I/O Read Mode Sequence (Command BB) 9 10 11 18 19 20 21 22 23 24 25 26 27 SCLK data address BB(hex) dummy SI/SIO0 bit6, bit4, bit2...bit0, bit6, bit4..bit22, bit20, bit18...bit0 High Impedance address data...
  • Page 120 KH25L1605D KH25L3205D KH25L6405D Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) 20 21 22 23 30 31 31 47 48 6 7 8 6 7 8 9 SCLK Command data in Valid data in 04 (hex) 05 (hex) AD (hex) 24-bit address...
  • Page 121 KH25L1605D KH25L3205D KH25L6405D Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) SCLK Command 60 or C7 Note: CE command is 60(hex) or C7(hex). Figure 25. Deep Power-down (DP) Sequence (Command B9) SCLK Command Deep Power-down Mode Stand-by Mode Figure 26.
  • Page 122 KH25L1605D KH25L3205D KH25L6405D Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB) RES1 SCLK Command High-Z Deep Power-down Mode Stand-by Mode Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF) 9 10 SCLK Command 2 Dummy Bytes 15 14 13 High-Z...
  • Page 123 KH25L1605D KH25L3205D KH25L6405D Figure 29. Power-up Timing V CC V CC (max) Program, Erase and Write Commands are Ignored Chip Selection is Not Allowed V CC (min) tVSL Read Command is Device is fully Reset State allowed accessible of the Flash V WI tPUW...
  • Page 124 KH25L1605D KH25L3205D KH25L6405D RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) tSHSL tCHSL...
  • Page 125 KH25L1605D KH25L3205D KH25L6405D ERASE AND PROGRAMMING PERFORMANCE PARAMETER Min. TYP. (1) Max. (2) UNIT Write Status Register Cycle Time Sector Erase Time Block Erase Time 64Mb Chip Erase Time 32Mb 16Mb 64Mb Chip Erase Time (at ACC mode) 32Mb 16Mb Byte Program Time (via page program command) Page Program Time Page Program Time (at ACC mode)
  • Page 126 All information in this data sheet is preliminary and subject to change. The MAX3543 broadband single conversion television ♦ tuner is designed for use in hybrid analog (PAL, SECAM) + ♦ digital (DVB T, GB20600) television sets and terrestrial ♦ receivers.
  • Page 127 !"# $ &' VCC to GND ..............(0.3V, +3.6V Operating Temperature .........0°C to +70°C RFIN, IFVGAIN+, IFVGAIN(, Junction Temperature ........... +150°C IFOUT1+, IFOUT1(, IFOUT2, ....... (0.3V, Vcc+0.3V Storage Temperature..........(65°C to +165°C SDA, SCLK, IFAGC, RFVGA ........(0.3V, +3.6V Lead Temperature (soldering 10 sec.)........+300°C IFOUT1, IFOUT Short Circuit Protection......
  • Page 128 Wideband Detector Input Programmable, R0B<6:4> = 100, Referred Attack Point 9.5dB Vpp(to(Vrms modulated waveform Narrowband Detector Programmable, R0B<2:0> = 100, Input Referred Attack 9.5dB Vpp(to(Vrms modulated waveform Point 0 , & RF N Divider Integer Part Fractional(N Resolution Bits Phase Detector Frequency FREF/2 10.5 Phase Detector Frequency FREF/1 , ! ,...
  • Page 129 5:" UHF RF Input Pin. Matched to 75H over the operating band. Requires a DC blocking UHF_IN capacitor. RF Ground. Bypass to the PC board’s ground plane with a 1000pF capacitor. RFGND1 1 5B 1 5+ RFVGC RF VGA Gain Control Voltage. Accepts a DC voltage from 0.5V to 3V (max gain). VCC_IF IF Supply.
  • Page 130 SY8008A/SY8008B/SY8008C High Efficiency 1.5MHz, 0.6A/1A/1.2A Synchronous Step Down Regulator Preliminary Spec General Description Features • low Rds(on) for internal switches (top/bottom) The SY8008A, SY8008B and SY8008C are high- ο SY8008A: 300m efficiency 1.5MHz synchronous step-down DC-DC /250m , 0.6A ο SY8008B: 250m regulator ICs capable of delivering up to 1.2A output /200m , 1A ο...
  • Page 131 SY8008A/SY8008B/SY8008C Pinout (top view) (SOT23-5, TSOT23-5) Top mark: AAxyz for SY8008AAAC, ABxyz for SY8008BAAC, ACxyz for SY8008CAAC, BIxyz for SY8008AACC, BGxyz for SY8008BACC (Device code: AA for SY8008AAAC, etc., x=year code, y=week code, z= lot number code) Pin Name Pin Description Number Enable control.
  • Page 132 SY8008A/SY8008B/SY8008C Electrical Characteristics = 3.6V, V = 2.5V, L = 2.2uH, C = 10uF, T = 25°C, I = 1A unless otherwise specified) Parameter Symbol Test Conditions Unit Input Voltage Range Shutdown Current EN=0 µA SHDN Feedback Reference VREF 0.588 0.612 Voltage FB Input Current...
  • Page 133 SY8008A/SY8008B/SY8008C SOT23-5 Package outline & PCB layout design 0.55 0.55 2.80 - 3.10 2.80 - 3.10 0.95 TYP 0.95 TYP 0.30 - 0.50 0.30 - 0.50 Recommended Pad Layout 1.0 - 1.3 1.0 - 1.3 0.95 TYP 0.95 TYP 0.3 - 0.6 0.3 - 0.6 1.90 TYP 1.90 TYP...
  • Page 134 SY8008A/SY8008B/SY8008C TSOT23-5 Package outline & PCB layout design 0.55 0.55 2.80 - 3.10 2.80 - 3.10 0.95 TYP 0.95 TYP 0.30 - 0.50 0.30 - 0.50 Recommended Pad Layout 1.00 (max) 0.95 TYP 0.3 - 0.6 1.90 TYP All dimensions are in millimeters. Notes: All dimensions don’t include mold flash &...
  • Page 135 SY8009A/SY8009B High Efficiency 1.5MHz/1MHz, 1.5A/2A Synchronous Step Down Regulator Preliminary Spec General Description Features • low Rds(on) for internal switches (top/bottom) The SY8009A and SY8009B are high-efficiency , high frequency synchronous step-down DC-DC regulator SY8009A: 200mohm/150mohm, 1.5A, ICs capable of delivering up to 1.5A/2A output SOT23-5 currents.
  • Page 136 SY8009A/SY8009B Pinout (top view) (SY8009A, SOT23-5) (SY8009B, SSOT23-6) Top Mark: ADxyz for SY8009A , ASxyz for SY8009B ( Device code: AD for SY8009A and AS for SY8009B, x=year code, y=week code, z= lot number code) Pin Number Pin Description Name Enable control.
  • Page 137 SY8009A/SY8009B Electrical Characteristics = 5V, V = 2.5V, L = 2.2uH, C = 10uF, T = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Unit Input Voltage Range ⋅ Quiescent Current VFB=VREF 105% µA OUT= Shutdown Current EN=0 µA SHDN Feedback Reference VREF 0.588...
  • Page 138 SY8009A/SY8009B SOT23-5 Package outline & PCB layout design 0.55 0.55 2.80 - 3.10 2.80 - 3.10 0.95 TYP 0.95 TYP 0.30 - 0.50 0.30 - 0.50 Recommended Pad Layout 1.0 - 1.3 1.0 - 1.3 0.95 TYP 0.95 TYP 0.3 - 0.6 0.3 - 0.6 1.90 TYP 1.90 TYP...
  • Page 139 SY8009A/SY8009B SSOT23-6 Package outline & PCB layout design 1.90 1.90 0.95 0.95 0.25 - 0.40 0.60 0.60 Recommended Pad Layout 2.95 - 3.10 2.95 - 3.10 0.30 - 0.60 0.30 - 0.60 0.95 TYP 0.95 TYP Notes: All dimensions are in millimeters. All dimensions don’t include mold flash &...
  • Page 140 SY8132 High Efficiency 400kHz, 2A,16V Input Synchronous Step Down Regulator Preliminary SPECIFICATION General Description Features • low Rds(on) for internal switches (top/bottom): The SY8132 is a high efficiency 400 kHz synchronous step-down DC-DC converters capable of delivering 2A 150/100 mΩ •...
  • Page 141 SY8132 Pinout (top view) (SO8) Pin Description Name Number Boot-Strap Pin. Supply high side gate driver. Decouple this pin to LX pin with 0.1uF ceramic cap. Input pin. Decouple this pin to GND pin with at least 1uF ceramic cap Inductor pin.
  • Page 142 SY8132 Electrical Characteristics = 12V, V = 2.5V, L = 2.2uH, C = 10uF, T = 25°C, I = 1A unless otherwise specified) Parameter Symbol Test Conditions Unit Input Voltage Range Quiescent Current VFB=VREF+5% µA OUT=0, Shutdown Current EN=0 µA SHDN Feedback Reference VREF...
  • Page 143 SY8132 SO8 Package outline & PCB layout design 1.27 TYP 1.27 TYP 0.30 – 0.50 0.30 – 0.50 0.60 0.60 Recommended Pad Layout 0.25 - 0.50 0.25 - 0.50 4.80 - 5.00 4.80 - 5.00 0.60 - 0.85 0.60 - 0.85 1.27 (TYP) 1.27 (TYP) Notes: All dimensions are in millimeters.
  • Page 144 SY8133 High Efficiency 400KHz, 3A,16V Input Synchronous Step Down Regulator Preliminary SPECIFICATION General Description Features • low Rds(on) for internal switches (top/bottom) The SY8133 is a high efficiency 400 KHz synchronous step-down DC-DC converters capable of delivering 3A 120/80 m , •...
  • Page 145 SY8133 Pinout top view) (SO8E) Top Mark: AAWxyz (device code: AAW, x=year code, y=week code, z= lot number code) Pin Description Name Number Boot-Strap Pin. Supply high side gate driver. Decouple this pin to LX pin with 0.1uF ceramic cap. Input pin.
  • Page 146 SY8133 Electrical Characteristics = 12V, V = 2.5V, L = 2.2uH, C = 10uF, T = 25°C, I = 1A unless otherwise specified) Parameter Symbol Test Conditions Input Voltage Range Quiescent Current VFB=VREF+5% µA OUT=0, Shutdown Current EN=0 µA SHDN Feedback Reference VREF 0.588...
  • Page 147 SY8133 SO8E Package outline & PCB layout design 1.27 TYP 3.20 0.60 0.30 – 0.50 0.30 – 0.50 Recommended Pad Layout 0.25 - 0.50 0.25 - 0.50 4.80 - 5.00 4.80 - 5.00 0.60 - 0.85 0.60 - 0.85 1.27 (TYP) 1.27 (TYP) Notes: All dimensions are in millimeters.
  • Page 148 PCB INFORMATION PCB of main board-1 Page 132 of 152...
  • Page 149 PCB of main board-2 Page 133 of 152...
  • Page 150 PCB of main board-3 Page 134 of 152...
  • Page 151 PCB of main board-4 Page 135 of 152...
  • Page 152 PCB of main board-5 Page 136 of 152...
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  • Page 160 UPGRADE SOFTWARE There are three method to update sw for MSD306 project: 1. USB port(TV must be display normally)； 2. ISP connector on board(blue 4pin connect)； 3. VGA port(need adapter)； The details as following: 1. USB port STEP1: cope correct file to usb disk(the file must named as “MERGE.bin”)； STEP2: plug usb disk into usb port on board,and ensure it is stable；...
  • Page 161 PIC3 2. ISP connect on board: usb update tool is used on this method.the tool as PIC4, of course,update SW is used together.it as PIC5 图 4 PIC5 STEP1: ensure usb tool connect correctly。As PIC6: Page 145 of 152...
  • Page 162 PIC6 NOTE:maybe ISP connector is different position on different type board,please find out the blue 4pin connector,it is correct ISP connector STEP2: run the update SW,and press connect button,you shall see the picture like PIC7. PIC7 PIC8 If picture looks like PIC8.please double check stpe1,and do step2 again. STEP3: press Read button,then select the correct update file.
  • Page 163 STEP4: press Auto button and set the parameters as PIC9,then press Run； PIC9 STEP5： please kindly wait a moment.it is finish as PIC10： PIC10 3. VGA PORT You need a adapter looks like PIC11. PIC11 Please ensure connect correctly with the VGA adapter,then do like ISP update steps. Page 147 of 152...
  • Page 164 Setup the USB TOOL driver as following: Please get the driver file from our engineer or saler ,file as PIC12： PIC12 STEP1: plug USB TOOL into usb port of your computer.the computer will auto check new HW,and lead you to setup driver.
  • Page 165 MSD306 Factory Menu 1. ADC ADJUST a. The pattern for YPbPr ADC must include red, green, blue, black and white. The black and white color is for calibration of Y, and the red, green and blue for PbPr. We use 100% color bar for auto ADC. YPbPr: 100% Color Bar b.The pattern for VGA ADC must include pure white(100IRE) and pure black(0IRE).
  • Page 166 2) OSD Language If we change OSD language, then Audio Language and Subtitle Language will change accordingly. 3) Audio Language Select the audio language for DTV program. 4) Subtitle Language Select the subtitle language for DTV program. 5) LCN Sorting We can choose LCN sorting for DTV program.
  • Page 167 shared, this adjustment for designer can use any panel of same resolution easily without compile the SW again. 6) AUDIO CURVE SWITCH For the OEM factory to adjust the volume curve as their request. 7) SSC For the designer only to adjust the LVDS and DDR CLK, to make EMI can pass the verification. 8) VIF1 For the designer only to finetune some parameter when configure different tuner.
  • Page 168 Choose the default source when power on. 4) HOTEL WELCOME MESSAGE We can decide whether to display the welcome message. 5) HOTEL KEY LOCK If we set KEY LOCK to on, the local keyboard will be disabled (the remote still works). 6) HOTEL TTX LOCK If we set TTX LOCK to on, the teletext will be disabled, and the TTX key will not work.
  • Page 169 Black Silver Black Stand color White Glossy Glossy Stand surface finishing Rubber paint Brushed TV specification 4TC0 I2 B1R A1 B5 Analog TV DVB-T DVB-T2 DVB-T/C DVB Digital signal demodulator DVB-T/C type DVB-T2/C DVB-T/S DVB-T/C/S T2CS DVB-T2/C/S MPEG2 BOM STV-24LEDGR7.xls...
  • Page 170 TV model name. Just click on the value , clik on the pop-up symbol [▼] and select new one from Comment: the pop-up list. - please make your parameters' selection in sequence from the top to the bottom of the list. This will let you to avoid Comment: incompatible parameters mistakes BOM STV-24LEDGR7.xls...
  • Page 171 Confidential 18-08-2021 Page 3 PARDAVIMO UŽSAKYMO LAPAS Gamybos registracijos Nr. Būsena: PO nr: Customer Tesco UK PO sukūrimo data: 27-10-2010 Customer code Užsakymo patvirtinimo data: Customer country TV nomenklatūrinis nr: Axapta PO Nr: Axapta PO Nr. garantiniams: Paruošė: Informacija planavimo valdymui PO nr: Component Order No.
  • Page 172 Confidential 18-08-2021 Page 4 Assembly level Required SKD content Full SKD, tuner separate Required CKD content SMPS; contol board Page 4 TV PO sheet...
  • Page 173 LCD panels list Frame rate LCD panel Resolution, LCD panel name (50Hz, Size, inches short name (HD,FHD) 100Hz) Not defined 15,4 50Hz 15,4 Not defined 15,6 50Hz 15,6 M185B1-L01 18,5 50Hz 18,5 MT185GW01 V.1 18.5L 50Hz 18,5 Not defined 50Hz Not defined 50Hz LTA216AT01...
  • Page 174 Back Light (LED,CCFL) CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL CCFL...
  • Page 175 4T518000001 Electric tape (10x20x0,09mm) 10x20x0,09mm (for tuner) 48 missing 4T521500001 Electric sponge 5x10x40mm (h=5mm) (for I/O bracket) 49 missing 40510000002 Nylon Tie 2,5x100mm for wire fixing 50 missing 60201800001 Fibre adhesive tape 20mmx50m (250mm for each TV) MSD30X BOM 18-08-2021 BOM STV-24LEDGR7.xls...

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