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1. Audio circuit (Circuit diagrams Main PWB)
1.1 Au dio in pu t
Th e au dio sig n al in pu t recei v ed from th e au dio in pu t termin al (JK011) i s appl ied to th e a mplifi er I001 of 4 (L-
CH) an d 9 (R-CH) th rou g h th e low-pass filt er c on sis tin g of R040, R041, R042, R043, C040 an d C041.
In th is amplifier, con trols of Volu me an d mu te are con du cted. Th e au dio sig n al con trolled at th e pin 6 determin es
th e atten u at ion of ou tpu t of th e amp lifiers. Sin ce th en , th e sig n al is ou tpu t to th e jack P003.
1.2 Au dio ou tpu t
Th e au dio s ig n al is ou tpu t from P002 ou tpu t termin al of th e Au dio block to th e in tern al spea ker sy stem.
2. Power supply (Circuit daigrams MAIN PWB)
2.1 Lin e fil ter c on sist s of C801, T801, C802, C803, C804. It eli min at es h i g h frequ en cy in terferen ce to me et EM I' s
req u ireme n t.
2.2 Rec & Filte r :
Bridg e diode D801 c on v erts AC so u rce in to pu lsed DC. Th is pu lsed DC i s smooth ed an d filtered b y C805.
R802 is an NTC ( n eg a tiv e th ermal c oefficien t ) resistor, u sed to redu ce in ru sh cu rren t to be with in safe ran g e.
2.3 Powe r tran sforme r :
T802 c on v erts en erg y for squ a re wav e fro m power sou rce C805 to secon dary s ide to g en erate +12V an d +5V.
2.4 Ou tpu t :
Th e squ are wav e from T802 is re ctifie d by D809, D810, th en filtered by C817, C822 to g e n erate +12V an d
+5V respe ctiv e ly .
2.4.1 A 5V power s u pply f or LCD modu le, CPU an d log ic i s g en era ted fro m th e p ower sou rce.
2.4.2 I308 : 3-t ermi n al reg u lat or
A 3.3V power su pply f or I306 a n alog is g en erate d from t h e 5V so u rce.
2.4.3 I308 : 3-t ermi n al reg u lat or
A 3.3V power su pply for I306 dig ita l is g e n erated from th e 5V sou rce.
Q302, Q303 ON/ OFF con t rol for LCD Modu le
ON/OFF con trol is performed for power ON/OFF an d also for th e p ower sav in g se qu en ce.
2.5
Driv er :
Q803 driv e T802 from PWM con tro l of I801 for po wer c on v ert ed.
2.6
FB :
Neg ativ e feedback CKT con si sts of ph oto cou p ler I802 an d adju s table reg u lator I803. It can main ta in ou tpu t
v olt ag es +5V an d +12V at a s table le v el.
2.7
PWM :
2.7.1 Start : W h en power is t u rn ed o n , Q801 con du c ts du e to bias from C805 an d R805,R803. C807 is c h arg ed a 16
v olt an d a startin g cu rren t abou t 0.3mA to pin 7 of I801. I801 starts to os cillate an d ou tpu ts a pu lse train
th rou g h pin 6 to driv e Q803.
2.7.2 OPP : Wh e n Q803 tu rn s on , C805 su pplies a lin early in c reasin g tri an g le cu rre n t th rou g h th e primary in du c
tan ce of T802 to th e driv er Q803, on ce th e peak v a lu e of th is cu rren t mu ltipl ied by R811 exceed s1 v olt, pu lse
tra in will be sh u t down i mmediat ely to p rotect Q803, T 802 fro m bein g bu rn ed ou t.
2.7.3 Regulation : If ou tp u t v oltag e +5V g oes u p, th e R termin al of I803 g ets more b ias, accordin g ly ph o to tran sis
tor an d ph o to diode flows more cu rren t. Th e v oltag e of pin 2 g oes u p too, makin g th e pu lse width of pin 6 to
become n arrower. So t h e ou tpu t v ol tag e +5V will be pu lled down to a stable v alu e.
Ci rcu i t D escri p ti on
A L 502
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