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BitFlow Cyton-CXP Hardware Reference Manual

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The Cyton-CXP
Hardware Reference Manual
BitFlow, Inc.
400 West Cummings Park, Suite 5050
Woburn, MA 01801
USA
Tel: 781-932-2900
Fax: 781-933-9965
Email: support@bitflow.com
Web: www.bitflow.com
Revision A.0

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  • Page 1 The Cyton-CXP Hardware Reference Manual BitFlow, Inc. 400 West Cummings Park, Suite 5050 Woburn, MA 01801 Tel: 781-932-2900 Fax: 781-933-9965 Email: support@bitflow.com Web: www.bitflow.com Revision A.0...
  • Page 2 BitFlow, Inc. BitFlow, Inc. makes no implicit warranty for the use of its products and assumes no responsibility for any errors that may appear in this document, nor does it make a commit- ment to update the information contained herein.

  • Page 3: Table Of Contents

    Synchronizing the StreamSync Acquisition Engine With the Camera CYT-2-4 Regions Of Interest (ROI) with the StreamSync Acquisition Engine. CYT-2-4 Triggering the StreamSync Acquisition Enginer CYT-2-6 Comparing the StreamSync Acquisition Engine to Other BitFlow products CYT-2-7 AE_CON CYT-2-8 AE_STATUS CYT-2-10 BitFlow, Inc.
  • Page 4 BOARD_CONFIG CYT-3-11 PACKETS_SENT_STATUS CYT-3-13 QUADS_USED_STATUS CYT-3-15 QTABS_USED_STATUS CYT-3-17 PKT_STAT CYT-3-19 QUADS_LOADED_STATUS CYT-3-22 QTABS_LOADED_STATUS CYT-3-24 BUF_MGR_STATUS CYT-3-26 PKT_CON CYT-3-29 4 - Timing Sequencer Introduction CYT-4-1 Description CYT-4-1 TS_CONTROL CYT-4-3 TS_TABLE_CONTROL CYT-4-6 TS_TABLE_ENTRY CYT-4-8 5 - Quadrature Encoder Introduction CYT-5-1 BitFlow, Inc.
  • Page 5 Encoder Divider Details CYT-6-2 Formula CYT-6-2 Example CYT-6-2 Restrictions CYT-6-2 PLL Locking CYT-6-3 Handling Encoder Slow Down or Stopping CYT-6-3 Encoder Divider Control Registers CYT-6-4 7 - Karbon/Cyton-CXP I/O System Registers Introduction CYT-7-1 CON60 CYT-7-2 CON61 CYT-7-4 CON62 CYT-7-6 CON63 CYT-7-10 CON64 CYT-7-15...
  • Page 6 CON168 CYT-8-92 CON169 CYT-8-95 CON170 CYT-8-97 CON171 CYT-8-99 CON172 CYT-8-101 CON173 CYT-8-103 CON174 CYT-8-105 CON175 CYT-8-107 CON179 CYT-8-109 CON180 CYT-8-111 CON181 CYT-8-114 CON182 CYT-8-117 CON184 CYT-8-120 CON185 CYT-8-122 CON186 CYT-8-124 CON187 CYT-8-126 CON190 CYT-8-128 CON191 CYT-8-130 CON192 CYT-8-132 BitFlow, Inc.
  • Page 7 Introduction CYT-9-6 R64 GPIN Configuration CYT-9-6 Neon-CL GPIN Configuration CYT-9-6 Karbon-CL GPIN Configuration CYT-9-6 Karbon-CXP Input Configuration CYT-9-7 General Purpose Outputs (GPOUT) CYT-9-8 Introduction CYT-9-8 GPOUT Source Options (CL Only) CYT-9-8 R64 GPOUT Configuration CYT-9-8 Version Pre BitFlow, Inc. CYT-TOC-5...
  • Page 8 Switches CYT-10-3 LEDs CYT-10-5 CXP Downlink LED Meaning CYT-10-6 CXP Uplink LED Meaning CYT-10-6 Button CYT-10-7 The Auxilary Power Connector (P4) CYT-10-8 The I/O Box Connector (P1) CYT-10-9 I/O Connector Pinout for the Cyton-CXP CYT-10-10 CYT-TOC-6 BitFlow, Inc. Version Pre...

  • Page 9: Support Services Cyt

    Second, it is a reference manual describing in detail the functionality of all of the board’s registers. P.1.1 Support Services BitFlow, Inc. provides both sales and technical support for the Karbon family of prod- ucts. P.1.2 Technical Support Our web site is www.bitflow.com.
  • Page 10 Purpose The Cyton-CXP P.1.4 Conventions Table P-1 shows the conventions that are used for numerical notation in this manual. Table P-1 Base Abbreviations Base Designator Example Binary 1010b Decimal None 4223 Hexidecimal 12fah Table P-2 shows the numerical abbreviations that are used in this manual.

  • Page 11: Bitfield Definitions Cyt

    0 to 7. Finally this section also indicates if the register is specific to only one product family. Bitfield discussion This section explains the purposed of the bitfield in detail. Usually meaning of every possible value of the bitfield is listed. Version A.0 BitFlow, Inc. CYT-P-3...
  • Page 12 Neon This bitfield is functional only the Neon This bitfield is functional only the R64 family. Alta This bitfield is functional only the Alta family. Cyton-CXP This bitfield is functional only on the Cyton-CXP family CYT-P-4 BitFlow, Inc. Version A.0...

  • Page 13: General Description And Architecture

    Chapter 1 1.1 The Cyton-CXP family The purpose of this chapter is to explain, at a block diagram level, how the Cyton-CXP works. Currently there is two main models in the Cytron-CXP family: CYT-PC2-CXP4, provides four 6.25 Gb/S CXP links CYT-PC2-CXP2, provides two 6.25 Gb/S CXP links...

  • Page 14: Cyton Configuration Spaces Cyt-1-2

    The idea of modifying a frame grabber by making changes to its firmware is not new. BitFlow has been doing this since its very first product. However, unique to BitFlow products is the fact the entire frame grabber is written in firmware. The only fixed hardware components are the interfaces to the outside world (e.g.
  • Page 15 Only available on PCI Interface, PCI Interface, PCI Interface, PCI Interface, Karbon-CXP4 Buffer Manager Buffer Manager Buffer Manager Buffer Manager Device Device Device Device PCI Express Bus PCI Express Bus Figure 1-1 The Cyton-CXP Block Diagram Version A.0 BitFlow, Inc. CYT-1-3...

  • Page 16: Firmware, Camera Files And Downloads Cyt-1-4

    Firmware, Camera Files and Downloads The Cyton-CXP 1.2 Firmware, Camera Files and Downloads CYT-1-4 BitFlow, Inc. Version A.0...

  • Page 17: General Description Cyt-1-5

    General Description 1.3 General Description The Cyton-CXP is a x8 PCI Express Gen 2 board. It can work in any PCI Express slot that it can fit it. Usually this means an x8 or x16 slot. However, some mother boards have x4 slots with x8 connectors.

  • Page 18: Video Data Cyt-1-6

    (see Figure 1-2). From this point on the Cyton-CXP works very similar to all of BitFlow’s frame grabbers. The acquisition circuit determines which pixels of which lines of which frames are to be acquired.

  • Page 19: Cyton-Cxp I/O System Cyt-1-7

    Timing Sequencer. The Timing Sequencer (TS) is more flexible and more power than the timing generators used on early BitFlow frame grabbers. It has the ability to output multiple different size pulses, each of which can free-run or require a trigger.

  • Page 20: Coaxpress Power Cyt-1-8

    The CoaXPress specification specifies that the frame grabber must be cable of supply- ing up to 13 W at 24V on each CXP link. The Cyton-CXP conforms to this specification. Some cameras do not require power, so the Cyton-CXP can optionally turn power on or off via its registers.
  • Page 21 Manager 3 PCI Express Bus Figure 1-3 Cyton-CXP Routing Between CXP Links and VFG Figure 1-3 may look confusing, but all of the routing details are handle automatically by software, there is no need to worry about programming the routing tables manu- ally in your software.
  • Page 22 The BitFlow CXP Models The Cyton-CXP 1.5 The BitFlow CXP Models BitFlow currently makes three CoaXPress frame grabbers. Table 1-1 illustrates the capabilities of each model. Table 1-1 BitFlow CXP Models Capability KBN-PCE- KBN-PCE- CYT-PC2- CYT-PC2- CXP2 CXP4 CXP4 CXP4 Number of 3.125 Gb/S links supported...

  • Page 23: The Streamsync Acquisition Engine

    BitFlow frame grabbers. The StreamSync system is a start-from-scratch complete redesign of the acquisition and DMA parts of a frame grabber. BitFlow used it years of experience in this area to design a next generation, super efficient capture system.

  • Page 24: The Streamsync Acquisition Engine World Cyt-2-2

    The StreamSync Acquisition Engine World The Cyton-CXP 2.2 The StreamSync Acquisition Engine World We are used to concept that an image has an X and a Y dimension. The Acquisition Engine expands on this concept by adding two further dimension Z and V. The Z dimension controls a sequence of frames or “Volume”...
  • Page 25 Some windows can be opened in more than one way. For example the Y win- dow can be opened when a Start Of Frame (SOF) packet is sent from the camera, or it can be opened by a trigger (all SOF packets are ignored until the trigger condition is Version A.0 BitFlow, Inc. CYT-2-3...

  • Page 26: Observing The Streamsync Acquisition Engine Cyt-2-4

    The StreamSync Acquisition Engine World The Cyton-CXP met) or it can just be opened immediately, as soon the Acquisition Engine level is inside the X window (i.e. the stat above). Table 2-1 enumerates all of these condi- tions.. Table 2-1 Open Close Conditions...
  • Page 27 Similarly there is a Z_OFFS register which if non-zero can cause the board to discard a certain number of frames before starting an acquisition of a sequence. This concept is illustrated in Figure 2-4. V Window Z_OFFS Z_SIZE Z Window Y Window X Window Camera Frames Figure 2-4 Z_OFFS Illustration Version A.0 BitFlow, Inc. CYT-2-5...

  • Page 28: Triggering The Streamsync Acquisition Enginer Cyt-2-6

    Triggering the StreamSync Acquisition Enginer The Cyton-CXP 2.3 Triggering the StreamSync Acquisition Enginer One of the areas where the power of the Acquisition Engine is really seen is with regards to triggering. There are many more ways to use triggers in the Acquisition Engine.

  • Page 29: Comparing The Streamsync Acquisition Engine To Other Bitflow Products Cyt-2-7

    While the Acquisition Engine might seem very complex, it is actually quite simple to use, and has considerably more power than previous acquisition engines used on all previous BitFlow frame grabbers. From a software point of view, there BitFlow API hides the differences between the traditional acquisition systems and the newer Acquisition Engine.
  • Page 30 AE_CON The Cyton-CXP 2.5 AE_CON Name AE_RUN_LEVEL AE_RUN_LEVEL AE_RUN_LEVEL AE_RUN_LEVEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-2-8 BitFlow, Inc.
  • Page 31 The StreamSync Acquisition Engine AE_CON AE_RUN_LEVEL R/W, AE_CON[3..0], Cyton-CXP This is the main control for starting/aborting acquisition. Writing this register changes the current run level. Reading this register returns the current run level command (not the current status). The abort run levels exit acquisition on a clean boundary. V exits on a volume boundary, Z on a frame boundary, Y on a line boundary, X on a 128-byte data boundary.
  • Page 32 AE_STATUS The Cyton-CXP 2.6 AE_STATUS Name AE_STATE AE_STATE AE_STATE Reserved AE_FIFO_OVERFLOW Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-2-10 BitFlow, Inc.
  • Page 33 The StreamSync Acquisition Engine AE_STATUS AE_STATE RO, AE_STATUS[2..0], Cyton-CXP This register indicates the current run level of the acquisition engine. The following table shows the meanings of each state. AE_STATE Meaning 0 (000b) Idle - System is idle 1 (001b)
  • Page 34 AE_STREAM_SEL The Cyton-CXP 2.7 AE_STREAM_SEL Name STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL STREAM_SEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved USE_SYNTHETIC_FRAME CYT-2-12 BitFlow, Inc.

  • Page 35: Ae_Stream_Sel Cyt-2-12

    The StreamSync Acquisition Engine AE_STREAM_SEL STREAM_SEL R/W, AE_STREAM_SEL[7..0], Cyton-CXP TBD. USE_ R/W, AE_STREAM_SEL[31], Cyton-CXP SYNTHETIC_ FRAME Use the Synthetic Frame generator instead of the camera. Version A.0 BitFlow, Inc. CYT-2-13...
  • Page 36 V_WIN_DIM The Cyton-CXP 2.8 V_WIN_DIM Name V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE V_SIZE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-2-14 BitFlow, Inc.
  • Page 37 The StreamSync Acquisition Engine V_WIN_DIM V_SIZE R/W, V_WIN_DIM[15..0], Cyton-CXP This register defines size of the V window, that is, the number of volumes to acquire. A value of 0XFFFF means infinite. When set to infinite, the acquisition engine can be stopped by writing AE_RUN_LEVEL.
  • Page 38 Z_WIN_CON The Cyton-CXP 2.9 Z_WIN_CON Name Z_CLOSE_TRIG_FUNC Z_CLOSE_TRIG_FUNC Z_CLOSE_TRIG_FUNC Z_CLOSE_TRIG_FUNC Z_CLOSE_TRIG_SEL Z_CLOSE_TRIG_SEL Z_CLOSE_TRIG_SEL Z_CLOSE_TRIG_SEL Z_CLOSE Z_CLOSE Z_CLOSE Z_CLOSE Z_OPEN_TRIG_FUNC Z_OPEN_TRIG_FUNC Z_OPEN_TRIG_FUNC Z_OPEN_TRIG_FUNC Z_OPEN_TRIG_SEL Z_OPEN_TRIG_SEL Z_OPEN_TRIG_SEL Z_OPEN_TRIG_SEL Z_OPEN Z_OPEN Z_OPEN Z_OPEN Z_SYNC Z_SYNC Z_SYNC Z_SYNC Reserved Reserved Reserved Reserved CYT-2-16 BitFlow, Inc.
  • Page 39 The StreamSync Acquisition Engine Z_WIN_CON Z_CLOSE_TRIG_ R/W, Z_WIN_CON[3..0], Cyton-CXP FUNC This register determines which trigger change (if any) will end the Z window. Z_CLOSE_TRIG_FUNC Meaning 0 (0000b) Rising edge of trigger 1 (0001b) Falling edge of trigger 2 (0010b) Trigger is high...
  • Page 40 Z_WIN_CON The Cyton-CXP Z_OPEN_TRIG_ R/W, Z_WIN_CON[19..16], Cyton-CXP Selects which trigger will control the start Z wIndow. Z_OPEN R/W, Z_WIN_CON[23..20], Cyton-CXP This field specifies how the Z window starts. Possible values are: 0 - immediate mode, 1 - trigger mode. If immediate mode is specified, no trigger synchronization is required. The acquisition engine waits for any frame sync requirements, opens the Z window, then starts the setup of the Y window.
  • Page 41 2.10 Z_WIN_DIM Name Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_SIZE Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Z_OFFS Version A.0 BitFlow, Inc. CYT-2-19...
  • Page 42 Z_WIN_DIM The Cyton-CXP Z_SIZE R/W, Z_WIN_DIM[15..0], Cyton-CXP Number of frames (Y windows) to acquire per sequence (Z windows). The acquisition of frames will only start after Z_OFFS frames have been skipped after the Z window is opened. Z_OFFS R/W, Z_WIN_DIM[31..16], Cyton-CXP The number of frames (Y windows) to skip before starting acquisition after the Z win- dow has been opened.
  • Page 43 2.11 Y_WIN_CON Name Y_CLOSE_TRIG_FUNC Y_CLOSE_TRIG_FUNC Y_CLOSE_TRIG_FUNC Y_CLOSE_TRIG_FUNC Y_CLOSE_TRIG_SEL Y_CLOSE_TRIG_SEL Y_CLOSE_TRIG_SEL Y_CLOSE_TRIG_SEL Y_CLOSE Y_CLOSE Y_CLOSE Y_CLOSE Y_OPEN_TRIG_FUNC Y_OPEN_TRIG_FUNC Y_OPEN_TRIG_FUNC Y_OPEN_TRIG_FUNC Y_OPEN_TRIG_SEL Y_OPEN_TRIG_SEL Y_OPEN_TRIG_SEL Y_OPEN_TRIG_SEL Y_OPEN Y_OPEN Y_OPEN Y_OPEN Y_SYNC Y_SYNC Y_SYNC Y_SYNC Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-2-21...

  • Page 44: Y_Close_Trig_Func

    Y_WIN_CON The Cyton-CXP Y_CLOSE_TRIG_ R/W, Y_WIN_CON[3..0], Cyton-CXP FUNC This register determines which trigger change (if any) will end the Y window. Y_CLOSE_TRIG_FUNC Meaning 0 (0000b) Rising edge of trigger 1 (0001b) Falling edge of trigger 2 (0010b) Trigger is high...

  • Page 45: Y_Open_Trig_Sel

    The StreamSync Acquisition Engine Y_WIN_CON Y_OPEN_TRIG_ R/W, Y_WIN_CON[19..16], Cyton-CXP Selects which trigger will control the start Y wIndow. Y_OPEN R/W, Y_WIN_CON[23..20], Cyton-CXP This field specifies how the Y window starts. Possible values are: 0 - immediate mode, 1 - trigger mode.
  • Page 46 Y_WIN_DIM The Cyton-CXP 2.12 Y_WIN_DIM Name Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_SIZE Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS Y_OFFS CYT-2-24 BitFlow, Inc.
  • Page 47 The StreamSync Acquisition Engine Y_WIN_DIM Y_SIZE R/W, Y_WIN_DIM[15..0], Cyton-CXP Number of lines per frame (Y window) to acquire. This number is only acquired after the Y window is opened and after Y_OFFS lines have been skipped. Y_OFFS R/W, Y_WIN_DIM[31..16], Cyton-CXP Number of lines to skip before starting the acquisition of lines (after the Y windows is opened).
  • Page 48 X_WIN_DIM The Cyton-CXP 2.13 X_WIN_DIM Name X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_SIZE X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS X_OFFS CYT-2-26 BitFlow, Inc.
  • Page 49 The StreamSync Acquisition Engine X_WIN_DIM X_SIZE R/W, X_WIN_DIM[15..0], Cyton-CXP Number of 16-byte data words to acquired per line (X window). This number is only acquired after the X window is opened and after X_OFFS words have been skipped. X_OFFS R/W, X_WIN_DIM[31..16], Cyton-CXP Number of 16-byte data words to skip per line (after the Z window is opened).
  • Page 50 V_ACQUIRED The Cyton-CXP 2.14 V_ACQUIRED Name V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT V_ACQ_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved V_ACQ_COUNT_CLR_MODE V_ACQ_COUNT_CLR_MODE V_ACQ_COUNT_CLR_MODE Reserved CYT-2-28 BitFlow, Inc.
  • Page 51 The StreamSync Acquisition Engine V_ACQUIRED V_ACQ_COUNT R/W, V_ACQUIRED[15..0], Cyton-CXP Returns the total number of volumes (frame sequence) acquired since the last reset of this register. The behavior of this register when it reaches it maximum value depends on the register V_ACQ_COUNT_CLEAR_MODE. This register can be written to 0 by software at any time.
  • Page 52 Z_ACQUIRED The Cyton-CXP 2.15 Z_ACQUIRED Name Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Z_ACQ_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Z_ACQ_COUNT_CLR_MODE Z_ACQ_COUNT_CLR_MODE Reserved Reserved CYT-2-30 BitFlow, Inc.
  • Page 53 The StreamSync Acquisition Engine Z_ACQUIRED Z_ACQ_COUNT R/W, Z_ACQUIRED[15..0], Cyton-CXP Returns the total number of frames acquired since the last reset of this register. he behavior of this register when it reaches it maximum value depends on the register Z_ ACQ_COUNT_CLEAR_MODE. This register can be written to 0 by software at any time.
  • Page 54 Y_ACQUIRED The Cyton-CXP 2.16 Y_ACQUIRED Name Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Y_ACQ_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Y_ACQ_COUNT_CLR_MODE Y_ACQ_COUNT_CLR_MODE Reserved Reserved CYT-2-32 BitFlow, Inc.
  • Page 55 The StreamSync Acquisition Engine Y_ACQUIRED Y_ACQ_COUNT R/W, Y_ACQUIRED[15..0], Cyton-CXP Returns the total number of lines acquired since the last reset of this register. he behavior of this register when it reaches it maximum value depends on the register Y_ ACQ_COUNT_CLEAR_MODE. This register can be written to 0 by software at any time.
  • Page 56 X_ACQUIRED The Cyton-CXP 2.17 X_ACQUIRED Name X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT X_ACQ_COUNT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved X_ACQ_COUNT_CLR_MODE X_ACQ_COUNT_CLR_MODE Reserved Reserved CYT-2-34 BitFlow, Inc.
  • Page 57 The StreamSync Acquisition Engine X_ACQUIRED X_ACQ_COUNT R/W, X_ACQUIRED[15..0], Cyton-CXP Returns the total number of 16-bit words acquired since the last reset of this register. he behavior of this register when it reaches it maximum value depends on the register X_ACQ_COUNT_CLEAR_MODE. This register can be written to 0 by software at any time.
  • Page 58 CON489 The Cyton-CXP 2.18 CON489 Name INT_Z_ACQUIRED INT_Y_ACQUIRED INT_V_ACQUIRED Reserved INT_ENC_B INT_ENC_A INT_TRIG Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_BM_ERROR INT_AE_LOSS_OF_SYNC INT_PCIE_PKT_DROPPED INT_Z_ACQUIRED_LEGACY Reserved Reserved CYT-2-36 BitFlow, Inc.
  • Page 59 The StreamSync Acquisition Engine CON489 INT_Z_ R/W, CON489[0], Cyton-CXP ACQUIRED Z window closed interrupt. INT_Y_ R/W, CON489[1], Cyton-CXP ACQUIRED Y window closed interrupt. INT_V_ R/W, CON489[2], Cyton-CXP ACQUIRED V window closed interrupt.. INT_ENC_B R/W, CON489[4], Cyton-CXP Encoder B interrupt. INT_ENC_A R/W, CON489[5], Cyton-CXP Encoder A interrupt.
  • Page 60 CON490 The Cyton-CXP 2.19 CON490 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_ANY ENINT_ALL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-2-38 BitFlow, Inc.
  • Page 61 The StreamSync Acquisition Engine CON490 INT_ANY RO, CON490[7], Cyton-CXP There is at least on active interrupt on the board. ENINT_ALL R/W, CON490[8], Cyton-CXP Set to 1 to enable board interrupts. Version A.0 BitFlow, Inc. CYT-2-39...
  • Page 62 CON548 The Cyton-CXP 2.20 CON548 Name INT_Z_ACQUIRED_M INT_Y_ACQUIRED_M INT_V_ACQUIRED_M Reserved INT_ENC_B_M INT_ENC_A_M INT_TRIG_M Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_BM_ERROR_M INT_AE_LOSS_OF_SYNC_M INT_PCIE_PKT_DROPPED_M INT_Z_ACQUIRED_LEGACY_M Reserved Reserved CYT-2-40 BitFlow, Inc.
  • Page 63 The StreamSync Acquisition Engine CON548 INT_Z_ R/W, CON548[0], Cyton-CXP ACQUIRED_M INT_Z_ACQUIRED mask. INT_Y_ R/W, CON548[1], Cyton-CXP ACQUIRED_M INT_Y_ACQUIRED mask. INT_V_ R/W, CON548[2], Cyton-CXP ACQUIRED_M INT_V_ACQUIRED mask. INT_ENC_B_M R/W, CON548[4], Cyton-CXP INT_ENC_B mask. INT_ENC_A_M R/W, CON548[5], Cyton-CXP INT_ENC_A mask. INT_TRIG_M R/W, CON548[6], Cyton-CXP INT_TRIG mask.
  • Page 64 CON549 The Cyton-CXP 2.21 CON549 Name INT_Z_ACQUIRED_WP INT_Y_ACQUIRED_WP INT_V_ACQUIRED_WP Reserved INT_ENC_B_WP INT_ENC_A_WP INT_TRIG_WP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT_BM_ERROR_WP INT_AE_LOSS_OF_SYNC_WP INT_PCIE_PKT_DROPPED_WP INT_Z_ACQUIRED_LEGACY_WP Reserved Reserved CYT-2-42 BitFlow, Inc.
  • Page 65 The StreamSync Acquisition Engine CON549 INT_Z_ R/W, CON549[0], Cyton-CXP ACQUIRED_WP INT_Z_ACQUIRED write protect. INT_Y_ R/W, CON549[1], Cyton-CXP ACQUIRED_WP INT_Y_ACQUIRED write protect. INT_V_ R/W, CON549[2], Cyton-CXP ACQUIRED_WP INT_V_ACQUIRED write protect. INT_ENC_B_WP R/W, CON549[4], Cyton-CXP INT_ENC_B write protect. INT_ENC_A_WP R/W, CON549[5], Cyton-CXP INT_ENC_A write protect.
  • Page 66 SF_DIM The Cyton-CXP 2.22 SF_DIM Name SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_HEIGHT SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH SF_WIDTH CYT-2-44 BitFlow, Inc.
  • Page 67 The StreamSync Acquisition Engine SF_DIM SF_HEIGHT R/W, SF_DIM[15..0], Cyton-CXP The height (in lines) of the Synthetic Frame (internally generated synthetic image). SF_WIDTH R/W, SF_DIM[31..16], Cyton-CXP The width of the Synthetic frame. Units are 16 byte chunks. Version A.0 BitFlow, Inc.
  • Page 68 SF_CON The Cyton-CXP 2.23 SF_CON Name SF_RUN_LEVEL SF_RUN_LEVEL SF_STATE SF_STATE SF_MODE SF_MODE Reserved SF_LINE_SCAN SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_INIT_BYTE SF_X_GAP SF_X_GAP SF_X_GAP SF_X_GAP SF_Y_GAP SF_Y_GAP SF_Y_GAP SF_Y_GAP SF_Z_GAP SF_Z_GAP SF_Z_GAP SF_Z_GAP SF_INC_X SF_INC_Y SF_INC_Z Reserved CYT-2-46 BitFlow, Inc.
  • Page 69 The StreamSync Acquisition Engine SF_CON SF_RUN_LEVEL R/W, SF_CON[1..0], Cyton-CXP The register controls the Synthetic Frame generator. SF_RUN_LEVEL Meaning/Command Idle Abort Reserved SF_STATE RO, SF_CON[3..2], Cyton-CXP This register controls if the Synthetic Frame generator is in free-running or triggered mode. SF_STATE...
  • Page 70 SF_CON The Cyton-CXP SF_Y_GAP R/W, SF_CON[23..20], Cyton-CXP The number of lines between frames. SF_Z_GAP R/W, SF_CON[27..24], Cyton-CXP The number of frames between volumes. SF_INC_X R/W, SF_CON[28], Cyton-CXP The amount to increment the grey scale output value every pixel. SF_INC_Y R/W, SF_CON[29], Cyton-CXP The amount to increment the grey scale output value every line.

  • Page 71: The Streamsync Buffer Manager

    BitFlow frame grabbers. The StreamSync system is a start-from-scratch complete redesign of the acquisition and DMA parts of a frame grabber. BitFlow used it years of experience in this area to design a next generation, super efficient capture system.

  • Page 72: The Buffer Manager Details Cyt-3-2

    The Buffer Manager Details The Cyton-CXP 3.2 The Buffer Manager Details The Buffer Manager interacts with a remote, software managed, set of Scatter Gather DMA lists. A single Scatter Gather DMA list is called a QTab. A QTab is made of indi- vidual DMA instructions (descriptors) called Quads.
  • Page 73 3.3 CON485 Register Name FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO FIRST_QUAD_PTR_LO Version A.0 BitFlow, Inc. CYT-3-3...
  • Page 74 CON485 Register The Cyton-CXP FIRST_QUAD_ R/W, CON28[31..0], Cyton-CXP PTR_LO This is the low word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. CYT-3-4 BitFlow, Inc. Version A.0...
  • Page 75 3.4 CON486 Register Name FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI FIRST_QUAD_PTR_HI Version A.0 BitFlow, Inc. CYT-3-5...
  • Page 76 CON486 Register The Cyton-CXP FIRST_QUAD_ R/W, CON29[31..0], Cyton-CXP PTR_HI This is the high word of the 64-bit address of the first DMA scatter-gather instruction in a chain of instructions. CYT-3-6 BitFlow, Inc. Version A.0...

  • Page 77: Buf_Mgr_Con Cyt-3-7

    3.5 BUF_MGR_CON Name BM_RUN_LEVEL BM_RUN_LEVEL BM_RUN_LEVEL BM_RUN_LEVEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CURR_FETCH_SIZE CURR_FETCH_SIZE CURR_FETCH_SIZE CURR_FETCH_SIZE MAX_FETCH_SIZE MAX_FETCH_SIZE MAX_FETCH_SIZE MAX_FETCH_SIZE Version A.0 BitFlow, Inc. CYT-3-7...
  • Page 78 BUF_MGR_CON The Cyton-CXP BM_RUN_LEVEL R/W, BUF_MGR_CON[3..0], Cyton-CXP This is the main control for starting/stopping the Buffer Manager. BM_RUN_LEVEL Meaning 0 (0000b) Idle - The Buffer Manager is not moving data 1 (0001b) Run - The Buffer Manger will start to move data...

  • Page 79: Buf_Mgr_Timeout Cyt-3-9

    3.6 BUF_MGR_TIMEOUT Name QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT QUAD_COMPLETE_TIMEOUT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DISABLE_TIMEOUT Version A.0 BitFlow, Inc. CYT-3-9...
  • Page 80 BUF_MGR_TIMEOUT The Cyton-CXP QUAD_ R/W, BUF_MGR_TIMEOUT[15..0], Cyton-CXP COMPLETE_ TIMEOUT The maximum amount of time to wait for a Quad completion. Units are 4 nanosec- onds. Writable only when BM_STATE is Idle. DISABLE_ R/W, BUF_MGR_TIMEOUT[31], Cyton-CXP TIMEOUT Setting this bit to 1 will disable the Quad completion timeout mechanism. The Buffer Manager will wait an infinite amount of time for a Quad completion to return.

  • Page 81: Board_Config Cyt-3-11

    The StreamSync Buffer Manager BOARD_CONFIG 3.7 BOARD_CONFIG Name Reserved Reserved CPLD_MODE CPLD_MODE CPLD_MODE CPLD_MODE Reserved Reserved Reserved Reserved CPLD_STRAP CPLD_STRAP CPLD_STRAP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-3-11...
  • Page 82 BOARD_CONFIG The Cyton-CXP RO, BOARD_CONFIG[1..0], Cyton-CXP The current value of the on board switch SW1. CPLD_MODE RO, BOARD_CONFIG[7..4], Cyton-CXP The current value of switch S3. This switch controls the firmware bank that the FPGA boots from. CPLD_STRAP RO, BOARD_CONFIG[14..12], Cyton-CXP The current value of the three on board straps.
  • Page 83 3.8 PACKETS_SENT_STATUS Name NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_SENT NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP NUM_PACKETS_DROP Version A.0 BitFlow, Inc. CYT-3-13...

  • Page 84: Packets_Sent_Status Cyt-3-13

    PACKETS_SENT_STATUS The Cyton-CXP NUM_PACKETS_ RO, PACKETS_SENT_STATUS[15..0], Cyton-CXP SENT The register indicates the number of PCIe packets that the Buffer Manager has sent across the PCIe bus. This register rolls over to 0 at 0xffff. NUM_PACKETS_ RO, PACKETS_SENT_STATUS[31..16], Cyton-CXP DROP This register indicates the number of PCIe packets that the buffer Manager was not able to send across the PCIe bus because the PCIe bus was busy.
  • Page 85 3.9 QUADS_USED_STATUS Name NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED NUM_QUADS_USED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-3-15...

  • Page 86: Quads_Used_Status Cyt-3-15

    QUADS_USED_STATUS The Cyton-CXP NUM_QUADS_ RO, QUADS_USED_STATUS[15..0], Cyton-CXP USED This register indicates the number of Quads that have been “consumed” by the Buffer Manager. This register rolls over to 0 at 0xffff. CYT-3-16 BitFlow, Inc. Version A.0...
  • Page 87 3.10 QTABS_USED_STATUS Name NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED NUM_QTABS_USED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-3-17...

  • Page 88: Qtabs_Used_Status Cyt-3-17

    QTABS_USED_STATUS The Cyton-CXP NUM_QTABS_ RO, QTABS_USED_STATUS[15..0], Cyton-CXP USED This register indicates the number of QTabs that have been “consumed” by the Buffer Manager. This register rolls over to 0 at 0xffff. CYT-3-18 BitFlow, Inc. Version A.0...
  • Page 89 3.11 PKT_STAT Name PKT_STATE PKT_STATE Reserved Reserved Reserved Reserved Reserved Reserved NO_QUAD_AVAIL VIDEO_DROPPED QUAD_DROPPED Reserved NEW_FRAME_RESYNC RD_ON_EMPTY WR_ON_FULL Reserved PKT_FLUSH_ENABLE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-3-19...
  • Page 90 PKT_STAT The Cyton-CXP PKT_STATE RO, PKT_STAT[1..0], Cyton-CXP Current state of the DMA engine. PKT_STATE Meaning 0 (00b) PKT_SYNC - Synchronizing DMA descriptors with video 1 (01b) PKT_HDR - Generating PCIe header 2 (10b)~ PKT_DAT - Placing data in PCIe packet...
  • Page 91 The StreamSync Buffer Manager PKT_STAT PKT_FLUSH_ R/W, PKT_STAT[16], Cyton-CXP ENABLE DMA tries to send as large as packets as possible for efficiency. Data is collected in a FIFO until certain size rules are met. However, sometimes no more data will be com- ing (end of frame).

  • Page 92: Quads_Loaded_Status Cyt-3-22

    QUADS_LOADED_STATUS The Cyton-CXP 3.12 QUADS_LOADED_STATUS Name NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED NUM_QUADS_LOADED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-3-22 BitFlow, Inc.
  • Page 93 The StreamSync Buffer Manager QUADS_LOADED_STATUS NUM_QUADS_ RO, QUADS_LOADED_STATUS[15..0], Cyton-CXP LOADED This register indicates the number of Quads that have been loaded by the Buffer Manager. This register will roll over to 0 at 0xffff. Version A.0 BitFlow, Inc. CYT-3-23...

  • Page 94: Qtabs_Loaded_Status Cyt-3-24

    QTABS_LOADED_STATUS The Cyton-CXP 3.13 QTABS_LOADED_STATUS Name NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED NUM_QTABS_LOADED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-3-24 BitFlow, Inc.
  • Page 95 The StreamSync Buffer Manager QTABS_LOADED_STATUS NUM_QTABS_ RO, QTABS_LOADED_STATUS[15..0], Cyton-CXP LOADED This register indicates the number of QTabs that have been loaded by the Buffer Man- ager. This register will roll over to 0 at 0xffff. Version A.0 BitFlow, Inc. CYT-3-25...

  • Page 96: Buf_Mgr_Status Cyt-3-26

    BUF_MGR_STATUS The Cyton-CXP 3.14 BUF_MGR_STATUS Name BM_STATE BM_STATE BM_STATE Reserved CPL_STATUS CPL_STATUS CPL_STATUS Reserved BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED BM_QUADS_CACHED Reserved Reserved Reserved Reserved DST_ADDR_ERROR_LSB NEXT_ADDR_ERROR_LSB SIZE_ERROR_LSB SIZE_ERROR_MSB Reserved Reserved Reserved Reserved CPL_ERROR QUAD_NUM_MISMATCH QUAD_FIFO_OVERFLOW QUAD_TIMEOUT_DETECTED CYT-3-26 BitFlow, Inc.
  • Page 97 The StreamSync Buffer Manager BUF_MGR_STATUS BM_STATE RO, BUF_MGR_STATUS[2..0], Cyton-CXP Returns the current state of the Buffer Manager. BM_STATE Meaning 0 (0000b) Idle - The buffer manager is not current active 1 (0001b) Active - The buffer manager is currently DMAing...
  • Page 98 BUF_MGR_STATUS The Cyton-CXP CPL_ERROR RO, BUF_MGR_STATUS[28], Cyton-CXP Error code received as a result of fetching a Quad. Check CPL_STATUS. QUAD_NUM_ RO, BUF_MGR_STATUS[29], Cyton-CXP MISMATCH Actual quad number does not match expected. QUAD_FIFO_ RO, BUF_MGR_STATUS[30], Cyton-CXP OVERFLOW Quad cache overflowed. QUAD_...

  • Page 99: Pkt_Con Cyt-3-29

    3.15 PKT_CON Name MAX_PAYLOAD_USER MAX_PAYLOAD_USER MAX_PAYLOAD_USER MAX_PAYLOAD_USER MAX_PAYLOAD_PCIE MAX_PAYLOAD_PCIE MAX_PAYLOAD_PCIE MAX_PAYLOAD_PCIE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DISABLE_PKT_FLUSH_TIMER DISABLE_PKT_GEN Version A.0 BitFlow, Inc. CYT-3-29...
  • Page 100 PKT_CON The Cyton-CXP MAX_ RO, PKT_CON[3..0], Cyton-CXP PAYLOAD_USER This is the maximum sized PCIe packet that will be generated by the Buffer Manager. Writes to this register of values higher than MAX_PAYLOAD_PCIE will be ignored. The coding is shown in the following table.

  • Page 101: Timing Sequencer

    4.1 Introduction This section covers the Timing Sequencer (TS) which is currently only available on the Cyton-CXP. The TS is a sophisticated programmable pulse generator. The TS takes the place of the NTG on previous models of BitFlow frame grabbers.
  • Page 102 Introduction The Cyton-CXP For example, let’s say you want a pulse that is example 1.2345678 seconds long. This is done by programing the TS table with three sub pulse as shown below Entry 1: 12 * 100 milliseconds = 1.2 seconds Entry 2: 345 * 100 microseconds = 0.0345 seconds...
  • Page 103 4.2 TS_CONTROL Name TS_RUN_LEVEL TS_RUN_LEVEL TS_RUN_LEVEL Reserved TS_CT0_DEFAULT_STATE TS_CT1_DEFAULT_STATE TS_CT2_DEFAULT_STATE TS_CT3_DEFAULT_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP TS_IDX_JUMP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-4-3...
  • Page 104 TS_CONTROL The Cyton-CXP TS_RUN_LEVEL R/W, TS_CONTROL[2..0], Cyton-CXP These bits control the operation of the TS. These bits are used to start and stop the sequencer. They can also be used to program the table to jump to a new section.
  • Page 105 Timing Sequencer TS_CONTROL This is the entry that the table sill jump to (synchronously) the TS_RUN_LEVEL register is set to Jump. Version A.0 BitFlow, Inc. CYT-4-5...
  • Page 106 TS_TABLE_CONTROL The Cyton-CXP 4.3 TS_TABLE_CONTROL Name TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS TS_IDX_ACCESS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-4-6 BitFlow, Inc.
  • Page 107 Timing Sequencer TS_TABLE_CONTROL TS_IDX_ACCESS R/W, TS_TABLE_CONTROL[7..0], Cyton-CXP Table index to access. Address is setup here. Access is done through read/write to TS_TABLE_ENTRY. Version A.0 BitFlow, Inc. CYT-4-7...
  • Page 108 TS_TABLE_ENTRY The Cyton-CXP 4.4 TS_TABLE_ENTRY Name TS_NEXT TS_NEXT TS_NEXT TS_NEXT TS_NEXT TS_NEXT TS_NEXT TS_NEXT Reserved Reserved TS_RESOLUTION TS_RESOLUTION TS_STATE_CT0 TS_STATE_CT1 TS_STATE_CT2 TS_STATE_CT3 Reserved TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_COUNT TS_CONDITION TS_CONDITION TS_CONDITION TS_TERMINATE TS_END_OF_SEQUENCE CYT-4-8 BitFlow, Inc.
  • Page 109 R/W, TS_TABLE_ENTRY[7..0], Cyton-CXP Index of next pulse. Only follow if TS_TERMINATE = 0. TS_RESOLUTION R/W, TS_TABLE_ENTRY[11..10], Cyton-CXP Then time units of the this pulse. The length of this pulse in the register TS_COUNT. The following table shows the available resolutions.
  • Page 110 TS_TABLE_ENTRY The Cyton-CXP TS_CONDITION R/W, TS_TABLE_ENTRY[29..27], Cyton-CXP This register is used to control the conditions under which this pulse will be output. The following table shows the options for this bitfield. TS_CONDITION Condition when pulse is output 0 (000b) Immediate...
  • Page 111 (decrease the encoder count in a negative direction). This mode is useful in situations where a stage is moving back and forth, and lines need only be acquired if the stage is moving in one direction only. The direction of acquisition is controlled by the QENC_AQ_DIR register. Version A.0 BitFlow, Inc. CYT-5-1...
  • Page 112 Introduction The Cyton-CXP 5.1.3 Interval Mode Often in situations when a stage is moving back and forth, acquisition is only required over a subsection of the total stage range. Interval mode has been designed for these situations. When the board is in interval mode, it only acquires lines when the encoder counter is between a lower limit and an upper limit.
  • Page 113 VFGx_ENCODER_B+ VFGx_ENCODER_B- Note: VFGx - refers to the VFG number that you wish to connect to. For example, if you want to connect a TLL A output to VFG 0, then you would use VFG0_ENCODER_TTL. Version A.0 BitFlow, Inc. CYT-5-3...
  • Page 114 Understanding Stage Movement vs. Quadrature Encoder Modes The Cyton-CXP 5.2 Understanding Stage Movement vs. Quadrature Encoder Modes The quadrature encoder system has many modes that can be used in various combi- nations. These combinations are easier to understand through a few simple illustra- tions.
  • Page 115 Quadrature Encoder Understanding Stage Movement vs. Quadrature Encoder Modes Figure 5-2 shows all of the major quadrature encoder modes. Acquisition Direction Positive Negative Both Not Valid Zoom In Figure 5-2 Quadrature Encoder Modes vs. Acquisition Version A.0 BitFlow, Inc. CYT-5-5...
  • Page 116 CON15 Register The Cyton-CXP 5.3 CON15 Register Name QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_INTRVL_LL QENC_DECODE QENC_AQ_DIR QENC_AQ_DIR QENC_INTRVL_MODE QENC_NO_REAQ QENC_DUAL_PHASE SCAN_STEP_TRIG QENC_RESET CYT-5-6 BitFlow, Inc.
  • Page 117 (or decrease if QENC_AQ_DIR = 1). If there is “jitter” in the encoder signal, often caused by problems with the mechanical systems, it is possible for the board to acquire the same line or lines more than once as the Version A.0 BitFlow, Inc. CYT-5-7...
  • Page 118 CON15 Register The Cyton-CXP mechanical system backs up and moves forward (jitter). This re-acquisition can cause problems as the resulting images will have distortions and will not accurately repre- sent the object in front of the camera. Programming this bit to a 1 turns on the no-reacquisition circuit. This circuit eliminates this problem as each line in the image will only be acquired once, regardless of how much jitter occurs in the quadrature encoder input.
  • Page 119 Quadrature Encoder CON15 Register QENC_RESET WO, CON15[31], Karbon, Neon Poking this bit to a 1 resets the entire quadrate encoder system. Version A.0 BitFlow, Inc. CYT-5-9...
  • Page 120 CON16 Register The Cyton-CXP 5.4 CON16 Register Name QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_INTRVL_UL QENC_REAQ_MODE QENC_REAQ_MODE QENC_RESET_REAQ CYT-5-10 BitFlow, Inc. Version A.0...
  • Page 121 QENC_REAQ_MODE. However, the register QENC_REAQ_MODE can be used to set the board in a mode where the no re-aquisition circuit is reset automatically every pass over the image. Version A.0 BitFlow, Inc. CYT-5-11...
  • Page 122 CON22 Register The Cyton-CXP 5.5 CON22 Register Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP SCAN_STEP CYT-5-12 BitFlow, Inc.
  • Page 123 This bitfield controls the number of encoder pulses that must occur before a trigger is issued to the system. See SCAN_STEP_TRIG for more information. The Scan Step cir- cuit takes into account the interval and re-acquisition functions. Version A.0 BitFlow, Inc. CYT-5-13...
  • Page 124 CON51 Register The Cyton-CXP 5.6 CON51 Register Name QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_COUNT QENC_PHASEA QENC_PHASEB QENC_DIR QENC_INTRVL_IN QENC_NEW_LINES Reserved Reserved Reserved CYT-5-14 BitFlow, Inc.
  • Page 125 System is not inside the interval. Encoder counter is not between QENC_INTRVL_LL and QENC_INTRVL_ UL. Lines are not being acquired. System is inside the interval. Encoder counter is between QENC_INTRVL_LL and QENC_INTRVL_UL. Lines are being acquired. Version A.0 BitFlow, Inc. CYT-5-15...
  • Page 126 CON51 Register The Cyton-CXP QENC_NEW_ RO, CON51[28], Karbon, Neon LINES This bit indicates if the system is at an encoder count that corresponds to a new line. When QENC_NO_REAQ = 1, only lines that have not yet been scanned are acquired.
  • Page 127 Note: The Encoder Divider circuit described in this chapter replaces the previous circuit which could only divide the incoming encoder by an integer value and could not increase the encoder frequncy. Please contact BitFlow if you have been using the previous on-board encoder divider.
  • Page 128 Encoder Divider Details The Cyton-CXP 6.2 Encoder Divider Details 6.2.1 Formula The following formula shows the equation used to scale the encoming encoder rate into the camera’s line rate: ------- Where: Fout = The frequency used to driver the camera or the NTG or the CTabs...
  • Page 129 The board will stay in this state until Fin goes above 1.6 KHz. This is useful when the encoder is being driven by a stage that is travelling back and forth. At both ends of travel when the stage changes directions, the board will not acquire. Version A.0 BitFlow, Inc. CYT-6-3...
  • Page 130 Encoder Divider Control Registers The Cyton-CXP 6.3 Encoder Divider Control Registers The following table summarizes the registers: Table 6-1 Encoder Divider Registers Name Locations Purpose ENC_DIV_M CON6[27..18] This controls the M factor in the Encoder Divider equation (see Section 6.2.1 ENC_DIV_N CON19[18..17]...
  • Page 131 Karbon/Cyton-CXP I/O System Registers Introduction Karbon/Cyton-CXP I/O System Registers Chapter 7 7.1 Introduction The registers documented in this section are used to control the I/O system on the Karbon-CXP and the Cyton-CXP. Version A.0 BitFlow, Inc. CYT-7-1...
  • Page 132 CON60 The Cyton-CXP 7.2 CON60 Name RD_BOX_IN_TTL RD_BOX_IN_TTL RD_BOX_IN_TTL RD_BOX_IN_TTL RD_BOX_IN_TTL RD_BOX_IN_TTL RD_BOX_IN_TTL RD_BOX_IN_TTL RD_BOX_IN_TTL RD_BOX_IN_TTL RD_BOX_IN_TTL Reserved RD_BOX_IN_DIF RD_BOX_IN_DIF RD_BOX_IN_DIF RD_BOX_IN_DIF RD_BOX_IN_DIF RD_BOX_IN_DIF RD_BOX_IN_DIF RD_BOX_IN_DIF RD_BOX_IN_DIF RD_BOX_IN_DIF RD_BOX_IN_DIF Reserved ENINT_CXP INT_CXP Reserved Reserved Reserved SW_TRIG SW_ENCA SW_ENCB CYT-7-2 BitFlow, Inc.
  • Page 133 Karbon/Cyton-CXP I/O System Registers CON60 RD_BOX_IN_TTL RO, CON60[11..0], Karbon-CXP, Cyton-CXP These bits reflect the real-time state of the 12 TTL inputs on the IO Box. RD_BOX_IN_DIF RO, CON60[23..12], Karbon-CXP, Cyton-CXP These bits reflect the real-time state of the 12 differential inputs on the IO Box.
  • Page 134 CON61 The Cyton-CXP 7.3 CON61 Name RD_BOX_IN_OPTO RD_BOX_IN_OPTO RD_BOX_IN_OPTO RD_BOX_IN_OPTO RD_BOX_IN_OPTO RD_BOX_IN_OPTO RD_BOX_IN_OPTO RD_BOX_IN_OPTO RD_BOX_IN_OPTO RD_BOX_IN_OPTO RD_BOX_IN_OPTO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RD_CXP_TRIG_OUT RD_CXP_OUT_IN RD_CXP_OUT_IN RD_CXP_OUT_IN RD_CXP_OUT_IN RD_CXP_OUT_IN RD_CXP_OUT_IN RD_CXP_OUT_IN RD_CXP_OUT_IN CYT-7-4 BitFlow, Inc.
  • Page 135 Karbon/Cyton-CXP I/O System Registers CON61 RD_BOX_IN_ RO, CON61[10..0], Karbon-CXP, Cyton-CXP OPTO These bits reflect the real-time state of the 12 Opto-Isolated inputs on the IO Box. RD_CXP_TRIG_ RO, CON61[23], Karbon-CXP, Cyton-CXP This bit reflects the real-time state of the CXP trigger signal going to the camera.
  • Page 136 CON62 The Cyton-CXP 7.4 CON62 Name RD_TRIG_TTL RD_TRIG_DIF RD_TRIG_VFG0 RD_SCAN_STEP RD_SW_TRIG RD_ENCA_TTL RD_ENCA_DIF RD_ENCA_VFG0 RD_ENCA_SW RD_ENCB_TTL RD_ENCB_DIF RD_ENCB_VFG0 RD_ENCB_SW RD_BUTTON Reserved Reserved RD_CXP_IO_IN RD_CXP_IO_IN RD_CXP_IO_IN RD_CXP_IO_IN RD_CXP_IO_IN RD_CXP_IO_IN RD_CXP_IO_IN RD_CXP_IO_IN RD_CXP_TRIG_IN EN_TRIG EN_ENCA EN_ENCB Reserved RD_ENCB_SELECTED RD_ENCA_SELECTED RD_TRIG_SELECTED CYT-7-6 BitFlow, Inc.
  • Page 137 Karbon/Cyton-CXP I/O System Registers CON62 RD_TRIG_TTL RO, CON62[0], Karbon-CXP, Cyton-CXP This bit reflects the real-time state of the board’s TTL trigger input. RD_TRIG_DIF RO, CON62[1], Karbon-CXP, Cyton-CXP This bit reflects the real-time state of the board’s differential trigger input. RD_TRIG_VFG0 RO, CON62[2], Karbon-CXP, Cyton-CXP This bit reflects the real-time state of VFG0’s selected trigger signal.
  • Page 138 CON62 The Cyton-CXP RD_ENCB_DIF RO, CON62[10], Karbon-CXP, Cyton-CXP This bit reflects the real-time state of the board’s differential encoder B input. RD_ENCB_VFG0 RO, CON62[11], Karbon-CXP, Cyton-CXP This bit reflects the real-time state of VFG0’s selected encoder B signal. RD_ENCB_SW RO, CON62[12], Karbon-CXP, Cyton-CXP This bit reflects the real-time state of the board’s software encoder B.
  • Page 139 Karbon/Cyton-CXP I/O System Registers CON62 RD_ENCA_ RO, CON62[30], Karbon-CXP, Cyton-CXP SELECTED The bit reflects the real-time status of the board’s selected encoder A input. RD_TRIG_ RO, CON62[31], Karbon-CXP, Cyton-CXP SELECTED The bit reflects the real-time status of the board’s selected trigger input.
  • Page 140 CON63 The Cyton-CXP 7.5 CON63 Name SEL_TRIG SEL_TRIG SEL_TRIG SEL_TRIG SEL_TRIG SEL_TRIG SEL_ENCA SEL_ENCA SEL_ENCA SEL_ENCA SEL_ENCA SEL_ENCA SEL_ENCB SEL_ENCB SEL_ENCB SEL_ENCB SEL_ENCB SEL_ENCB SEL_CC1 SEL_CC1 SEL_CC1 SEL_CC1 SEL_CC2 SEL_CC2 SEL_CC2 SEL_CC2 Reserved Reserved SEL_LED SEL_LED SEL_LED SEL_LED CYT-7-10 BitFlow, Inc.
  • Page 141 Karbon/Cyton-CXP I/O System Registers CON63 SEL_TRIG R/W, CON63[5..0], Karbon-CXP, Cyton-CXP Selects the source of the trigger. SEL_TRIG Source 0 (000000b) Forced low 1 (000001b) Forced high 2 (000010b) This VFG’s differential trigger VFGx_TRIGGER=/- 3 (000011b) This VFG’s TTL trigger VFGx_TRIGGER_TTL...
  • Page 142 Reserved 28 to 39 BOX_IN_TTL_0 to BOX_IN_TTL_11 40 to 51 BOX_IN_DIF_0 to BOX_IN_DIF_11 52 to 63 BOS_IN_OPT_0 to BOX_IN_OPT_11 SEL_ENCB R/W, CON63[17..12], Karbon-CXP, Cyton-CXP Selects the source of encoder B. SEL_ENCB Source 0 (000000b) Forced low 1 (000001b) Forced high 2 (000010b) This VFG’s differential encoder B VFGx_ENCB=/-...
  • Page 143 Karbon/Cyton-CXP I/O System Registers CON63 SEL_CC1 R/W, CON63[21..18], Karbon-CXP, Cyton-CXP Selects the source of CC1. SEL_CC1 Source 0 (0000b) Forced low 1 (0001b) Forced high 2 (0010b) CT0 (from CTabs or TS) 3 (0011b) CT1 (from CTabs or TS) 4 (0100b)
  • Page 144 CON63 The Cyton-CXP SEL_LED R/W, CON63[31..28], Karbon-CXP, Cyton-CXP Selects the source of the LED. The LED receives a 1/2 second pulse every time the selected event asserts. SEL_CC1 Source 0 (0000b) Board emits an interrupt to the host 1 (0001b)
  • Page 145 Karbon/Cyton-CXP I/O System Registers CON64 7.6 CON64 Name SEL_CC3 SEL_CC3 SEL_CC3 SEL_CC3 SEL_CC4 SEL_CC4 SEL_CC4 SEL_CC4 SEL_BOX_OUT_TTL SEL_BOX_OUT_DIF SEL_BOX_OUT_OPTO Reserved Reserved TRIGPOL ENCA_POL ENCB_POL GPOUT0 GPOUT1 GPOUT2 GPOUT3 GPOUT4 GPOUT5 GPOUT6 GPOUT7 GPOUT8 GPOUT9 GPOUT10 GPOUT11 LED_RED LED_ORANGE LED_GREEN Reserved Version A.0...
  • Page 146 CON64 The Cyton-CXP SEL_CC3 R/W, CON64[3..0], Karbon-CXP, Cyton-CXP Selects the source of CC3. SEL_CC3 Source 0 (0000b) Forced low 1 (0001b) Forced high 2 (0010b) CT0 (from CTabs or TS) 3 (0011b) CT1 (from CTabs or TS) 4 (0100b) CT2 (from CTabs or TS)
  • Page 147 Karbon/Cyton-CXP I/O System Registers CON64 SEL_BOX_OUT_ R/W, CON64[8], Karbon-CXP, Cyton-CXP Selects the source for the IOBOX TTL outputs. SEL_BOX_OUT_TTL Meaning IOBOX TTL outputs are driven GPOUT0 to GPOUT11 IOBOX TTL outputs are driven by VFG0_CC1 to VFG3_CC3 SEL_BOX_OUT_ R/W, CON64[9], Karbon-CXP, Cyton-CXP Selects the source for the IOBOX differential outputs.
  • Page 148 CON64 The Cyton-CXP ENCA_POL R/W, CON64[14], Karbon-CXP, Cyton-CXP Selects the edge of encoder A signal the corresponds to its assertion. ENCA_POL Meaning Encoder A asserted on rising edge Encoder A asserted on falling edge ENCB_POL R/W, CON64[15], Karbon-CXP, Cyton-CXP Selects the edge of encoder B signal the corresponds to its assertion.
  • Page 149 Karbon/Cyton-CXP I/O System Registers CON64 GPOUT6 R/W, CON64[22], Karbon-CXP, Cyton-CXP General purpose output bit 6. GPOUT7 R/W, CON64[23], Karbon-CXP, Cyton-CXP General purpose output bit 7. GPOUT8 R/W, CON64[24], Karbon-CXP, Cyton-CXP General purpose output bit 8. GPOUT9 R/W, CON64[25], Karbon-CXP, Cyton-CXP General purpose output bit 9.
  • Page 150 CON64 The Cyton-CXP CYT-7-20 BitFlow, Inc. Version A.0...
  • Page 151 The Karbon-CXP and the Cyton-CXP both have up to four CXP links. Each link has it’s own SERDES and associated decode circuitry. In addition, each link can be powered separately.
  • Page 152 CON104 The Cyton-CXP 8.2 CON104 Name 0_POCXP_EN_POWER 0_POCXP_EN_24V_REG 0_POCXP_EN_CAM_SENSE 0_POCXP_CAM_IS_POCXP 0_POCXP_SHORT_DETECTED 0_POCXP_OPEN_DETECTED 0_POCXP_OVER_DETECTED 0_POCXP_OVER_LATCH 0_POCXP_UNDER_DETECTED 0_POCXP_UNDER_LATCH 0_POCXP_24V_OK Reserved 0_POCXP_STATE 0_POCXP_OVR_AUTO_RESTART 0_POCXP_SENSE_BYPASS 0_ENABLE_POCXP_SYSTEM 0_POCXP_CURRENT_LATCH 0_POCXP_CURRENT_LATCH 0_POCXP_CURRENT_LATCH 0_POCXP_CURRENT_LATCH 0_POCXP_CURRENT_LATCH 0_POCXP_CURRENT_LATCH 0_POCXP_CURRENT_LATCH 0_POCXP_CURRENT_LATCH 0_POCXP_CURRENT 0_POCXP_CURRENT 0_POCXP_CURRENT 0_POCXP_CURRENT 0_POCXP_CURRENT 0_POCXP_CURRENT 0_POCXP_CURRENT 0_POCXP_CURRENT CYT-8-2 BitFlow, Inc.
  • Page 153 CXP Subsystem Registers CON104 0_POCXP_EN_ RO, CON104[0], Karbon-CXP, Cyton-CXP POWER CXP Power enabled. 0_POCXP_EN_ RO, CON104[1], Karbon-CXP, Cyton-CXP 24V_REG 24V Regulator enabled. 0_POCXP_EN_ RO, CON104[2], Karbon-CXP, Cyton-CXP CAM_SENSE Enable POCXP Sense. 0_POCXP_CAM_ RO, CON104[3], Karbon-CXP, Cyton-CXP IS_POCXP Reserved for future use.
  • Page 154 CON104 The Cyton-CXP 0_POCXP_ RO, CON104[8], Karbon-CXP, Cyton-CXP UNDER_ DETECTED This status bit indicated under current detected. The protection circuit will immedi- ately disable POCXP_EN_POWER and POCXP_EN_24V_REG in this event. The error is also latched in POCXP_UNDER_LATCH. The most likely cause of this is when a pow- ered camera is disconnected.
  • Page 155 CXP Subsystem Registers CON104 0_POCXP_ RO, CON104[31..24], Karbon-CXP, Cyton-CXP CURRENT Real time current indicator. Version A.0 BitFlow, Inc. CYT-8-5...
  • Page 156 CON105 The Cyton-CXP 8.3 CON105 Name 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER 0_POCXP_OVER_TIMER CYT-8-6 BitFlow, Inc.
  • Page 157 CXP Subsystem Registers CON105 0_POCXP_ R/W, CON105[31..0], Karbon-CXP, Cyton-CXP OVER_TIMER This register specifies the time (in 6.4ns units) to wait after both POCXP_EN_POWER and POCXP_EN_24_REG transition from 0 to 1 before enabling the overcurrent detection circuit. It should be set high enough to ignore transients that may occur on initial power.
  • Page 158 CON106 The Cyton-CXP 8.4 CON106 Name 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER 0_POCXP_UNDER_TIMER CYT-8-8 BitFlow, Inc.
  • Page 159 CXP Subsystem Registers CON106 0_POCXP_ R/W, CON106[31..0], Karbon-CXP, Cyton-CXP UNDER_TIMER This register specifies the time (in 6.4ns units) to wait after both POCXP_EN_POWER and POCXP_EN_24_REG transition from 0 to 1 before enabling the under current detection circuit. It should be set high enough to ignore transients that may occur on initial power.
  • Page 160 CON107 The Cyton-CXP 8.5 CON107 Name 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_RCV_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE 0_COM_SEND_FIFO_SIZE CYT-8-10 BitFlow, Inc.
  • Page 161 CXP Subsystem Registers CON107 0_COM_RCV_ RO, CON107[15..0], Karbon-CXP, Cyton-CXP FIFO_SIZE Depth of the control channel receive fifo. It is measured in 32-bit words. 0_COM_SEND_ RO, CON107[31..16], Karbon-CXP, Cyton-CXP FIFO_SIZE Depth of the control channel request fifo. It is measured in 32-bit words.
  • Page 162 CON108 The Cyton-CXP 8.6 CON108 Name 0_COM_SEND_FIFO_CLR 0_COM_SEND_GO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT 0_COM_SEND_FIFO_CNT CYT-8-12 BitFlow, Inc.
  • Page 163 CXP Subsystem Registers CON108 0_COM_SEND_ WO, CON108[0], Karbon-CXP, Cyton-CXP FIFO_CLR Clear the control channel request fifo. 0_COM_SEND_ WO, CON108[1], Karbon-CXP, Cyton-CXP Transmit the packet stored in the request fifo to the uplink channel. This involves an 8b/10b encoding and serialization. It is assumed that the packet was constructed in the fifo by software and is ready for transmission.
  • Page 164 CON109 The Cyton-CXP 8.7 CON109 Name 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA 0_COM_SEND_DATA CYT-8-14 BitFlow, Inc.
  • Page 165 CXP Subsystem Registers CON109 0_COM_SEND_ R/W, CON109[31..0], Karbon-CXP, Cyton-CXP DATA Software constructs an uplink control channel request packet by writing to the tail of this fifo as 32-bit words. Software is responsible for constructing the majority of the CXP packed according to the CXP specification. Hardware will automatically generate the leading start of packet indication (K27.7), the control command indication (0x2),...
  • Page 166 CON110 The Cyton-CXP 8.8 CON110 Name 0_COM_RCV_FIFO_CLR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT 0_COM_RCV_FIFO_CNT CYT-8-16 BitFlow, Inc.
  • Page 167 CXP Subsystem Registers CON110 0_COM_RCV_ WO, CON110[0], Karbon-CXP, Cyton-CXP FIFO_CLR Clear the control channel receive fifo. 0_COM_RCV_ RO, CON110[31..16], Karbon-CXP, Cyton-CXP FIFO_CNT Number of 32-bit words currently in the response fifo. Version A.0 BitFlow, Inc. CYT-8-17...
  • Page 168 CON111 The Cyton-CXP 8.9 CON111 Name 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA 0_COM_RCV_DATA CYT-8-18 BitFlow, Inc.
  • Page 169 CXP Subsystem Registers CON111 0_COM_RCV_ RO, CON111[31..0], Karbon-CXP, Cyton-CXP DATA Read the head of the control channel response fifo. Fifo level can be monitored with COM_RCV_FIFO_CNT. Version A.0 BitFlow, Inc. CYT-8-19...
  • Page 170 CON115 The Cyton-CXP 8.10 CON115 Name 0_LINK_INT_DEST 0_LINK_INT_DEST Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-20 BitFlow, Inc.
  • Page 171 CXP Subsystem Registers CON115 0_LINK_INT_ R/W, CON115[1..0], Karbon-CXP, Cyton-CXP DEST Version A.0 BitFlow, Inc. CYT-8-21...
  • Page 172 CON116 The Cyton-CXP 8.11 CON116 Name 0_UNDER_CURRENT 0_OVER_CURRENT 0_TRIG_ACK_RCVD 0_GPIO_ACK_RCVD 0_CTL_ACK_RCVD 0_GPIO_RCVD 0_TRIG_RCVD 0_CTL_RSP_FIFO_OVF 0_CTL_REQ_FIFO_OVF 0_GPIO_NOMATCH 0_TRIG_NOMATCH 0_IOACK_UNKNOWN_TYPE 0_IOACK_NOMATCH 0_IOACK_UNEXPECTED_INT 0_IOACK_NOMATCH2 0_STRM_PKT_DROP 0_STRM_NOT_ENOUGH_DAT 0_STRM_TOO_MUCH_DAT 0_STRM_BAD_CRC 0_STRM_OVERFLOW 0_STRM_CORNER 0_SERDES_LOST_ALIGN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-22 BitFlow, Inc.

  • Page 173: 0_Trig_Rcvd

    CXP Subsystem Registers CON116 0_UNDER_ R/W, CON116[0], Karbon-CXP, Cyton-CXP CURRENT Undercurrent detected by POCXP controller interrupt. 0_OVER_ R/W, CON116[1], Karbon-CXP, Cyton-CXP CURRENT Overcurrent detected by POCXP controller interrupt. 0_TRIG_ACK_ R/W, CON116[2], Karbon-CXP, Cyton-CXP RCVD Trigger acknowledgement received from device interrupt.
  • Page 174 CON116 The Cyton-CXP 0_TRIG_ R/W, CON116[10], Karbon-CXP, Cyton-CXP NOMATCH Problem decoding a trigger packet from device interrupt. 0_IOACK_ R/W, CON116[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE Problem decoding an IO acknowledgment from device interrupt. 0_IOACK_ R/W, CON116[12], Karbon-CXP, Cyton-CXP NOMATCH Problem decoding an IO acknowledgement from device interrupt.
  • Page 175 CXP Subsystem Registers CON116 0_STRM_ R/W, CON116[19], Karbon-CXP, Cyton-CXP CORNER Not implemented, reserved interrupt. 0_SERDES_ R/W, CON116[21], Karbon-CXP, Cyton-CXP LOST_ALIGN Serdes lost alignment interrupt. Version A.0 BitFlow, Inc. CYT-8-25...

  • Page 176: 0_Gpio_Nomatch

    CON117 The Cyton-CXP 8.12 CON117 Name 0_UNDER_CURRENT_M 0_OVER_CURRENT_M 0_TRIG_ACK_RCVD_M 0_GPIO_ACK_RCVD_M 0_CTL_ACK_RCVD_M 0_GPIO_RCVD_M 0_TRIG_RCVD_M 0_CTL_RSP_FIFO_OVF_M 0_CTL_REQ_FIFO_OVF_M 0_GPIO_NOMATCH_M 0_TRIG_NOMATCH_M 0_IOACK_UNKNOWN_TYPE_M 0_IOACK_NOMATCH_M 0_IOACK_UNEXPECTED_INT_M 0_IOACK_NOMATCH2_M 0_STRM_PKT_DROP_M 0_STRM_NOT_ENOUGH_DAT_M 0_STRM_TOO_MUCH_DAT_M 0_STRM_BAD_CRC_M 0_STRM_OVERFLOW_M 0_STRM_CORNER_M 0_SERDES_LOST_ALIGN_M Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-26 BitFlow, Inc.
  • Page 177 CXP Subsystem Registers CON117 0_UNDER_ R/W, CON117[0], Karbon-CXP, Cyton-CXP CURRENT_M Mask for the 0_UNDER_CURRENT_M interrupt. 0_OVER_ R/W, CON117[1], Karbon-CXP, Cyton-CXP CURRENT_M Mask for the 0_OVER_CURRENT_M interrupt. 0_TRIG_ACK_ R/W, CON117[2], Karbon-CXP, Cyton-CXP RCVD_M Mask for the 0_TRIG_ACK_RCVD_M interrupt. 0_GPIO_ACK_ R/W, CON117[3], Karbon-CXP, Cyton-CXP RCVD_M Mask for the 0_GPIO_ACK_RCVD_M interrupt.
  • Page 178 CON117 The Cyton-CXP 0_TRIG_ R/W, CON117[10], Karbon-CXP, Cyton-CXP NOMATCH_M Mask for the 0_TRIG_NOMATCH_M interrupt. 0_IOACK_ R/W, CON117[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE_M Mask for the 0_IOACK_UNKNOWN_TYPE_M interrupt. 0_IOACK_ R/W, CON117[12], Karbon-CXP, Cyton-CXP NOMATCH_M Mask for the 0_IOACK_NOMATCH_M interrupt. 0_IOACK_ R/W, CON117[13], Karbon-CXP, Cyton-CXP...
  • Page 179 8.13 CON118 Name 0_UNDER_CURRENT_WP 0_OVER_CURRENT_WP 0_TRIG_ACK_RCVD_WP 0_GPIO_ACK_RCVD_WP 0_CTL_ACK_RCVD_WP 0_GPIO_RCVD_WP 0_TRIG_RCVD_WP 0_CTL_RSP_FIFO_OVF_WP 0_CTL_REQ_FIFO_OVF_WP 0_GPIO_NOMATCH_WP 0_TRIG_NOMATCH_WP 0_IOACK_UNKNOWN_TYPE_WP 0_IOACK_NOMATCH_WP 0_IOACK_UNEXPECTED_INT_WP 0_IOACK_NOMATCH2_WP 0_STRM_PKT_DROP_WP 0_STRM_NOT_ENOUGH_DAT_WP 0_STRM_TOO_WPUCH_DAT_WP 0_STRM_BAD_CRC_WP 0_STRM_OVERFLOW_WP 0_STRM_CORNER_WP 0_SERDES_LOST_ALIGN_WP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-29...
  • Page 180 CON118 The Cyton-CXP 0_UNDER_ R/W, CON118[0], Karbon-CXP, Cyton-CXP CURRENT_WP Write mask for the 0_UNDER_CURRENT_WP interrupt. 0_OVER_ R/W, CON118[1], Karbon-CXP, Cyton-CXP CURRENT_WP Write mask for the 0_OVER_CURRENT_WP interrupt. 0_TRIG_ACK_ R/W, CON118[2], Karbon-CXP, Cyton-CXP RCVD_WP Write mask for the 0_TRIG_ACK_RCVD_WP interrupt. 0_GPIO_ACK_...
  • Page 181 CXP Subsystem Registers CON118 0_TRIG_ R/W, CON118[10], Karbon-CXP, Cyton-CXP NOMATCH_WP Write mask for the 0_TRIG_NOMATCH_WP interrupt. 0_IOACK_ R/W, CON118[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE_WP Write mask for the 0_IOACK_UNKNOWN_TYPE_WP interrupt. 0_IOACK_ R/W, CON118[12], Karbon-CXP, Cyton-CXP NOMATCH_WP Write mask for the 0_IOACK_NOMATCH_WP interrupt.
  • Page 182 CON120 The Cyton-CXP 8.14 CON120 Name 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_RCVD_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT 0_PKT_GNT_CNT CYT-8-32 BitFlow, Inc.
  • Page 183 CXP Subsystem Registers CON120 0_PKT_RCVD_ RO, CON120[15..0], Karbon-CXP, Cyton-CXP Number of CXP packets received on this link. The entire register [31:0] is cleared on a write access of any value. 0_PKT_GNT_ RO, CON120[31..16], Karbon-CXP, Cyton-CXP Number of packets forwarded from this link to the Stream Assembler engine. The entire register [31:0] is cleared on a write access of any value.
  • Page 184 CON121 The Cyton-CXP 8.15 CON121 Name 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_PKT_DROP_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT 0_CRC_ERR_CNT CYT-8-34 BitFlow, Inc.
  • Page 185 CXP Subsystem Registers CON121 0_PKT_DROP_ RO CON121[15..0], Karbon-CXP, Cyton-CXP Number of packets dropped due to packet header errors. The entire register [31:0] is cleared on a write access of any value. 0_CRC_ERR_ RO, CON121[31..16], Karbon-CXP, Cyton-CXP Number of packets with crc errors. These packets are not dropped because they most likely have a small data error and the majority of the frame can be recovered.
  • Page 186 CON122 The Cyton-CXP 8.16 CON122 Name 0_CXP_TRIG_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0_CXP_TRIG_ACK_CNT 0_CXP_TRIG_ACK_CNT 0_CXP_TRIG_ACK_CNT 0_CXP_TRIG_ACK_CNT 0_CXP_TRIG_ACK_CNT 0_CXP_TRIG_ACK_CNT 0_CXP_TRIG_ACK_CNT 0_CXP_TRIG_ACK_CNT CYT-8-36 BitFlow, Inc.
  • Page 187 CXP Subsystem Registers CON122 0_CXP_TRIG_ RO, CON122[0], Karbon-CXP, Cyton-CXP STATE Current state of the uplink CXP trigger signal. 0_CXP_TRIG_ RO, CON122[31..24], Karbon-CXP, Cyton-CXP ACK_CNT Number of CXP trigger acknowledgements received. Version A.0 BitFlow, Inc. CYT-8-37...
  • Page 188 CON123 The Cyton-CXP 8.17 CON123 Name 0_CXP_GPIO_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0_CXP_GPIO_ACK_CNT 0_CXP_GPIO_ACK_CNT 0_CXP_GPIO_ACK_CNT 0_CXP_GPIO_ACK_CNT 0_CXP_GPIO_ACK_CNT 0_CXP_GPIO_ACK_CNT 0_CXP_GPIO_ACK_CNT 0_CXP_GPIO_ACK_CNT CYT-8-38 BitFlow, Inc.
  • Page 189 CXP Subsystem Registers CON123 0_CXP_GPIO_ RO, CON123[0], Karbon-CXP, Cyton-CXP STATE Current state up of the uplink CXP GPIO bus. 0_CXP_GPIO_ RO, CON123[31..24], Karbon-CXP, Cyton-CXP ACK_CNT Number of GPIO acknowledgements received. Version A.0 BitFlow, Inc. CYT-8-39...
  • Page 190 CON126 The Cyton-CXP 8.18 CON126 Name 0_LINK_SPEED 0_LINK_SPEED 0_LINK_SPEED 0_LINK_SPEED 0_LINK_SPEED 0_LINK_SPEED 0_LINK_SPEED 0_LINK_SPEED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-40 BitFlow, Inc.
  • Page 191 CXP Subsystem Registers CON126 0_LINK_SPEED RO, CON126[7..0], Karbon-CXP, Cyton-CXP Describe 0_LINK_SPEED Version A.0 BitFlow, Inc. CYT-8-41...
  • Page 192 CON127 The Cyton-CXP 8.19 CON127 Name 0_SERDES_STATE 0_SERDES_STATE 0_SERDES_STATE 0_SERDES_STATE 0_SERDES_STATE 0_SERDES_STATE 0_SERDES_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0_SERDES_ALIGNED 0_SERDERS_SIGNALDETECT CYT-8-42 BitFlow, Inc.
  • Page 193 CXP Subsystem Registers CON127 0_SERDES_ RO, CON127[6..0], Karbon-CXP, Cyton-CXP STATE Describe 0_SERDES_STATE 0_SERDES_ RO, CON127[30], Karbon-CXP, Cyton-CXP ALIGNED Describe 0_SERDES_ALIGNED 0_SERDERS_ RO, CON127[31], Karbon-CXP, Cyton-CXP SIGNALDETECT Describe 0_SERDERS_SIGNALDETECT Version A.0 BitFlow, Inc. CYT-8-43...
  • Page 194 CON128 The Cyton-CXP 8.20 CON128 Name 0_RAW_DATA_MODE 0_REMOVE_IDLES Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-44 BitFlow, Inc.
  • Page 195 CXP Subsystem Registers CON128 0_RAW_DATA_ R/W, CON128[0], Karbon-CXP, Cyton-CXP MODE Enable raw capture mode. This mode captures raw data from the CXP link without any processing. 0_REMOVE_ R/W, CON128[1], Karbon-CXP, Cyton-CXP IDLES Remove CXP idle packets from the raw capture.
  • Page 196 CON131 The Cyton-CXP 8.21 CON131 Name 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE 0_SERDES_ERROR_CODE Reserved CYT-8-46 BitFlow, Inc.
  • Page 197 CXP Subsystem Registers CON131 0_SERDES_ RO, CON131[30..0], Karbon-CXP, Cyton-CXP ERROR_CODE Describe 0_SERDES_ERROR_CODE Version A.0 BitFlow, Inc. CYT-8-47...
  • Page 198 CON136 The Cyton-CXP 8.22 CON136 Name 1_POCXP_EN_POWER 1_POCXP_EN_24V_REG 1_POCXP_EN_CAM_SENSE 1_POCXP_CAM_IS_POCXP 1_POCXP_SHORT_DETECTED 1_POCXP_OPEN_DETECTED 1_POCXP_OVER_DETECTED 1_POCXP_OVER_LATCH 1_POCXP_UNDER_DETECTED 1_POCXP_UNDER_LATCH 1_POCXP_24V_OK Reserved 1_POCXP_STATE 1_POCXP_OVR_AUTO_RESTART 1_POCXP_SENSE_BYPASS 1_ENABLE_POCXP_SYSTEM 1_POCXP_CURRENT_LATCH 1_POCXP_CURRENT_LATCH 1_POCXP_CURRENT_LATCH 1_POCXP_CURRENT_LATCH 1_POCXP_CURRENT_LATCH 1_POCXP_CURRENT_LATCH 1_POCXP_CURRENT_LATCH 1_POCXP_CURRENT_LATCH 1_POCXP_CURRENT 1_POCXP_CURRENT 1_POCXP_CURRENT 1_POCXP_CURRENT 1_POCXP_CURRENT 1_POCXP_CURRENT 1_POCXP_CURRENT 1_POCXP_CURRENT CYT-8-48 BitFlow, Inc.
  • Page 199 CXP Subsystem Registers CON136 1_POCXP_EN_ RO, CON136[0], Karbon-CXP, Cyton-CXP POWER See description of 0_POCXP_EN_POWER 1_POCXP_EN_ RO, CON136[1], Karbon-CXP, Cyton-CXP 24V_REG See description of 0_POCXP_EN_24V_REG 1_POCXP_EN_ RO, CON136[2], Karbon-CXP, Cyton-CXP CAM_SENSE See description of 0_POCXP_EN_CAM_SENSE 1_POCXP_CAM_ RO, CON136[3], Karbon-CXP, Cyton-CXP IS_POCXP...
  • Page 200 CON136 The Cyton-CXP 1_POCXP_24V_ RO, CON136[10], Karbon-CXP, Cyton-CXP See description of 0_POCXP_24V_OK 1_POCXP_ RO, CON136[12], Karbon-CXP, Cyton-CXP STATE See description of 0_POCXP_STATE. 1_POCXP_OVR_ RW, CON136[13], Karbon-CXP, Cyton-CXP AUTO_RESTART See description of 0_POCXP_OVR_AUTO_RESTART. 1_POCXP_ RW, CON136[14], Karbon-CXP, Cyton-CXP SENSE_BYPASS See description of 0_POCXP_SENSE_BYPASS.
  • Page 201 8.23 CON137 Name 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER 1_POCXP_OVER_TIMER Version A.0 BitFlow, Inc. CYT-8-51...
  • Page 202 CON137 The Cyton-CXP 1_POCXP_ R/W, CON137[31..0], Karbon-CXP, Cyton-CXP OVER_TIMER See description of 0_POCXP_OVER_TIMER CYT-8-52 BitFlow, Inc. Version A.0...
  • Page 203 8.24 CON138 Name 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER 1_POCXP_UNDER_TIMER Version A.0 BitFlow, Inc. CYT-8-53...
  • Page 204 CON138 The Cyton-CXP 1_POCXP_ R/W, CON138[31..0], Karbon-CXP, Cyton-CXP UNDER_TIMER See description of 0_POCXP_UNDER_TIMER CYT-8-54 BitFlow, Inc. Version A.0...
  • Page 205 8.25 CON139 Name 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_RCV_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE 1_COM_SEND_FIFO_SIZE Version A.0 BitFlow, Inc. CYT-8-55...
  • Page 206 CON139 The Cyton-CXP 1_COM_RCV_ RO, CON139[15..0], Karbon-CXP, Cyton-CXP FIFO_SIZE See description of 0_COM_RCV_FIFO_SIZE 1_COM_SEND_ RO, CON139[31..16], Karbon-CXP, Cyton-CXP FIFO_SIZE See description of 0_COM_SEND_FIFO_SIZE CYT-8-56 BitFlow, Inc. Version A.0...
  • Page 207 8.26 CON140 Name 1_COM_SEND_FIFO_CLR 1_COM_SEND_GO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT 1_COM_SEND_FIFO_CNT Version A.0 BitFlow, Inc. CYT-8-57...
  • Page 208 CON140 The Cyton-CXP 1_COM_SEND_ WO, CON140[0], Karbon-CXP, Cyton-CXP FIFO_CLR See description of 0_COM_SEND_FIFO_CLR 1_COM_SEND_ WO, CON140[1], Karbon-CXP, Cyton-CXP See description of 0_COM_SEND_GO 1_COM_SEND_ RO, CON140[31..16], Karbon-CXP, Cyton-CXP FIFO_CNT See description of 0_COM_SEND_FIFO_CNT CYT-8-58 BitFlow, Inc. Version A.0...
  • Page 209 8.27 CON141 Name 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA 1_COM_SEND_DATA Version A.0 BitFlow, Inc. CYT-8-59...
  • Page 210 CON141 The Cyton-CXP 1_COM_SEND_ R/W, CON141[31..0], Karbon-CXP, Cyton-CXP DATA See description of 0_COM_SEND_DATA CYT-8-60 BitFlow, Inc. Version A.0...
  • Page 211 8.28 CON142 Name 1_COM_RCV_FIFO_CLR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT 1_COM_RCV_FIFO_CNT Version A.0 BitFlow, Inc. CYT-8-61...
  • Page 212 CON142 The Cyton-CXP 1_COM_RCV_ WO, CON142[0], Karbon-CXP, Cyton-CXP FIFO_CLR See description of 0_COM_RCV_FIFO_CLR 1_COM_RCV_ RO, CON142[31..16], Karbon-CXP, Cyton-CXP FIFO_CNT See description of 0_COM_RCV_FIFO_CNT CYT-8-62 BitFlow, Inc. Version A.0...
  • Page 213 8.29 CON143 Name 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA 1_COM_RCV_DATA Version A.0 BitFlow, Inc. CYT-8-63...
  • Page 214 CON143 The Cyton-CXP 1_COM_RCV_ RO, CON143[31..0], Karbon-CXP, Cyton-CXP DATA See description of 0_COM_RCV_DATA CYT-8-64 BitFlow, Inc. Version A.0...
  • Page 215 8.30 CON147 Name 1_LINK_INT_DEST 1_LINK_INT_DEST Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-65...
  • Page 216 CON147 The Cyton-CXP 1_LINK_INT_ R/W, CON147[1..0], Karbon-CXP, Cyton-CXP DEST See description of 0_LINK_INT_DEST CYT-8-66 BitFlow, Inc. Version A.0...
  • Page 217 8.31 CON148 Name 1_UNDER_CURRENT 1_OVER_CURRENT 1_TRIG_ACK_RCVD 1_GPIO_ACK_RCVD 1_CTL_ACK_RCVD 1_GPIO_RCVD 1_TRIG_RCVD 1_CTL_RSP_FIFO_OVF 1_CTL_REQ_FIFO_OVF 1_GPIO_NOMATCH 1_TRIG_NOMATCH 1_IOACK_UNKNOWN_TYPE 1_IOACK_NOMATCH 1_IOACK_UNEXPECTED_INT 1_IOACK_NOMATCH2 1_STRM_PKT_DROP 1_STRM_NOT_ENOUGH_DAT 1_STRM_TOO_MUCH_DAT 1_STRM_BAD_CRC 1_STRM_OVERFLOW 1_STRM_CORNER 1_SERDES_LOST_ALIGN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-67...
  • Page 218 CON148 The Cyton-CXP 1_UNDER_ R/W, CON148[0], Karbon-CXP, Cyton-CXP CURRENT See description of 0_UNDER_CURRENT 1_OVER_ R/W, CON148[1], Karbon-CXP, Cyton-CXP CURRENT See description of 0_OVER_CURRENT 1_TRIG_ACK_ R/W, CON148[2], Karbon-CXP, Cyton-CXP RCVD See description of 0_TRIG_ACK_RCVD 1_GPIO_ACK_ R/W, CON148[3], Karbon-CXP, Cyton-CXP RCVD See description of 0_GPIO_ACK_RCVD...
  • Page 219 CXP Subsystem Registers CON148 1_TRIG_ R/W, CON148[10], Karbon-CXP, Cyton-CXP NOMATCH See description of 0_TRIG_NOMATCH 1_IOACK_ R/W, CON148[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE See description of 0_IOACK_UNKNOWN_TYPE 1_IOACK_ R/W, CON148[12], Karbon-CXP, Cyton-CXP NOMATCH See description of 0_IOACK_NOMATCH 1_IOACK_ R/W, CON148[13], Karbon-CXP, Cyton-CXP...
  • Page 220 CON149 The Cyton-CXP 8.32 CON149 Name 1_UNDER_CURRENT_M 1_OVER_CURRENT_M 1_TRIG_ACK_RCVD_M 1_GPIO_ACK_RCVD_M 1_CTL_ACK_RCVD_M 1_GPIO_RCVD_M 1_TRIG_RCVD_M 1_CTL_RSP_FIFO_OVF_M 1_CTL_REQ_FIFO_OVF_M 1_GPIO_NOMATCH_M 1_TRIG_NOMATCH_M 1_IOACK_UNKNOWN_TYPE_M 1_IOACK_NOMATCH_M 1_IOACK_UNEXPECTED_INT_M 1_IOACK_NOMATCH2_M 1_STRM_PKT_DROP_M 1_STRM_NOT_ENOUGH_DAT_M 1_STRM_TOO_MUCH_DAT_M 1_STRM_BAD_CRC_M 1_STRM_OVERFLOW_M 1_STRM_CORNER_M 1_SERDES_LOST_ALIGN_M Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-70 BitFlow, Inc.
  • Page 221 CXP Subsystem Registers CON149 1_UNDER_ R/W, CON149[0], Karbon-CXP, Cyton-CXP CURRENT_M See description of 0_UNDER_CURRENT_M 1_OVER_ R/W, CON149[1], Karbon-CXP, Cyton-CXP CURRENT_M See description of 0_OVER_CURRENT_M 1_TRIG_ACK_ R/W, CON149[2], Karbon-CXP, Cyton-CXP RCVD_M See description of 0_TRIG_ACK_RCVD_M 1_GPIO_ACK_ R/W, CON149[3], Karbon-CXP, Cyton-CXP RCVD_M...
  • Page 222 CON149 The Cyton-CXP 1_TRIG_ R/W, CON149[10], Karbon-CXP, Cyton-CXP NOMATCH_M See description of 0_TRIG_NOMATCH_M 1_IOACK_ R/W, CON149[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE_M See description of 0_IOACK_UNKNOWN_TYPE_M 1_IOACK_ R/W, CON149[12], Karbon-CXP, Cyton-CXP NOMATCH_M See description of 0_IOACK_NOMATCH_M 1_IOACK_ R/W, CON149[13], Karbon-CXP, Cyton-CXP UNEXPECTED_...
  • Page 223 8.33 CON150 Name 1_UNDER_CURRENT_WP 1_OVER_CURRENT_WP 1_TRIG_ACK_RCVD_WP 1_GPIO_ACK_RCVD_WP 1_CTL_ACK_RCVD_WP 1_GPIO_RCVD_WP 1_TRIG_RCVD_WP 1_CTL_RSP_FIFO_OVF_WP 1_CTL_REQ_FIFO_OVF_WP 1_GPIO_NOMATCH_WP 1_TRIG_NOMATCH_WP 1_IOACK_UNKNOWN_TYPE_WP 1_IOACK_NOMATCH_WP 1_IOACK_UNEXPECTED_INT_WP 1_IOACK_NOMATCH2_WP 1_STRM_PKT_DROP_WP 1_STRM_NOT_ENOUGH_DAT_WP 1_STRM_TOO_WPUCH_DAT_WP 1_STRM_BAD_CRC_WP 1_STRM_OVERFLOW_WP 1_STRM_CORNER_WP 1_SERDES_LOST_ALIGN_WP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-73...
  • Page 224 CON150 The Cyton-CXP 1_UNDER_ R/W, CON150[0], Karbon-CXP, Cyton-CXP CURRENT_WP See description of 0_UNDER_CURRENT_WP 1_OVER_ R/W, CON150[1], Karbon-CXP, Cyton-CXP CURRENT_WP See description of 0_OVER_CURRENT_WP 1_TRIG_ACK_ R/W, CON150[2], Karbon-CXP, Cyton-CXP RCVD_WP See description of 0_TRIG_ACK_RCVD_WP 1_GPIO_ACK_ R/W, CON150[3], Karbon-CXP, Cyton-CXP RCVD_WP See description of 0_GPIO_ACK_RCVD_WP...
  • Page 225 CXP Subsystem Registers CON150 1_TRIG_ R/W, CON150[10], Karbon-CXP, Cyton-CXP NOMATCH_WP See description of 0_TRIG_NOMATCH_WP 1_IOACK_ R/W, CON150[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE_WP See description of 0_IOACK_UNKNOWN_TYPE_WP 1_IOACK_ R/W, CON150[12], Karbon-CXP, Cyton-CXP NOMATCH_WP See description of 0_IOACK_NOMATCH_WP 1_IOACK_ R/W, CON150[13], Karbon-CXP, Cyton-CXP...
  • Page 226 CON152 The Cyton-CXP 8.34 CON152 Name 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_RCVD_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT 1_PKT_GNT_CNT CYT-8-76 BitFlow, Inc.
  • Page 227 CXP Subsystem Registers CON152 1_PKT_RCVD_ RO, CON152[15..0], Karbon-CXP, Cyton-CXP See description of 0_PKT_RCVD_CNT 1_PKT_GNT_ RO, CON152[31..16], Karbon-CXP, Cyton-CXP See description of 0_PKT_GNT_CNT Version A.0 BitFlow, Inc. CYT-8-77...
  • Page 228 CON153 The Cyton-CXP 8.35 CON153 Name 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_PKT_DROP_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT 1_CRC_ERR_CNT CYT-8-78 BitFlow, Inc.
  • Page 229 CXP Subsystem Registers CON153 1_PKT_DROP_ RO, CON153[15..0], Karbon-CXP, Cyton-CXP See description of 0_PKT_DROP_CNT 1_CRC_ERR_ RO, CON153[31..16], Karbon-CXP, Cyton-CXP See description of 0_CRC_ERR_CNT Version A.0 BitFlow, Inc. CYT-8-79...
  • Page 230 CON154 The Cyton-CXP 8.36 CON154 Name 1_CXP_TRIG_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1_CXP_TRIG_ACK_CNT 1_CXP_TRIG_ACK_CNT 1_CXP_TRIG_ACK_CNT 1_CXP_TRIG_ACK_CNT 1_CXP_TRIG_ACK_CNT 1_CXP_TRIG_ACK_CNT 1_CXP_TRIG_ACK_CNT 1_CXP_TRIG_ACK_CNT CYT-8-80 BitFlow, Inc.
  • Page 231 CXP Subsystem Registers CON154 1_CXP_TRIG_ RO, CON154[0], Karbon-CXP, Cyton-CXP STATE See description of 0_CXP_TRIG_STATE 1_CXP_TRIG_ RO, CON154[31..24], Karbon-CXP, Cyton-CXP ACK_CNT See description of 0_CXP_TRIG_ACK_CNT Version A.0 BitFlow, Inc. CYT-8-81...
  • Page 232 CON155 The Cyton-CXP 8.37 CON155 Name 1_CXP_GPIO_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1_CXP_GPIO_ACK_CNT 1_CXP_GPIO_ACK_CNT 1_CXP_GPIO_ACK_CNT 1_CXP_GPIO_ACK_CNT 1_CXP_GPIO_ACK_CNT 1_CXP_GPIO_ACK_CNT 1_CXP_GPIO_ACK_CNT 1_CXP_GPIO_ACK_CNT CYT-8-82 BitFlow, Inc.
  • Page 233 CXP Subsystem Registers CON155 1_CXP_GPIO_ RO, CON155[0], Karbon-CXP, Cyton-CXP STATE See description of 0_CXP_GPIO_STATE 1_CXP_GPIO_ RO, CON155[31..24], Karbon-CXP, Cyton-CXP ACK_CNT See description of 0_CXP_GPIO_ACK_CNT Version A.0 BitFlow, Inc. CYT-8-83...
  • Page 234 CON158 The Cyton-CXP 8.38 CON158 Name 1_LINK_SPEED 1_LINK_SPEED 1_LINK_SPEED 1_LINK_SPEED 1_LINK_SPEED 1_LINK_SPEED 1_LINK_SPEED 1_LINK_SPEED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-84 BitFlow, Inc.
  • Page 235 CXP Subsystem Registers CON158 1_LINK_SPEED RO, CON158[7..0], Karbon-CXP, Cyton-CXP See description of 0_LINK_SPEED Version A.0 BitFlow, Inc. CYT-8-85...
  • Page 236 CON159 The Cyton-CXP 8.39 CON159 Name 1_SERDES_STATE 1_SERDES_STATE 1_SERDES_STATE 1_SERDES_STATE 1_SERDES_STATE 1_SERDES_STATE 1_SERDES_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1_SERDES_ALIGNED 1_SERDERS_SIGNALDETECT CYT-8-86 BitFlow, Inc.
  • Page 237 CXP Subsystem Registers CON159 1_SERDES_ RO, CON159[6..0], Karbon-CXP, Cyton-CXP STATE See description of 0_SERDES_STATE 1_SERDES_ RO, CON159[30], Karbon-CXP, Cyton-CXP ALIGNED See description of 0_SERDES_ALIGNED 1_SERDERS_ RO, CON159[31], Karbon-CXP, Cyton-CXP SIGNALDETECT See description of 0_SERDERS_SIGNALDETECT Version A.0 BitFlow, Inc. CYT-8-87...
  • Page 238 CON160 The Cyton-CXP 8.40 CON160 Name 1_RAW_DATA_MODE 1_REMOVE_IDLES Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-88 BitFlow, Inc.
  • Page 239 CXP Subsystem Registers CON160 1_RAW_DATA_ R/W, CON160[0], Karbon-CXP, Cyton-CXP MODE See description of 0_RAW_DATA_MODE 1_REMOVE_ R/W, CON160[1], Karbon-CXP, Cyton-CXP IDLES See description of 0_REMOVE_IDLES Version A.0 BitFlow, Inc. CYT-8-89...
  • Page 240 CON163 The Cyton-CXP 8.41 CON163 Name 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE 1_SERDES_ERROR_CODE Reserved CYT-8-90 BitFlow, Inc.
  • Page 241 CXP Subsystem Registers CON163 1_SERDES_ RO, CON163[30..0], Karbon-CXP, Cyton-CXP ERROR_CODE See description of 0_SERDES_ERROR_CODE Version A.0 BitFlow, Inc. CYT-8-91...
  • Page 242 CON168 The Cyton-CXP 8.42 CON168 Name 2_POCXP_EN_POWER 2_POCXP_EN_24V_REG 2_POCXP_EN_CAM_SENSE 2_POCXP_CAM_IS_POCXP 2_POCXP_SHORT_DETECTED 2_POCXP_OPEN_DETECTED 2_POCXP_OVER_DETECTED 2_POCXP_OVER_LATCH 2_POCXP_UNDER_DETECTED 2_POCXP_UNDER_LATCH 2_POCXP_24V_OK Reserved 2_POCXP_STATE 2_POCXP_OVR_AUTO_RESTART 2_POCXP_SENSE_BYPASS 2_ENABLE_POCXP_SYSTEM 2_POCXP_CURRENT_LATCH 2_POCXP_CURRENT_LATCH 2_POCXP_CURRENT_LATCH 2_POCXP_CURRENT_LATCH 2_POCXP_CURRENT_LATCH 2_POCXP_CURRENT_LATCH 2_POCXP_CURRENT_LATCH 2_POCXP_CURRENT_LATCH 2_POCXP_CURRENT 2_POCXP_CURRENT 2_POCXP_CURRENT 2_POCXP_CURRENT 2_POCXP_CURRENT 2_POCXP_CURRENT 2_POCXP_CURRENT 2_POCXP_CURRENT CYT-8-92 BitFlow, Inc.
  • Page 243 CXP Subsystem Registers CON168 2_POCXP_EN_ R/W, CON168[0], Karbon-CXP, Cyton-CXP POWER See description of 0_POCXP_EN_POWER 2_POCXP_EN_ R/W, CON168[1], Karbon-CXP, Cyton-CXP 24V_REG See description of 0_POCXP_EN_24V_REG 2_POCXP_EN_ RO, CON168[2], Karbon-CXP, Cyton-CXP CAM_SENSE See description of 0_POCXP_EN_CAM_SENSE 2_POCXP_CAM_ RO, CON168[3], Karbon-CXP, Cyton-CXP IS_POCXP...
  • Page 244 CON168 The Cyton-CXP 2_POCXP_24V_ RO, CON168[10], Karbon-CXP, Cyton-CXP See description of 0_POCXP_24V_OK 2_POCXP_ RO, CON168[12], Karbon-CXP, Cyton-CXP STATE See description of 0_POCXP_STATE. 2_POCXP_OVR_ RW, CON168[13], Karbon-CXP, Cyton-CXP AUTO_RESTART See description of 0_POCXP_OVR_AUTO_RESTART. 2_POCXP_ RW, CON168[14], Karbon-CXP, Cyton-CXP SENSE_BYPASS See description of 0_POCXP_SENSE_BYPASS.
  • Page 245 8.43 CON169 Name 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER 2_POCXP_OVER_TIMER Version A.0 BitFlow, Inc. CYT-8-95...
  • Page 246 CON169 The Cyton-CXP 2_POCXP_ R/W, CON169[31..0], Karbon-CXP, Cyton-CXP OVER_TIMER See description of 0_POCXP_OVER_TIMER CYT-8-96 BitFlow, Inc. Version A.0...
  • Page 247 8.44 CON170 Name 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER 2_POCXP_UNDER_TIMER Version A.0 BitFlow, Inc. CYT-8-97...
  • Page 248 CON170 The Cyton-CXP 2_POCXP_ R/W, CON170[31..0], Karbon-CXP, Cyton-CXP UNDER_TIMER See description of 0_POCXP_UNDER_TIMER CYT-8-98 BitFlow, Inc. Version A.0...
  • Page 249 8.45 CON171 Name 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_RCV_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE 2_COM_SEND_FIFO_SIZE Version A.0 BitFlow, Inc. CYT-8-99...
  • Page 250 CON171 The Cyton-CXP 2_COM_RCV_ RO, CON171[15..0], Karbon-CXP, Cyton-CXP FIFO_SIZE See description of 0_COM_RCV_FIFO_SIZE 2_COM_SEND_ RO, CON171[31..16], Karbon-CXP, Cyton-CXP FIFO_SIZE See description of 0_COM_SEND_FIFO_SIZE CYT-8-100 BitFlow, Inc. Version A.0...
  • Page 251 8.46 CON172 Name 2_COM_SEND_FIFO_CLR 2_COM_SEND_GO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT 2_COM_SEND_FIFO_CNT Version A.0 BitFlow, Inc. CYT-8-101...
  • Page 252 CON172 The Cyton-CXP 2_COM_SEND_ WO, CON172[0], Karbon-CXP, Cyton-CXP FIFO_CLR See description of 0_COM_SEND_FIFO_CLR 2_COM_SEND_ WO, CON172[1], Karbon-CXP, Cyton-CXP See description of 0_COM_SEND_GO 2_COM_SEND_ RO, CON172[31..16], Karbon-CXP, Cyton-CXP FIFO_CNT See description of 0_COM_SEND_FIFO_CNT CYT-8-102 BitFlow, Inc. Version A.0...
  • Page 253 8.47 CON173 Name 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA 2_COM_SEND_DATA Version A.0 BitFlow, Inc. CYT-8-103...
  • Page 254 CON173 The Cyton-CXP 2_COM_SEND_ R/W, CON173[31..0], Karbon-CXP, Cyton-CXP DATA See description of 0_COM_SEND_DATA CYT-8-104 BitFlow, Inc. Version A.0...
  • Page 255 8.48 CON174 Name 2_COM_RCV_FIFO_CLR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT 2_COM_RCV_FIFO_CNT Version A.0 BitFlow, Inc. CYT-8-105...
  • Page 256 CON174 The Cyton-CXP 2_COM_RCV_ WO, CON174[0], Karbon-CXP, Cyton-CXP FIFO_CLR See description of 0_COM_RCV_FIFO_CLR 2_COM_RCV_ RO, CON174[31..16], Karbon-CXP, Cyton-CXP FIFO_CNT See description of 0_COM_RCV_FIFO_CNT CYT-8-106 BitFlow, Inc. Version A.0...
  • Page 257 8.49 CON175 Name 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA 2_COM_RCV_DATA Version A.0 BitFlow, Inc. CYT-8-107...
  • Page 258 CON175 The Cyton-CXP 2_COM_RCV_ RO, CON175[31..0], Karbon-CXP, Cyton-CXP DATA See description of 0_COM_RCV_DATA CYT-8-108 BitFlow, Inc. Version A.0...
  • Page 259 8.50 CON179 Name 2_LINK_INT_DEST 2_LINK_INT_DEST Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-109...
  • Page 260 CON179 The Cyton-CXP 2_LINK_INT_ R/W, CON179[1..0], Karbon-CXP, Cyton-CXP DEST See description of 0_LINK_INT_DEST CYT-8-110 BitFlow, Inc. Version A.0...
  • Page 261 8.51 CON180 Name 2_UNDER_CURRENT 2_OVER_CURRENT 2_TRIG_ACK_RCVD 2_GPIO_ACK_RCVD 2_CTL_ACK_RCVD 2_GPIO_RCVD 2_TRIG_RCVD 2_CTL_RSP_FIFO_OVF 2_CTL_REQ_FIFO_OVF 2_GPIO_NOMATCH 2_TRIG_NOMATCH 2_IOACK_UNKNOWN_TYPE 2_IOACK_NOMATCH 2_IOACK_UNEXPECTED_INT 2_IOACK_NOMATCH2 2_STRM_PKT_DROP 2_STRM_NOT_ENOUGH_DAT 2_STRM_TOO_MUCH_DAT 2_STRM_BAD_CRC 2_STRM_OVERFLOW 2_STRM_CORNER 2_SERDES_LOST_ALIGN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-111...
  • Page 262 CON180 The Cyton-CXP 2_UNDER_ R/W, CON180[0], Karbon-CXP, Cyton-CXP CURRENT See description of 0_UNDER_CURRENT 2_OVER_ R/W, CON180[1], Karbon-CXP, Cyton-CXP CURRENT See description of 0_OVER_CURRENT 2_TRIG_ACK_ R/W, CON180[2], Karbon-CXP, Cyton-CXP RCVD See description of 0_TRIG_ACK_RCVD 2_GPIO_ACK_ R/W, CON180[3], Karbon-CXP, Cyton-CXP RCVD See description of 0_GPIO_ACK_RCVD...
  • Page 263 CXP Subsystem Registers CON180 2_TRIG_ R/W, CON180[10], Karbon-CXP, Cyton-CXP NOMATCH See description of 0_TRIG_NOMATCH 2_IOACK_ R/W, CON180[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE See description of 0_IOACK_UNKNOWN_TYPE 2_IOACK_ R/W, CON180[12], Karbon-CXP, Cyton-CXP NOMATCH See description of 0_IOACK_NOMATCH 2_IOACK_ R/W, CON180[13], Karbon-CXP, Cyton-CXP...
  • Page 264 CON181 The Cyton-CXP 8.52 CON181 Name 2_UNDER_CURRENT_M 2_OVER_CURRENT_M 2_TRIG_ACK_RCVD_M 2_GPIO_ACK_RCVD_M 2_CTL_ACK_RCVD_M 2_GPIO_RCVD_M 2_TRIG_RCVD_M 2_CTL_RSP_FIFO_OVF_M 2_CTL_REQ_FIFO_OVF_M 2_GPIO_NOMATCH_M 2_TRIG_NOMATCH_M 2_IOACK_UNKNOWN_TYPE_M 2_IOACK_NOMATCH_M 2_IOACK_UNEXPECTED_INT_M 2_IOACK_NOMATCH2_M 2_STRM_PKT_DROP_M 2_STRM_NOT_ENOUGH_DAT_M 2_STRM_TOO_MUCH_DAT_M 2_STRM_BAD_CRC_M 2_STRM_OVERFLOW_M 2_STRM_CORNER_M 2_SERDES_LOST_ALIGN_M Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-114 BitFlow, Inc.
  • Page 265 CXP Subsystem Registers CON181 2_UNDER_ R/W, CON181[0], Karbon-CXP, Cyton-CXP CURRENT_M See description of 0_UNDER_CURRENT_M 2_OVER_ R/W, CON181[1], Karbon-CXP, Cyton-CXP CURRENT_M See description of 0_OVER_CURRENT_M 2_TRIG_ACK_ R/W, CON181[2], Karbon-CXP, Cyton-CXP RCVD_M See description of 0_TRIG_ACK_RCVD_M 2_GPIO_ACK_ R/W, CON181[3], Karbon-CXP, Cyton-CXP RCVD_M...
  • Page 266 CON181 The Cyton-CXP 2_TRIG_ R/W, CON181[10], Karbon-CXP, Cyton-CXP NOMATCH_M See description of 0_TRIG_NOMATCH_M 2_IOACK_ R/W, CON181[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE_M See description of 0_IOACK_UNKNOWN_TYPE_M 2_IOACK_ R/W, CON181[12], Karbon-CXP, Cyton-CXP NOMATCH_M See description of 0_IOACK_NOMATCH_M 2_IOACK_ R/W, CON181[13], Karbon-CXP, Cyton-CXP UNEXPECTED_...
  • Page 267 8.53 CON182 Name 2_UNDER_CURRENT_WP 2_OVER_CURRENT_WP 2_TRIG_ACK_RCVD_WP 2_GPIO_ACK_RCVD_WP 2_CTL_ACK_RCVD_WP 2_GPIO_RCVD_WP 2_TRIG_RCVD_WP 2_CTL_RSP_FIFO_OVF_WP 2_CTL_REQ_FIFO_OVF_WP 2_GPIO_NOMATCH_WP 2_TRIG_NOMATCH_WP 2_IOACK_UNKNOWN_TYPE_WP 2_IOACK_NOMATCH_WP 2_IOACK_UNEXPECTED_INT_WP 2_IOACK_NOMATCH2_WP 2_STRM_PKT_DROP_WP 2_STRM_NOT_ENOUGH_DAT_WP 2_STRM_TOO_WPUCH_DAT_WP 2_STRM_BAD_CRC_WP 2_STRM_OVERFLOW_WP 2_STRM_CORNER_WP 2_SERDES_LOST_ALIGN_WP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-117...
  • Page 268 CON182 The Cyton-CXP 2_UNDER_ R/W, CON182[0], Karbon-CXP, Cyton-CXP CURRENT_WP See description of 0_UNDER_CURRENT_WP 2_OVER_ R/W, CON182[1], Karbon-CXP, Cyton-CXP CURRENT_WP See description of 0_OVER_CURRENT_WP 2_TRIG_ACK_ R/W, CON182[2], Karbon-CXP, Cyton-CXP RCVD_WP See description of 0_TRIG_ACK_RCVD_WP 2_GPIO_ACK_ R/W, CON182[3], Karbon-CXP, Cyton-CXP RCVD_WP See description of 0_GPIO_ACK_RCVD_WP...
  • Page 269 CXP Subsystem Registers CON182 2_TRIG_ R/W, CON182[10], Karbon-CXP, Cyton-CXP NOMATCH_WP See description of 0_TRIG_NOMATCH_WP 2_IOACK_ R/W, CON182[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE_WP See description of 0_IOACK_UNKNOWN_TYPE_WP 2_IOACK_ R/W, CON182[12], Karbon-CXP, Cyton-CXP NOMATCH_WP See description of 0_IOACK_NOMATCH_WP 2_IOACK_ R/W, CON182[13], Karbon-CXP, Cyton-CXP...
  • Page 270 CON184 The Cyton-CXP 8.54 CON184 Name 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_RCVD_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT 2_PKT_GNT_CNT CYT-8-120 BitFlow, Inc.
  • Page 271 CXP Subsystem Registers CON184 2_PKT_RCVD_ RO, CON184[15..0], Karbon-CXP, Cyton-CXP See description of 0_PKT_RCVD_CNT 2_PKT_GNT_ RO, CON184[31..16], Karbon-CXP, Cyton-CXP See description of 0_PKT_GNT_CNT Version A.0 BitFlow, Inc. CYT-8-121...
  • Page 272 CON185 The Cyton-CXP 8.55 CON185 Name 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_PKT_DROP_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT 2_CRC_ERR_CNT CYT-8-122 BitFlow, Inc.
  • Page 273 CXP Subsystem Registers CON185 2_PKT_DROP_ RO, CON185[15..0], Karbon-CXP, Cyton-CXP See description of 0_PKT_DROP_CNT 2_CRC_ERR_ RO, CON185[31..16], Karbon-CXP, Cyton-CXP See description of 0_CRC_ERR_CNT Version A.0 BitFlow, Inc. CYT-8-123...
  • Page 274 CON186 The Cyton-CXP 8.56 CON186 Name 2_CXP_TRIG_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2_CXP_TRIG_ACK_CNT 2_CXP_TRIG_ACK_CNT 2_CXP_TRIG_ACK_CNT 2_CXP_TRIG_ACK_CNT 2_CXP_TRIG_ACK_CNT 2_CXP_TRIG_ACK_CNT 2_CXP_TRIG_ACK_CNT 2_CXP_TRIG_ACK_CNT CYT-8-124 BitFlow, Inc.
  • Page 275 CXP Subsystem Registers CON186 2_CXP_TRIG_ RO, CON186[0], Karbon-CXP, Cyton-CXP STATE See description of 0_CXP_TRIG_STATE 2_CXP_TRIG_ RO, CON186[31..24], Karbon-CXP, Cyton-CXP ACK_CNT See description of 0_CXP_TRIG_ACK_CNT Version A.0 BitFlow, Inc. CYT-8-125...
  • Page 276 CON187 The Cyton-CXP 8.57 CON187 Name 2_CXP_GPIO_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2_CXP_GPIO_ACK_CNT 2_CXP_GPIO_ACK_CNT 2_CXP_GPIO_ACK_CNT 2_CXP_GPIO_ACK_CNT 2_CXP_GPIO_ACK_CNT 2_CXP_GPIO_ACK_CNT 2_CXP_GPIO_ACK_CNT 2_CXP_GPIO_ACK_CNT CYT-8-126 BitFlow, Inc.
  • Page 277 CXP Subsystem Registers CON187 2_CXP_GPIO_ RO, CON187[0], Karbon-CXP, Cyton-CXP STATE See description of 0_CXP_GPIO_STATE 2_CXP_GPIO_ RO, CON187[31..24], Karbon-CXP, Cyton-CXP ACK_CNT See description of 0_CXP_GPIO_ACK_CNT Version A.0 BitFlow, Inc. CYT-8-127...
  • Page 278 CON190 The Cyton-CXP 8.58 CON190 Name 2_LINK_SPEED 2_LINK_SPEED 2_LINK_SPEED 2_LINK_SPEED 2_LINK_SPEED 2_LINK_SPEED 2_LINK_SPEED 2_LINK_SPEED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-128 BitFlow, Inc.
  • Page 279 CXP Subsystem Registers CON190 2_LINK_SPEED RO, CON190[7..0], Karbon-CXP, Cyton-CXP See description of 0_LINK_SPEED Version A.0 BitFlow, Inc. CYT-8-129...
  • Page 280 CON191 The Cyton-CXP 8.59 CON191 Name 2_SERDES_STATE 2_SERDES_STATE 2_SERDES_STATE 2_SERDES_STATE 2_SERDES_STATE 2_SERDES_STATE 2_SERDES_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2_SERDES_ALIGNED 2_SERDERS_SIGNALDETECT CYT-8-130 BitFlow, Inc.
  • Page 281 CXP Subsystem Registers CON191 2_SERDES_ RO, CON191[6..0], Karbon-CXP, Cyton-CXP STATE See description of 0_SERDES_STATE 2_SERDES_ RO, CON191[30], Karbon-CXP, Cyton-CXP ALIGNED See description of 0_SERDES_ALIGNED 2_SERDERS_ RO, CON191[31], Karbon-CXP, Cyton-CXP SIGNALDETECT See description of 0_SERDERS_SIGNALDETECT Version A.0 BitFlow, Inc. CYT-8-131...
  • Page 282 CON192 The Cyton-CXP 8.60 CON192 Name 2_RAW_DATA_MODE 2_REMOVE_IDLES Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-132 BitFlow, Inc.
  • Page 283 CXP Subsystem Registers CON192 2_RAW_DATA_ R/W, CON192[0], Karbon-CXP, Cyton-CXP MODE See description of 0_RAW_DATA_MODE 2_REMOVE_ R/W, CON192[1], Karbon-CXP, Cyton-CXP IDLES See description of 0_REMOVE_IDLES Version A.0 BitFlow, Inc. CYT-8-133...
  • Page 284 CON195 The Cyton-CXP 8.61 CON195 Name 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE 2_SERDES_ERROR_CODE Reserved CYT-8-134 BitFlow, Inc.
  • Page 285 CXP Subsystem Registers CON195 2_SERDES_ RO, CON195[30..0], Karbon-CXP, Cyton-CXP ERROR_CODE See description of 0_SERDES_ERROR_CODE Version A.0 BitFlow, Inc. CYT-8-135...
  • Page 286 CON200 The Cyton-CXP 8.62 CON200 Name 3_POCXP_EN_POWER 3_POCXP_EN_24V_REG 3_POCXP_EN_CAM_SENSE 3_POCXP_CAM_IS_POCXP 3_POCXP_SHORT_DETECTED 3_POCXP_OPEN_DETECTED 3_POCXP_OVER_DETECTED 3_POCXP_OVER_LATCH 3_POCXP_UNDER_DETECTED 3_POCXP_UNDER_LATCH 3_POCXP_24V_OK Reserved 3_POCXP_STATE 3_POCXP_OVR_AUTO_RESTART 3_POCXP_SENSE_BYPASS 3_ENABLE_POCXP_SYSTEM 3_POCXP_CURRENT_LATCH 3_POCXP_CURRENT_LATCH 3_POCXP_CURRENT_LATCH 3_POCXP_CURRENT_LATCH 3_POCXP_CURRENT_LATCH 3_POCXP_CURRENT_LATCH 3_POCXP_CURRENT_LATCH 3_POCXP_CURRENT_LATCH 3_POCXP_CURRENT 3_POCXP_CURRENT 3_POCXP_CURRENT 3_POCXP_CURRENT 3_POCXP_CURRENT 3_POCXP_CURRENT 3_POCXP_CURRENT 3_POCXP_CURRENT CYT-8-136 BitFlow, Inc.
  • Page 287 CXP Subsystem Registers CON200 3_POCXP_EN_ RO, CON200[0], Karbon-CXP, Cyton-CXP POWER See description of 0_POCXP_EN_POWER 3_POCXP_EN_ RO, CON200[1], Karbon-CXP, Cyton-CXP 24V_REG See description of 0_POCXP_EN_24V_REG 3_POCXP_EN_ RO, CON200[2], Karbon-CXP, Cyton-CXP CAM_SENSE See description of 0_POCXP_EN_CAM_SENSE 3_POCXP_CAM_ RO, CON200[3], Karbon-CXP, Cyton-CXP IS_POCXP...
  • Page 288 CON200 The Cyton-CXP 3_POCXP_24V_ RO, CON200[10], Karbon-CXP, Cyton-CXP See description of 0_POCXP_24V_OK 3_POCXP_ RO, CON200[12], Karbon-CXP, Cyton-CXP STATE See description of 0_POCXP_STATE. 3_POCXP_OVR_ RW, CON200[13], Karbon-CXP, Cyton-CXP AUTO_RESTART See description of 0_POCXP_OVR_AUTO_RESTART. 3_POCXP_ RW, CON200[14], Karbon-CXP, Cyton-CXP SENSE_BYPASS See description of 0_POCXP_SENSE_BYPASS.
  • Page 289 8.63 CON201 Name 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER 3_POCXP_OVER_TIMER Version A.0 BitFlow, Inc. CYT-8-139...
  • Page 290 CON201 The Cyton-CXP 3_POCXP_ R/W, CON201[31..0], Karbon-CXP, Cyton-CXP OVER_TIMER See description of 0_POCXP_OVER_TIMER CYT-8-140 BitFlow, Inc. Version A.0...
  • Page 291 8.64 CON202 Name 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER 3_POCXP_UNDER_TIMER Version A.0 BitFlow, Inc. CYT-8-141...
  • Page 292 CON202 The Cyton-CXP 3_POCXP_ R/W, CON202[31..0], Karbon-CXP, Cyton-CXP UNDER_TIMER See description of 0_POCXP_UNDER_TIMER CYT-8-142 BitFlow, Inc. Version A.0...
  • Page 293 8.65 CON203 Name 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_RCV_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE 3_COM_SEND_FIFO_SIZE Version A.0 BitFlow, Inc. CYT-8-143...
  • Page 294 CON203 The Cyton-CXP 3_COM_RCV_ RO, CON203[15..0], Karbon-CXP, Cyton-CXP FIFO_SIZE See description of 0_COM_RCV_FIFO_SIZE 3_COM_SEND_ RO, CON203[31..16], Karbon-CXP, Cyton-CXP FIFO_SIZE See description of 0_COM_SEND_FIFO_SIZE CYT-8-144 BitFlow, Inc. Version A.0...
  • Page 295 8.66 CON204 Name 3_COM_SEND_FIFO_CLR 3_COM_SEND_GO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT 3_COM_SEND_FIFO_CNT Version A.0 BitFlow, Inc. CYT-8-145...
  • Page 296 CON204 The Cyton-CXP 3_COM_SEND_ WO, CON204[0], Karbon-CXP, Cyton-CXP FIFO_CLR See description of 0_COM_SEND_FIFO_CLR 3_COM_SEND_ WO, CON204[1], Karbon-CXP, Cyton-CXP See description of 0_COM_SEND_GO 3_COM_SEND_ RO, CON204[31..16], Karbon-CXP, Cyton-CXP FIFO_CNT See description of 0_COM_SEND_FIFO_CNT CYT-8-146 BitFlow, Inc. Version A.0...
  • Page 297 8.67 CON205 Name 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA 3_COM_SEND_DATA Version A.0 BitFlow, Inc. CYT-8-147...
  • Page 298 CON205 The Cyton-CXP 3_COM_SEND_ R/W, CON205[31..0], Karbon-CXP, Cyton-CXP DATA See description of 0_COM_SEND_DATA CYT-8-148 BitFlow, Inc. Version A.0...
  • Page 299 8.68 CON206 Name 3_COM_RCV_FIFO_CLR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT 3_COM_RCV_FIFO_CNT Version A.0 BitFlow, Inc. CYT-8-149...
  • Page 300 CON206 The Cyton-CXP 3_COM_RCV_ WO, CON206[0], Karbon-CXP, Cyton-CXP FIFO_CLR See description of 0_COM_RCV_FIFO_CLR 3_COM_RCV_ RO, CON206[31..16], Karbon-CXP, Cyton-CXP FIFO_CNT See description of 0_COM_RCV_FIFO_CNT CYT-8-150 BitFlow, Inc. Version A.0...
  • Page 301 8.69 CON207 Name 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA 3_COM_RCV_DATA Version A.0 BitFlow, Inc. CYT-8-151...
  • Page 302 CON207 The Cyton-CXP 3_COM_RCV_ RO, CON207[31..0], Karbon-CXP, Cyton-CXP DATA See description of 0_COM_RCV_DATA CYT-8-152 BitFlow, Inc. Version A.0...
  • Page 303 8.70 CON211 Name 3_LINK_INT_DEST 3_LINK_INT_DEST Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-153...
  • Page 304 CON211 The Cyton-CXP 3_LINK_INT_ R/W, CON211[1..0], Karbon-CXP, Cyton-CXP DEST See description of 0_LINK_INT_DEST CYT-8-154 BitFlow, Inc. Version A.0...
  • Page 305 8.71 CON212 Name 3_UNDER_CURRENT 3_OVER_CURRENT 3_TRIG_ACK_RCVD 3_GPIO_ACK_RCVD 3_CTL_ACK_RCVD 3_GPIO_RCVD 3_TRIG_RCVD 3_CTL_RSP_FIFO_OVF 3_CTL_REQ_FIFO_OVF 3_GPIO_NOMATCH 3_TRIG_NOMATCH 3_IOACK_UNKNOWN_TYPE 3_IOACK_NOMATCH 3_IOACK_UNEXPECTED_INT 3_IOACK_NOMATCH2 3_STRM_PKT_DROP 3_STRM_NOT_ENOUGH_DAT 3_STRM_TOO_MUCH_DAT 3_STRM_BAD_CRC 3_STRM_OVERFLOW 3_STRM_CORNER 3_SERDES_LOST_ALIGN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-155...
  • Page 306 CON212 The Cyton-CXP 3_UNDER_ R/W, CON212[0], Karbon-CXP, Cyton-CXP CURRENT See description of 0_UNDER_CURRENT 3_OVER_ R/W, CON212[1], Karbon-CXP, Cyton-CXP CURRENT See description of 0_OVER_CURRENT 3_TRIG_ACK_ R/W, CON212[2], Karbon-CXP, Cyton-CXP RCVD See description of 0_TRIG_ACK_RCVD 3_GPIO_ACK_ R/W, CON212[3], Karbon-CXP, Cyton-CXP RCVD See description of 0_GPIO_ACK_RCVD...
  • Page 307 CXP Subsystem Registers CON212 3_TRIG_ R/W, CON212[10], Karbon-CXP, Cyton-CXP NOMATCH See description of 0_TRIG_NOMATCH 3_IOACK_ R/W, CON212[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE See description of 0_IOACK_UNKNOWN_TYPE 3_IOACK_ R/W, CON212[12], Karbon-CXP, Cyton-CXP NOMATCH See description of 0_IOACK_NOMATCH 3_IOACK_ R/W, CON212[13], Karbon-CXP, Cyton-CXP...
  • Page 308 CON213 The Cyton-CXP 8.72 CON213 Name 3_UNDER_CURRENT_M 3_OVER_CURRENT_M 3_TRIG_ACK_RCVD_M 3_GPIO_ACK_RCVD_M 3_CTL_ACK_RCVD_M 3_GPIO_RCVD_M 3_TRIG_RCVD_M 3_CTL_RSP_FIFO_OVF_M 3_CTL_REQ_FIFO_OVF_M 3_GPIO_NOMATCH_M 3_TRIG_NOMATCH_M 3_IOACK_UNKNOWN_TYPE_M 3_IOACK_NOMATCH_M 3_IOACK_UNEXPECTED_INT_M 3_IOACK_NOMATCH2_M 3_STRM_PKT_DROP_M 3_STRM_NOT_ENOUGH_DAT_M 3_STRM_TOO_MUCH_DAT_M 3_STRM_BAD_CRC_M 3_STRM_OVERFLOW_M 3_STRM_CORNER_M 3_SERDES_LOST_ALIGN_M Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-158 BitFlow, Inc.
  • Page 309 CXP Subsystem Registers CON213 3_UNDER_ R/W, CON213[0], Karbon-CXP, Cyton-CXP CURRENT_M See description of 0_UNDER_CURRENT_M 3_OVER_ R/W, CON213[1], Karbon-CXP, Cyton-CXP CURRENT_M See description of 0_OVER_CURRENT_M 3_TRIG_ACK_ R/W, CON213[2], Karbon-CXP, Cyton-CXP RCVD_M See description of 0_TRIG_ACK_RCVD_M 3_GPIO_ACK_ R/W, CON213[3], Karbon-CXP, Cyton-CXP RCVD_M...
  • Page 310 CON213 The Cyton-CXP 3_TRIG_ R/W, CON213[10], Karbon-CXP, Cyton-CXP NOMATCH_M See description of 0_TRIG_NOMATCH_M 3_IOACK_ R/W, CON213[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE_M See description of 0_IOACK_UNKNOWN_TYPE_M 3_IOACK_ R/W, CON213[12], Karbon-CXP, Cyton-CXP NOMATCH_M See description of 0_IOACK_NOMATCH_M 3_IOACK_ R/W, CON213[13], Karbon-CXP, Cyton-CXP UNEXPECTED_...
  • Page 311 8.73 CON214 Name 3_UNDER_CURRENT_WP 3_OVER_CURRENT_WP 3_TRIG_ACK_RCVD_WP 3_GPIO_ACK_RCVD_WP 3_CTL_ACK_RCVD_WP 3_GPIO_RCVD_WP 3_TRIG_RCVD_WP 3_CTL_RSP_FIFO_OVF_WP 3_CTL_REQ_FIFO_OVF_WP 3_GPIO_NOMATCH_WP 3_TRIG_NOMATCH_WP 3_IOACK_UNKNOWN_TYPE_WP 3_IOACK_NOMATCH_WP 3_IOACK_UNEXPECTED_INT_WP 3_IOACK_NOMATCH2_WP 3_STRM_PKT_DROP_WP 3_STRM_NOT_ENOUGH_DAT_WP 3_STRM_TOO_WPUCH_DAT_WP 3_STRM_BAD_CRC_WP 3_STRM_OVERFLOW_WP 3_STRM_CORNER_WP 3_SERDES_LOST_ALIGN_WP Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Version A.0 BitFlow, Inc. CYT-8-161...
  • Page 312 CON214 The Cyton-CXP 3_UNDER_ R/W, CON214[0], Karbon-CXP, Cyton-CXP CURRENT_WP See description of 0_UNDER_CURRENT_WP 3_OVER_ R/W, CON214[1], Karbon-CXP, Cyton-CXP CURRENT_WP See description of 0_OVER_CURRENT_WP 3_TRIG_ACK_ R/W, CON214[2], Karbon-CXP, Cyton-CXP RCVD_WP See description of 0_TRIG_ACK_RCVD_WP 3_GPIO_ACK_ R/W, CON214[3], Karbon-CXP, Cyton-CXP RCVD_WP See description of 0_GPIO_ACK_RCVD_WP...
  • Page 313 CXP Subsystem Registers CON214 3_TRIG_ R/W, CON214[10], Karbon-CXP, Cyton-CXP NOMATCH_WP See description of 0_TRIG_NOMATCH_WP 3_IOACK_ R/W, CON214[11], Karbon-CXP, Cyton-CXP UNKNOWN_ TYPE_WP See description of 0_IOACK_UNKNOWN_TYPE_WP 3_IOACK_ R/W, CON214[12], Karbon-CXP, Cyton-CXP NOMATCH_WP See description of 0_IOACK_NOMATCH_WP 3_IOACK_ R/W, CON214[13], Karbon-CXP, Cyton-CXP...
  • Page 314 CON216 The Cyton-CXP 8.74 CON216 Name 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_RCVD_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT 3_PKT_GNT_CNT CYT-8-164 BitFlow, Inc.
  • Page 315 CXP Subsystem Registers CON216 3_PKT_RCVD_ RO, CON216[15..0], Karbon-CXP, Cyton-CXP See description of 0_PKT_RCVD_CNT 3_PKT_GNT_ RO, CON216[31..16], Karbon-CXP, Cyton-CXP See description of 0_PKT_GNT_CNT Version A.0 BitFlow, Inc. CYT-8-165...
  • Page 316 CON217 The Cyton-CXP 8.75 CON217 Name 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_PKT_DROP_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT 3_CRC_ERR_CNT CYT-8-166 BitFlow, Inc.
  • Page 317 CXP Subsystem Registers CON217 3_PKT_DROP_ RO, CON217[15..0], Karbon-CXP, Cyton-CXP See description of 0_PKT_DROP_CNT 3_CRC_ERR_ RO, CON217[31..16], Karbon-CXP, Cyton-CXP See description of 0_CRC_ERR_CNT Version A.0 BitFlow, Inc. CYT-8-167...
  • Page 318 CON218 The Cyton-CXP 8.76 CON218 Name 3_CXP_TRIG_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3_CXP_TRIG_ACK_CNT 3_CXP_TRIG_ACK_CNT 3_CXP_TRIG_ACK_CNT 3_CXP_TRIG_ACK_CNT 3_CXP_TRIG_ACK_CNT 3_CXP_TRIG_ACK_CNT 3_CXP_TRIG_ACK_CNT 3_CXP_TRIG_ACK_CNT CYT-8-168 BitFlow, Inc.
  • Page 319 CXP Subsystem Registers CON218 3_CXP_TRIG_ RO, CON218[0], Karbon-CXP, Cyton-CXP STATE See description of 0_CXP_TRIG_STATE 3_CXP_TRIG_ RO, CON218[31..24], Karbon-CXP, Cyton-CXP ACK_CNT See description of 0_CXP_TRIG_ACK_CNT Version A.0 BitFlow, Inc. CYT-8-169...
  • Page 320 CON219 The Cyton-CXP 8.77 CON219 Name 3_CXP_GPIO_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3_CXP_GPIO_ACK_CNT 3_CXP_GPIO_ACK_CNT 3_CXP_GPIO_ACK_CNT 3_CXP_GPIO_ACK_CNT 3_CXP_GPIO_ACK_CNT 3_CXP_GPIO_ACK_CNT 3_CXP_GPIO_ACK_CNT 3_CXP_GPIO_ACK_CNT CYT-8-170 BitFlow, Inc.
  • Page 321 CXP Subsystem Registers CON219 3_CXP_GPIO_ RO, CON219[0], Karbon-CXP, Cyton-CXP STATE See description of 0_CXP_GPIO_STATE 3_CXP_GPIO_ RO, CON219[31..24], Karbon-CXP, Cyton-CXP ACK_CNT See description of 0_CXP_GPIO_ACK_CNT Version A.0 BitFlow, Inc. CYT-8-171...
  • Page 322 CON222 The Cyton-CXP 8.78 CON222 Name 3_LINK_SPEED 3_LINK_SPEED 3_LINK_SPEED 3_LINK_SPEED 3_LINK_SPEED 3_LINK_SPEED 3_LINK_SPEED 3_LINK_SPEED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-172 BitFlow, Inc.
  • Page 323 CXP Subsystem Registers CON222 3_LINK_SPEED RO, CON222[7..0], Karbon-CXP, Cyton-CXP See description of 0_LINK_SPEED Version A.0 BitFlow, Inc. CYT-8-173...
  • Page 324 CON223 The Cyton-CXP 8.79 CON223 Name 3_SERDES_STATE 3_SERDES_STATE 3_SERDES_STATE 3_SERDES_STATE 3_SERDES_STATE 3_SERDES_STATE 3_SERDES_STATE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 3_SERDES_ALIGNED 3_SERDERS_SIGNALDETECT CYT-8-174 BitFlow, Inc.
  • Page 325 CXP Subsystem Registers CON223 3_SERDES_ RO, CON223[6..0], Karbon-CXP, Cyton-CXP STATE See description of 0_SERDES_STATE 3_SERDES_ RO, CON223[30], Karbon-CXP, Cyton-CXP ALIGNED See description of 0_SERDES_ALIGNED 3_SERDERS_ RO, CON223[31], Karbon-CXP, Cyton-CXP SIGNALDETECT See description of 0_SERDERS_SIGNALDETECT Version A.0 BitFlow, Inc. CYT-8-175...
  • Page 326 CON224 The Cyton-CXP 8.80 CON224 Name 3_RAW_DATA_MODE 3_REMOVE_IDLES Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-176 BitFlow, Inc.
  • Page 327 CXP Subsystem Registers CON224 3_RAW_DATA_ R/W, CON224[0], Karbon-CXP, Cyton-CXP MODE See description of 0_RAW_DATA_MODE 3_REMOVE_ R/W, CON224[1], Karbon-CXP, Cyton-CXP IDLES See description of 0_REMOVE_IDLES Version A.0 BitFlow, Inc. CYT-8-177...
  • Page 328 CON227 The Cyton-CXP 8.81 CON227 Name 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE 3_SERDES_ERROR_CODE Reserved CYT-8-178 BitFlow, Inc.
  • Page 329 CXP Subsystem Registers CON227 3_SERDES_ RO, CON227[30..0], Karbon-CXP, Cyton-CXP ERROR_CODE See description of 0_SERDES_ERROR_CODE Version A.0 BitFlow, Inc. CYT-8-179...
  • Page 330 CON356 The Cyton-CXP 8.82 CON356 Name FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR FW_BUILD_YEAR Reserved FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_DAY FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH FW_BUILD_MONTH CYT-8-180 BitFlow, Inc.
  • Page 331 CXP Subsystem Registers CON356 FW_BUILD_ RO, CON356[15..0], Karbon-CXP, Cyton-CXP YEAR Year that this firmware was compiled in BCD format. Example: 0x2012 is year 2012 FW_BUILD_DAY RO, CON356[23..16], Karbon-CXP, Cyton-CXP Day that this firmware was compiled in BCD format. Example: 0x18 the 18th of the month.
  • Page 332 CON357 The Cyton-CXP 8.83 CON357 Name FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_MIN FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FW_BUILD_HOUR FPGA_ID FPGA_ID FPGA_ID FPGA_ID FPGA_ID FPGA_ID FPGA_ID FPGA_ID FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL FW_CMPTBL CYT-8-182 BitFlow, Inc.
  • Page 333 CXP Subsystem Registers CON357 FW_BUILD_MIN RO, CON357[7..0], Karbon-CXP, Cyton-CXP Minute that this firmware was compiled. Example: 0x35 is 35 minutes past the hour. FW_BUILD_ RO, CON357[15..8], Karbon-CXP, Cyton-CXP HOUR Hour that this firmware was compiled. Example: 0x23 is 11pm (23rd hour).
  • Page 334 CON358 The Cyton-CXP 8.84 CON358 Name PFG_RESET Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-184 BitFlow, Inc.
  • Page 335 CXP Subsystem Registers CON358 PFG_RESET R/W, CON358[0], Karbon-CXP, Cyton-CXP Reset the pfg (Stream assembler). This register does not get cleared automatically. Software must clear it. Version A.0 BitFlow, Inc. CYT-8-185...
  • Page 336 CON360 The Cyton-CXP 8.85 CON360 Name NUM_LINKS_NEEDED NUM_LINKS_NEEDED NUM_LINKS_NEEDED Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-186 BitFlow, Inc.
  • Page 337 CXP Subsystem Registers CON360 NUM_LINKS_ R/W, CON360[2..0], Karbon-CXP, Cyton-CXP NEEDED Number of active CXP links that a Stream assembler will be working with. The LINK_ ORDER register should be configured prior to setting NUM_LINKS to a non-zero value. Version A.0 BitFlow, Inc.
  • Page 338 CON361 The Cyton-CXP 8.86 CON361 Name LINK_0_ORDER LINK_0_ORDER LINK_0_ORDER LINK_0_ORDER LINK_1_ORDER LINK_1_ORDER LINK_1_ORDER LINK_1_ORDER LINK_2_ORDER LINK_2_ORDER LINK_2_ORDER LINK_2_ORDER LINK_3_ORDER LINK_3_ORDER LINK_3_ORDER LINK_3_ORDER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-188 BitFlow, Inc.
  • Page 339 CXP Subsystem Registers CON361 LINK_0_ORDER R/W, CON361[3..0], Karbon-CXP, Cyton-CXP First physical link that the stream decoder will accept packets from. NUM_LINKS regis- ter determines how many of these physical links will be considered in arbitration. LINK_1_ORDER R/W, CON361[7..4], Karbon-CXP, Cyton-CXP Second physical link that the stream decoder will accept packets from.
  • Page 340 CON363 The Cyton-CXP 8.87 CON363 Name CXP_OUT_TABLE_EVEN CXP_OUT_TABLE_EVEN CXP_OUT_TABLE_EVEN CXP_OUT_TABLE_EVEN CXP_OUT_TABLE_ODD CXP_OUT_TABLE_ODD CXP_OUT_TABLE_ODD CXP_OUT_TABLE_ODD CXP_OUT_TABLE_LPC CXP_OUT_TABLE_LPC CXP_OUT_TABLE_LPC CXP_OUT_TABLE_LPC Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CXP_OUT_TABLE_EN CYT-8-190 BitFlow, Inc.
  • Page 341 CXP_OUT_ R/W, CON363[11..8], Karbon-CXP TABLE_LPC Number of lines to send to an odd or even VFG channel before switching. CXP_OUT_ R/W, CON363[31], Karbon-CXP TABLE_EN Enable the forwarding of video data to the DMA engines (VFGs) Version A.0 BitFlow, Inc. CYT-8-191...
  • Page 342 CON372 The Cyton-CXP 8.88 CON372 Name PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT PKT_GNT_CNT NEXT_LINK NEXT_LINK NEXT_LINK DISABLE_PKT_TAG_CHK UNEXP_PKT_TAG_CNT UNEXP_PKT_TAG_CNT UNEXP_PKT_TAG_CNT UNEXP_PKT_TAG_CNT UNEXP_PKT_TAG_CNT UNEXP_PKT_TAG_CNT UNEXP_PKT_TAG_CNT UNEXP_PKT_TAG_CNT Reserved Reserved Reserved ACTIVE CYT-8-192 BitFlow, Inc.
  • Page 343 CXP Subsystem Registers CON372 PKT_GNT_CNT RO, CON372[15..0], Karbon-CXP, Cyton-CXP Total number of packets accepted from all links associated with this stream decoder. The counter wraps and is for debug only. NEXT_LINK RO, CON372[18..16], Karbon-CXP, Cyton-CXP The next link from which a packet is expected.
  • Page 344 CON428 The Cyton-CXP 8.89 CON428 Name FORCE_RESYNC PACK_PIXELS Reserved Reserved STRM_DECODE_STATE STRM_DECODE_STATE STRM_DECODE_STATE Reserved SOF_ERR SOL_ERR IH_ERR SRC_TAG_ERR IS_LINE_SCAN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CYT-8-194 BitFlow, Inc.
  • Page 345 CXP Subsystem Registers CON428 FORCE_RESYNC WO, CON428[0], Cyton-CXP Forces re-sync of CXP engine. PACK_PIXELS WO, CON428[1], Cyton-CXP Denotes that pixels will be DMAed packed. STRM_DECODE_ RO, CON428[6..4], Cyton-CXP STATE Current state CXP stream decode engine. SOF_ERR RO, CON428[8], Cyton-CXP Bad Start Of Frame Packet.
  • Page 346 CON428 The Cyton-CXP CYT-8-196 BitFlow, Inc. Version A.0...
  • Page 347 This chapter describes the electrical interface of the Karbon/Neon/R64. This includes detailed information on the all if the input and output signals. In addition, information is provided on recommend circuits to use when connecting to these signals. Version A.0 BitFlow, Inc. CYT-9-1...
  • Page 348 Trigger The Cyton-CXP 9.2 Trigger 9.2.1 Trigger Input Types There are four trigger inputs. TRIGGER_TTL - Single ended TTL level trigger TRIGGER_DIFF - Differential (LVDS) trigger TRIGGER_OPTO - Optocoupled trigger FEN - The FEN signal on the CL1 connector. The hardware trigger is enabled/disabled by the bit EN_TRIGGER. Only one input at a time is active (the software trigger bit, SW_TRIG, is always active).
  • Page 349 Electrical Interfacing Trigger TRIGGER_OPTO_A TRIGGER_OPTO Opto Coupler SFH6325 7407 TRIGGER_OPTO_K User Circuit Frame Grabber Figure 9-1 Driver Circuit for Opto-Coupled Trigger Version A.0 BitFlow, Inc. CYT-9-3...
  • Page 350 Encoder The Cyton-CXP 9.3 Encoder 9.3.1 Encoder Input Types There are three encoder inputs. ENCODER_TTL - Single ended TTL level encoder ENCODER_DIFF - Differential (LVDS) encoder ENCODER_OPTO - Optocoupled encoder The hardware encoder is enabled/disabled by the bit EN_ENCODER. Only one input at a time is active (the software encoder bit, SW_ENC, is always active).
  • Page 351 Electrical Interfacing Encoder ENCODER_OPTO_A ENCODER_OPTO Opto Coupler SFH6325 7407 ENCODER_OPTO_K User Circuit Frame Grabber Figure 9-2 Driver Circuit for Opto-Coupled Encoder Version A.0 BitFlow, Inc. CYT-9-5...
  • Page 352 General Purpose Inputs (GPIN) The Cyton-CXP 9.4 General Purpose Inputs (GPIN) 9.4.1 Introduction General Purpose Inputs (GPIN) are use to relay the state of an external signal onto the board and ultimately make it available to a software program. In other words, if an external signal connected to a GPIN pin is electrically high, then an associated regis- ter will read back one, if the same signal is low, then the bit will read back zero.
  • Page 353 For example, if you are not using the Encoder B TTL input, you can read its state at any time using the registers RD_ENCB_TTL. This same principle applies to all the all the trigger and encoder inputs (A & B). Version A.0 BitFlow, Inc. CYT-9-7...
  • Page 354 General Purpose Outputs (GPOUT) The Cyton-CXP 9.5 General Purpose Outputs (GPOUT) 9.5.1 Introduction The General Purpose Outputs (GPOUT) are used to control external hardware (e.g. strobes, stages, etc.). Each GPOUT has a pin on the I/O connector. The level on this pin can be controlled either statically via a GPOUT register, or dynamically via one of the on-board signal generators.
  • Page 355 GPOUT0 Differential GPOUT1 GPOUT2 Differential GPOUT3 GPOUT4 GPOUT5 Open collector GPOUT6 Open collector Table 9-3 Karbon-CL2-D/C:4-F GPOUTs vs. VFGs Signal VFG0 VFG1 GPOUT0 Differential Differential GPOUT1 GPOUT2 Open collector Open collector GPOUT3 Differential Not available Version A.0 BitFlow, Inc. CYT-9-9...
  • Page 356 General Purpose Outputs (GPOUT) The Cyton-CXP Table 9-4 Karbon-CL4-D GPOUTs vs. VFGs Signal VFG0 VFG1 VFG2 VFG3 GPOUT0 Differential Differential Differential Open Collector GPOUT1 Open Collector Not available 9.5.6 Karbon-CXP GPOUT Configuration The Karbon-CXP model has a sophisticated I/O subsystem that is described in detail inSection 2.1.
  • Page 357 The user must supply the +5V to this LED and the two systems must have their grounds connected. In this configuration the board and the user’s system must have a common electrical ground. Version A.0 BitFlow, Inc. CYT-9-11...
  • Page 358 General Purpose Outputs (GPOUT) The Cyton-CXP +12V GPOUT_VCC Opto-Coupler 7407 GPOUT_OC GPOUT Frame Grabber User Circuit Figure 9-4 GPOUT Driving Opto-Coupled Circuit using Galvanic Isolation Figure 9-4 shows how the board’s open collector GPOUT can drive an user’s opto- coupled device configured for galvanic isolation between the board and the user. The power to the user’s LED is supplied by the board’s 5V through a 220 Ohm resistor.
  • Page 359 3 (011b) Free running on board signal generator. Controlled by FREE_RUN_RATE and FREE_ RUN_HIGH 4 (100b) Internally generated clock. Frequency set by CFREQ. 5 (101b) GPIN0’s signal level 6 (110b) Forced low 7 (111b) Forced high Version A.0 BitFlow, Inc. CYT-9-13...
  • Page 360 Camera Link Controls (CCs) The Cyton-CXP CYT-9-14 BitFlow, Inc. Version A.0...
  • Page 361 Chapter 10 10.1 Introduction This chapter describes the mechanical characteristics of the Cyton-CXP. This includes description of all of the connectors on the board and pin-outs for these connectors. The mechanical layout of the Cyton-CXP4 board is shown in Figure 10-1.
  • Page 362 The Cyton-CXP Connectors The Cyton-CXP 10.2 The Cyton-CXP Connectors There are eight connectors on the Cyton-CXP4 main board: CTX - CXP high speed uplink connector 1 C2 - CXP connector 2 C1 - CXP connector 1 C3 - CXP connector 3...
  • Page 363 There is one micro switch block, SW3, on the Cyton-CXP with four switches. These used to control the flash bank that the system boots from. Note: Do not change these switches unless instructed by BitFlow support. See Table 10-3 below which shows the switch settings and the corresponding firm- ware bank.
  • Page 364 Switches The Cyton-CXP Table 10-3 Switch S3 Setting SW3.4 SW3.2 SW 3.2 SW 3.1 FW Bank Reserved Reserved Reserved Reserved CYT-10-4 BitFlow, Inc. Version A.0...
  • Page 365 Mechanical LEDs 10.4 LEDs The Cyton-CXP has 14 LEDs. Table 10-4 Describes the function of these LEDS. Note: The meanings of the LEDs where color is shown a “Various” is described in Table 10-5 and Table 10-6 . Table 10-4 LEDs...
  • Page 366 LEDs The Cyton-CXP 10.4.1 CXP Downlink LED Meaning The LEDs D14, D15, D16 and D18 indicate the status of the CXP downlink. The mean- ing of each color and blink mode is described in Table 10-5. Table 10-5 Downlink LED meaning...
  • Page 367 Button 10.5 Button The Cyton-CXP has a general purpose button, SW2, that can be routed to many differ- ent destinations. The purpose of the button is primarily to help debug I/O problems. It can be used as a trigger, encoder, or I/O that is routed off the board. Please see Sec- tion 2.1 for more information on how the button can be routed.
  • Page 368 The Auxilary Power Connector (P4) The Cyton-CXP 10.6 The Auxilary Power Connector (P4) For cameras that require more power than can be provide by the PCIe bus, the Cyton- CXP has a connector, P4, which can take auxiliary power from the PC’s power supply.
  • Page 369 Mechanical The I/O Box Connector (P1) 10.7 The I/O Box Connector (P1) This connector is for a I/O break out box the BitFlow will be offering in the future. Please contact BitFlow for more information. Version A.0 BitFlow, Inc. CYT-10-9...
  • Page 370 The Cyton-CXP 10.8 I/O Connector Pinout for the Cyton-CXP The pin-out for the I/O Connector (P4) for the Cyton-CXP is illustrated in the Table 10- Note: Signal names start with the Virtual Frame Grabber (VFG) that they are routed to.
  • Page 371 Mechanical I/O Connector Pinout for the Cyton-CXP Table 10-8 I/O Connector for the Cyton-CXP Signal Comment VFG3_CC3+ LVDS VFG3_CC3- LVDS VFG0_TRIGGER_TTL VFG0_ENCODERA_TTL VFG0_ENCODERB_TTL VFG1_TRIGGER_TTL VFG1_ENCODERA_TTL VFG1_ENCODERB_TTL VFG2_TRIGGER_TTL VFG2_ENCODERA_TTL VFG2_ENCODERB_TTL VFG3_TRIGGER_TTL VFG3_ENCODERA_TTL VFG3_ENCODERB_TTL Reserved VFG0_CC3_TTL VFG0_CC4_TTL VFG0_CC2_TTL VFG1_CC3_TTL VFG1_CC4_TTL VFG1_CC2_TTL VFG2_CC3_TTL...
  • Page 372 I/O Connector Pinout for the Cyton-CXP The Cyton-CXP CYT-10-12 BitFlow, Inc. Version A.0...
  • Page 373 0_STRM_NOT_ENOUGH_DAT_CM CYT-8-31 0_IOACK_NOMATCH2 CYT-8-24 0_STRM_NOT_ENOUGH_DAT_M CYT-8-28 0_IOACK_NOMATCH2_CM CYT-8-31 0_STRM_OVERFLOW CYT-8-24 0_IOACK_NOMATCH2_M CYT-8-28 0_STRM_OVERFLOW_CM CYT-8-31 0_IOACK_UNEXPECTED_INT CYT-8-24 0_STRM_OVERFLOW_M CYT-8-28 0_IOACK_UNEXPECTED_INT_CM CYT-8-31 0_STRM_PKT_DROP CYT-8-24 0_IOACK_UNEXPECTED_INT_M CYT-8-28 0_STRM_PKT_DROP_CM CYT-8-31 0_IOACK_UNKNOWN_TYPE CYT-8-24 0_STRM_PKT_DROP_M CYT-8-28 0_IOACK_UNKNOWN_TYPE_CM CYT-8-31 0_STRM_TOO_CMUCH_DAT_CM CYT-8-31 0_IOACK_UNKNOWN_TYPE_M CYT-8-28 0_STRM_TOO_MUCH_DAT CYT-8-24 BitFlow, Inc.
  • Page 374 1_STRM_NOT_ENOUGH_DAT_CM CYT-8-75 1_GPIO_NOMATCH_M CYT-8-71 1_STRM_NOT_ENOUGH_DAT_M CYT-8-72 1_GPIO_RCVD CYT-8-68 1_STRM_OVERFLOW CYT-8-69 1_GPIO_RCVD_CM CYT-8-74 1_STRM_OVERFLOW_CM CYT-8-75 1_GPIO_RCVD_M CYT-8-71 1_STRM_OVERFLOW_M CYT-8-72 1_IOACK_NOMATCH CYT-8-69 1_STRM_PKT_DROP CYT-8-69 1_IOACK_NOMATCH_CM CYT-8-75 1_STRM_PKT_DROP_CM CYT-8-75 1_IOACK_NOMATCH_M CYT-8-72 1_STRM_PKT_DROP_M CYT-8-72 1_IOACK_NOMATCH2 CYT-8-69 1_STRM_TOO_CMUCH_DAT_CM CYT-8-75 1_IOACK_NOMATCH2_CM CYT-8-75 1_STRM_TOO_MUCH_DAT CYT-8-69 BitFlow, Inc.
  • Page 375 2_STRM_NOT_ENOUGH_DAT_CM CYT-8-119 2_GPIO_NOMATCH_M CYT-8-115 2_STRM_NOT_ENOUGH_DAT_M CYT-8-116 2_GPIO_RCVD CYT-8-112 2_STRM_OVERFLOW CYT-8-113 2_GPIO_RCVD_CM CYT-8-118 2_STRM_OVERFLOW_CM CYT-8-119 2_GPIO_RCVD_M CYT-8-115 2_STRM_OVERFLOW_M CYT-8-116 2_IOACK_NOMATCH CYT-8-113 2_STRM_PKT_DROP CYT-8-113 2_IOACK_NOMATCH_CM CYT-8-119 2_STRM_PKT_DROP_CM CYT-8-119 2_IOACK_NOMATCH_M CYT-8-116 2_STRM_PKT_DROP_M CYT-8-116 2_IOACK_NOMATCH2 CYT-8-113 2_STRM_TOO_CMUCH_DAT_CM CYT-8-119 2_IOACK_NOMATCH2_CM CYT-8-119 2_STRM_TOO_MUCH_DAT CYT-8-113 BitFlow, Inc.
  • Page 376 3_STRM_NOT_ENOUGH_DAT_CM CYT-8-163 3_GPIO_NOMATCH_M CYT-8-159 3_STRM_NOT_ENOUGH_DAT_M CYT-8-160 3_GPIO_RCVD CYT-8-156 3_STRM_OVERFLOW CYT-8-157 3_GPIO_RCVD_CM CYT-8-162 3_STRM_OVERFLOW_CM CYT-8-163 3_GPIO_RCVD_M CYT-8-159 3_STRM_OVERFLOW_M CYT-8-160 3_IOACK_NOMATCH CYT-8-157 3_STRM_PKT_DROP CYT-8-157 3_IOACK_NOMATCH_CM CYT-8-163 3_STRM_PKT_DROP_CM CYT-8-163 3_IOACK_NOMATCH_M CYT-8-160 3_STRM_PKT_DROP_M CYT-8-160 3_IOACK_NOMATCH2 CYT-8-157 3_STRM_TOO_CMUCH_DAT_CM CYT-8-163 3_IOACK_NOMATCH2_CM CYT-8-163 3_STRM_TOO_MUCH_DAT CYT-8-157 BitFlow, Inc.
  • Page 377 CON175 CYT-8-107 CON104 CYT-8-2 CON179 CYT-8-109 CON105 CYT-8-6 CON180 CYT-8-111 CON106 CYT-8-8 CON181 CYT-8-114 CON107 CYT-8-10 CON182 CYT-8-117 CON108 CYT-8-12 CON184 CYT-8-120 CON109 CYT-8-14 CON185 CYT-8-122 CON110 CYT-8-16 CON186 CYT-8-124 CON111 CYT-8-18 CON187 CYT-8-126 CON115 CYT-8-20 CON190 CYT-8-128 BitFlow, Inc.
  • Page 378 CON61 CYT-7-4 GPOUT1 CYT-7-18 CON62 CYT-7-6 GPOUT10 CYT-7-19 CON63 CYT-7-10 GPOUT11 CYT-7-19 CON64 CYT-7-15 GPOUT2 CYT-7-18 CPL_ERROR CYT-3-28 GPOUT3 CYT-7-18 CPL_STATUS CYT-3-27 GPOUT4 CYT-7-18 CPLD_MODE CYT-3-12 GPOUT5 CYT-7-18 CPLD_STRAP CYT-3-12 GPOUT6 CYT-7-19 CURR_FETCH_SIZE CYT-3-8 GPOUT7 CYT-7-19 CXP_OUT_TABLE_EN CYT-8-191 BitFlow, Inc.
  • Page 379 INT_Z_ACQUIRED_WP CYT-2-43 QENC_INTRVL_IN CYT-5-15 IS_LINE_SCAN CYT-8-195 QENC_INTRVL_LL CYT-5-7 QENC_INTRVL_MODE CYT-5-7 QENC_INTRVL_UL CYT-5-11 QENC_NEW_LINES CYT-5-16 LED_GREEN CYT-7-19 QENC_NO_REAQ CYT-5-7 LED_ORANGE CYT-7-19 QENC_PHASEA CYT-5-15 LED_RED CYT-7-19 QENC_PHASEB CYT-5-15 LINK_0_ORDER CYT-8-189 QENC_REAQ_MODE CYT-5-11 LINK_1_ORDER CYT-8-189 QENC_RESET CYT-5-9 LINK_2_ORDER CYT-8-189 QENC_RESET_REAQ CYT-5-11 BitFlow, Inc.
  • Page 380 Trigger CYT-9-2 TRIGPOL CYT-7-17 TS CYT-4-1 SCAN_STEP CYT-5-13 TS_CONDITION CYT-4-10 SCAN_STEP_TRIG CYT-5-8 TS_CONTROL CYT-4-3 SEL_BOX_OUT_DIF CYT-7-17 TS_COUNT CYT-4-9 SEL_BOX_OUT_OPTO CYT-7-17 TS_CT0_DEFAULT_STATE CYT-4-4 SEL_BOX_OUT_TTL CYT-7-17 TS_CT1_DEFAULT_STATE CYT-4-4 SEL_CC1 CYT-7-13 TS_CT2_DEFAULT_STATE CYT-4-4 SEL_CC2 CYT-7-13 TS_CT3_DEFAULT_STATE CYT-4-4 SEL_CC3 CYT-7-16 TS_END_OF_SEQUENCE CYT-4-10 BitFlow, Inc.
  • Page 381 V_ACQUIRED CYT-2-28 V_SIZE CYT-2-15 V_WIN_DIM CYT-2-14 VFG CYT-1-2 VIDEO_DROPPED CYT-3-20 WO CYT-P-4 WR_ON_FULL CYT-3-20 X_ACQ_COUNT CYT-2-35 X_ACQ_COUNT_CLR_MODE CYT-2-35 X_ACQUIRED CYT-2-34 X_OFFS CYT-2-27 X_SIZE CYT-2-27 X_WIN_DIM CYT-2-26 Y_ACQ_COUNT CYT-2-33 Y_ACQUIRED CYT-2-32 Y_CLOSE CYT-2-22 Y_CLOSE_TRIG_FUNC CYT-2-22 Y_CLOSE_TRIG_SEL CYT-2-22 Y_OFFS CYT-2-25 BitFlow, Inc.
  • Page 382 Index BitFlow, Inc.
  • Page 383 Index BitFlow, Inc.
  • Page 384 Index BitFlow, Inc.
  • Page 385 Index BitFlow, Inc.
  • Page 386 Index BitFlow, Inc.
  • Page 387 Index BitFlow, Inc.
  • Page 388 Index BitFlow, Inc.

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