Creotech FMC masterFIP User Manual

Production test suite

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FMC masterFIP

Production Test Suite

User Manual

Creotech Instruments SA | Jan 2018 | Version 4.0

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Page 1 FMC masterFIP Production Test Suite User Manual Creotech Instruments SA | Jan 2018 | Version 4.0...
Page 2 Revision Table Revision Date Author Comments Update to board version V4: changed log 31/01/2018 Eva Gousiou folder name, ipmi part: EDA-03098-V4. Update to board version V3: removed ADC 08/03/2017 Marek Gumiński tests, modified EXT_SYNC tests. Changes for V2 version of the board (removed 16/11/2016 Evangelia Gousiou EXT_SYNC_TST)
Page 3: Table Of Contents
Table of content Introduction ............................ - 3 - FMC masterFIP Board Functionality ....................- 9 - PTS Functionality Tests ......................... - 10 - Log files retrieval .......................... - 11 - Custom cable preparation ......................- 12 - First Time Setup ..........................- 13 - Testing Procedure .........................
Page 4: Introduction
Printed Circuit Boards (PCB). It is important to note that the FMC masterFIP PTS covers only to the functionality tests of the boards and does not cover any verification or validation tests of the design. This document describes the FMC masterFIP PTS components and its use.
Page 5 1x LEMO – Dsub9 custom cable 1x LEMO – miniDsub9 custom Schematic shown in Figure 9, picture of real component in Figure 6 cable nanoFIPdiag version must match FMC masterFIP under test speed nanoFIPDiag version. http://www.ohwr.org/projects/nanofipdiag/wiki FMC Fine Delay version. USB cable provided USB relay box 1 http://www.ohwr.org/projects/usb-relay-box1/wiki...
Page 6 The following paragraphs provide an overview of the required items. The FMC masterFIP mezzanine board is tested while mounted on a SPEC carrier board, as Figure 2 shows. The SPEC carrier board provides access to the PCIe interface of the computer. The computer hosts the FMC masterFIP PTS software which provides the automated testing environment.
Page 7 The Relay Box (fine delay version) is controlled by PTS software in order to automate cable reconnections. Figure 4: USB relay box 1 The nanoFIPdiag is used to verify the WorldFIP bus communication by answering to WorldFIP question frames. Note that the nanoFIPdiag speed version should match the version of the masterFIP under test. Figure 5 nanoFIPdiag - 6 -...
Page 8 Custom cables are used to connect the FMC masterFIP to the nanoFIPdiag via the USB relay box. Figure 6 Custom cables One standard Lemo00-Lemo00 cable is also required. Any length may be used. - 7 -...
Page 9 In brief, the operator needs to: o mount the FMC masterFIP board onto the SPEC carrier o connect the cables between the FMC masterFIP, the USB relay box and the nanoFIPdiag o run the software o at certain points of the tests an intervention needs to be done by the operator (e.g.: scan the board’s barcode, check the font panel LED);...
Page 10: Fmc Masterfip Board Functionality
Figure 8: Bottom, top and front views of the masterFIP board The FMC masterFIP mezzanine board is tested while mounted on a SPEC carrier board. The SPEC provides FPGA logic, power supplies, memories, clocking resources and interface to the PCIe bus. The mezzanine houses all the WorldFIP specific parts (FielDrive, FieldTR).
Page 11: Pts Functionality Tests
PTS Functionality Tests The PTS consists of a set of six independent tests, each one checking a different part of the FMC masterFIP board. Table 4 gives a short description of each one of them. Note that the same firmware is used for all the tests, loaded at test00.
Page 12: Log Files Retrieval
Log files retrieval Log files with detailed descriptions of the tests are automatically generated and archived in a .zip file called: <timestamp>_zip_run_<run id>_ FmcMasterFip_<serial number>.zip. The log files need to be delivered to CERN after completing the tests for all of the boards. To do so, please follow the instructions below: o Plug the USB memory key in to the computer.
Page 13: Custom Cable Preparation
– coaxial cable (about 30cm)  blue wire – shield of coaxial cable Resistors (used for termination) should be soldered close to the Dsub connectors. Figure 9 Schematic design of custom cables used by FMC MasterFIP PTS . - 12 -...
Page 14: First Time Setup
First Time Setup The following list explains how to setup the FMC masterFIP environment for the first time. 1) Make sure that the computer is switched off. 2) Remove the screws and open the computer cover. Confirm that the USB relay box is mounted on the upper side of the computer cover.
Page 15 8) Connect the monitor, keyboard and mouse to the computer. 9) Start the PC. 10) Install the FMC masterFIP test environment through the following commands. Please note that the test environment may be installed in any path. The installation sequence then makes sure that the top directory is called fmcmasterfip.
Page 16: Testing Procedure
Mount the FMC masterFIP under-test on the SPEC board. Connect the FMC masterFIP with the USB relay box and the nanoFIPdiag using the provided cables, as in Figure 7. Note that the nanoFIPdiag speed version should match the masterFIP speed version.
Page 17 Switch ON the computer.  Verify that the “Pwr” LED on the SPEC board is ON. This will confirm that the SPEC board is properly plugged.  If the LED is OFF there is a problem with the power supply lines. After the computer has finished with the booting procedure: ...
Page 18: Common Causes Of Test Failure
Verify with lsmod that the cp210x driver is mounted in the kernel.  Make sure you are using the Ubuntu version 14.04.00 LTS. SPEC board with FMC masterFIP was not detected  Verify that the SPEC board is well connected to the PCIe port and the Pwr LED is ON.
Page 19 Might be caused by human error or shorting of traces leading to speed indicating resistors Test 01 Test01 verifies soldering of the FMC masterFIP front panel LED’s. The user is asked to visually verify if all LED’s are blinking one after the other. Possible errors: ...
Page 20 Test 02 This test performs SSSB231 FieldDrive (IC14) tests. The following points are tested one-by-one as described below.  FIP communication o The masterFIP sends a request frame asking for the presence of the nanoFIPdiag (ID_DAT(147F)). o The PTS waits for the response RP_DAT and verifies that all the bytes of the frame received by the masterFIP match the expected ones.
Page 21  RST_N line o The RST_N line does not stall the transmission/ reception of data. It resets the TX_ERR and WDG_N lines. Following from the WDG_N test described above, we activate the fd_rst_n_o line and check that the td_wdgn_i goes inactive. Possible errors: ...
Page 22 internal FPGA pulldown. IC1 output should be is Hi- Read "0" from the FPGA No matter voltage forced by EXT_SYN pin forced by USB Relay Box value read by High internal FPGA pulldown. FPGA is constant. IC1 output should be is Hi- OEn line is checked.
Page 23 o IPMI-FRU  vendor: CERN  name: FmcMasterFip  serial: <SERIAL>  part: EDA-03098-V4-<SPEED> o name  FmcMasterFip o speed  number from 0 (31.25k speed version) to 3 (5M speed version) Possible errors:  EEPROM communication, EEPROM content o EEPROM might be broken or badly soldered o Faulty soldering of FMC connector - 22 -...