iC-Haus iC-PVS Manual
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iC-Haus iC-PVS Manual

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iC-PVS
LINEAR/OFF-AXIS
BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR
FEATURES
High-performance Hall sensors with analog output for
•
downstream high-resolution A/D conversion
Fits magnetic scales of 1.0 up to 2.5 mm pole width or gear
•
tooth modules of 0.3 up to 1.5
Absolute position data with battery-buffered period counting up
•
to 56 bits
Adjustable period count per revolution:
•
FlexCount® logic for 1 to 65536 magnetic periods
Backup battery current consumption of only
•
2 µA to 30 µA in typical applications
Internal 6-bit flash interpolation
•
Incremental output (ABZ) with up to 64 increments per
•
magnetic period
Serial I/O interfaces (BiSS, SSI, SPI, and I
•
Tracking speed of up to 75 m/s (1.5 mm poles)
•
or 46 000 rpm (32 pole pairs)
Differential scanning for high immunity to external magnetic
•
stray fields
2
I
C master function for initial boot-up from EEPROM
•
Overspeed, battery, loss-of-magnet and RAM (CRC) monitoring
•
BLOCK DIAGRAM
iC-PVS
SCL
SCL
SCL
SDA
SDA
SDA
SO
SO
SO
SI
SI
SI
CLK
CLK
CLK
NCS
NCS
NCS
PRE
PRE
PRE
Copyright © 2021 iC-Haus
2
C)
Supply Switch
Power-Up
I
C
2
RAM
MultiMaster
Config
or Slave
Serial I/O Interface - Absolute Data
SLO
SLO
MISO
BiSS
ExtSSI
SPI
SLI
MOSI
MA
MA
SCLK
NCS
Hall Control and Select
B
B
B
B
Oscillator
Hall Sensor Line
APPLICATIONS
Freely scalable hollow-shaft
•
absolute multiturn position
sensors
Freely scalable linear absolute
•
position sensors
Ferrous gear wheel or magnetic
•
scale scanning
Configurable magnetic sensing
•
heads
PACKAGES
VBAT
VBAT
VBAT
VDD
VDD
VDD
VBAT Monitor
VDD Monitor
Counter Logic
Serial Interface
Hall Control
+
0
1
1
1
0
-
1
Period Counter
FlexCount
Amplitude
Position
Control
Encode
+
-
DIG
SIN
+
-
Analog Output
GND
GND
GND
Rev A2, Page 1/51
dra_qfn38-1_pack_2, 2.4:1
38-pin QFN
5 mm x 7 mm
RoHS compliant
VDDS
VDDS
VDDS
General
GPIO0
GPIO0
GPIO0
Purpose
GPIO1
GPIO1
GPIO1
I/O
GPIO2
GPIO2
GPIO2
GPIO3
GPIO3
GPIO3
6 bit Parallel
6 bit ABZ
Status
Monitor
NERR
NERR
NERR
NWRN
NWRN
NWRN
PSIN
PSIN
PSIN
+
-
NSIN
NSIN
NSIN
PCOS
PCOS
PCOS
+
-
NCOS
NCOS
NCOS
http://www.ichaus.com

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  • Page 1 MISO Period Counter BiSS ExtSSI MOSI FlexCount Status SCLK Monitor NERR NERR NERR NWRN NWRN NWRN Amplitude Position Hall Control and Select Control Encode PSIN PSIN PSIN NSIN NSIN NSIN PCOS PCOS PCOS NCOS NCOS NCOS Oscillator Hall Sensor Line Analog Output Copyright © 2021 iC-Haus http://www.ichaus.com...
  • Page 2 BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 2/51 DESCRIPTION iC-PVS is a high performance hall sensor used for or waits for the configuration from one of the I/O incremental or absolute position sensing. It generates interfaces. An undervoltage reset zeroes internal reg- analog sine/cosine signals usable as inputs to down- isters.

  • Page 3: Table Of Contents

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 3/51 CONTENTS PACKAGING INFORMATION PCR_ADI : Period Counts per (mech.) Revolution ....PIN CONFIGURATION QFN38 5 x 7 mm² . .
  • Page 4 Get Register Communication Status ..MAG_ERR: Magnet Error ... Multi-slave configurations with iC-PVS ..Error Output NERR ....

  • Page 5: Packaging Information

    Connect bypass capacitor according to Elec. Char. 011. The output must not be further loaded. Do not leave pin open. Connect pin to VDD if iC-PVS is used without a backup power source (e.g. battery, supercap). To improve the heat dissipation connect the backside paddle to an extended copper area connected to GND. Avoid any current flow across the paddle.

  • Page 6: Package Dimensions

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 6/51 PACKAGE DIMENSIONS RECOMMENDED PCB-FOOTPRINT 4.90 3.65 SIDE 0.50 0.30 BOTTOM 3.65 0.10 0.50 0.22 *): Center package vs. center hall sensor array All dimensions given in mm. Tolerances of form and position according to JEDEC MO-220.

  • Page 7: Absolute Maximum Ratings

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 7/51 ABSOLUTE MAXIMUM RATINGS These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item Symbol Parameter Conditions Unit Min. Max.

  • Page 8: Electrical Characteristics

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 8/51 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.
  • Page 9 LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 9/51 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.
  • Page 10 LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 10/51 ELECTRICAL CHARACTERISTICS Operating conditions: VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.

  • Page 11: Operating Requirements Serial I/O Interface: Biss/Ssi Protocol

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 11/51 OPERATING REQUIREMENTS: Serial I/O Interface: BiSS/SSI Protocol Operating conditions: VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.

  • Page 12: Serial I/O Interface: Spi Protocol

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 12/51 OPERATING REQUIREMENTS: Serial I/O Interface: SPI Protocol Operating conditions: VDD = 3.15...5.5 V, VBAT = 3.0...5.0 V, GND = 0 V, Tj = -40...125 °C, fslow calibrated to 34 kHz with IBIAS, unless otherwise stated.

  • Page 13: Configuration Parameters

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 13/51 CONFIGURATION PARAMETERS Register Map ......Page 14 Magnetic Signal Conditioning .

  • Page 14: Register Map: On-Chip Ram (Banks 0X00 - 0X0F, Address 0X00 - 0X3F)

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 14/51 REGISTER MAP: On-Chip RAM (Banks 0x00 - 0x0F, Address 0x00 - 0x3F) OVERVIEW Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
  • Page 15 LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 15/51 OVERVIEW Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 1 (BSEL=0x01): BiSS ID Data B1|0x01 EDS_BANK(7:0) BiSS Profile B1|0x02...

  • Page 16: Direct Access Register (All Banks, Address 0X40 - 0X7F)

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 16/51 DIRECT ACCESS REGISTER (All Banks, Address 0x40 - 0x7F) OVERVIEW Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank selection...

  • Page 17: Basic Operation And Signal Definitions

    BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 17/51 BASIC OPERATION AND SIGNAL DEFINITIONS The iC-PVS uses an array of hall sensors to detect the sine curve (B - Elec. Char. 105) plus the presence of local variation of the magnetic field emerging from a...
  • Page 18 11520°e for one full mechanical rotation of [mm] target displacement 360°m. The absolute FlexCount® feature of iC-PVS can be utilized to interpret the 32 magnetic periods as one mechanical singleturn revolution. Excessive period counts are processed and output as multiturn revolu- tions.

  • Page 19: Device Operating States

    ). This either happens shortly after battery insertion nected to the system via pin VBAT first. A power-on-re- or after a longer shelf life. iC-PVS will now progress set is performed when rising the voltage at VBAT above through the operating states described in Figure 12.

  • Page 20: Device Operating States

    On one of the following reset conditions, a system re- 2. The EEPROM does not contain a valid configura- set/restart is performed. tion and the CRC check fails. In that case iC-PVS • Power-On-Reset (initial power up via pin VBAT) will stay in BOOT_ST, indicated by STUP_ERR = •...
  • Page 21 LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 21/51 Working Description Position Position Status I(VDD) I(VBAT) State Supply Tracking Readout Indication typical typical RESET Security state after Power-On-Reset, 0 mA 0.6 µA Preset or REBOOT command available RESET...

  • Page 22: Memory Organization, Eeprom & Register Protection Level

    < 2.9 V (due to Elec.Char. 405) Configuration and other data can be transferred from Addressing 11 bit address max. and to iC-PVS by register communication via one of Device Address 0x50 (’1010 000’ w/o R/W bit) the available digital interfaces (BiSS, SPI, I C).

  • Page 23: Register Protection Level (Rpl)

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 23/51 EEPROM at once. selecting the bank using BSEL and then executing the command RPL_SET_RO (read-only) or RPL_SET_NA (no-access, no read or write). This setting must then In contrast to configuration data, the EDS and user data be stored in the EEPROM.
  • Page 24 0x040 unused/reserved ro/na Device Config 0x23 0x03F 0x0FF 0x24 0x000 0x100 EDS - USER DATA 0x25 0x03F 0x17F 0x26 0x000 0x180 USER DATA 0x27 0x03F 0x1FF Figure 13: Detailed register assignment with iC-PVS device configuration data at EEPROM address 0x000...

  • Page 25: I/O Interface Operating Modes

    DIO stands for <digital input output>, hence these ports options for position data and control/register communi- can also be used as inputs. DIOMODE = 0x0 is the cation. iC-PVS offers 2 digital I/O interfaces with 4 pins default assignment. Table 7 lists further options. each: DIOMODE(2:0) Addr.

  • Page 26: Absolute Data Format

    (BiSS, Ext SSI or SPI). If iC-PVS is used in conjunction with a high resolution Hence, the parameter listed in this chapter affect the...

  • Page 27: Err_Adi: Transmission Of Error Bit

    By way of example, assume a magnetic code disc with voltage warning. A warning is indicated by transmit- 32 magnetic periods. With PCR_ADI = 0x0019, iC-PVS ting a ’0’ when Status bit 8, BAT_WRN is set in the will make a revolution count every 32 periods. The syn- STATUS(15:8) register at address 0x6D.

  • Page 28: Os_Adi: Code Offset Of Absolute Position

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 28/51 If the sign-of-life counter is enabled (ENSOL = 1), a 6-bit OS_ADI(5:0) Addr. 0x05; bit 5:0 reset: 0x00 count value (1 - 63) is transmitted as specified in Table...

  • Page 29: Period Counter

    The current consumption of the battery monitoring feature can be configured by parameter MON_FRQ (Table 26). The iC-PVS monitors the voltage at pin VBAT to detect a low battery voltage condition. If the supply drops below the error threshold V voltage (Elec.

  • Page 30: Bat_Thr: Battery Monitor Thresholds

    3.10 3.10 3.20 Parameter VON5 defines the typical supply voltage 3.20 3.30 of the device. iC-PVS can operate at 3.3 V and 5.0 V respectively. Please set the parameter to the typical 3.30 3.40 3.40 3.50 supply voltage at VDD according to Table 27. The sup-...

  • Page 31: Magnetic Signal Conditioning

    LOWPOW: Low Power Mode When iC-PVS is powered via VDD the magnetic signal iC-PVS is able to scan magnetic wheels or linear scales acquisition can run in four different power modes. In de- with a pole width of 0.5 mm to 2.5 mm. This corresponds fault mode, the maximum permissible input frequency to a magnetic period (N-S sequence) of 1 to 5 mm.

  • Page 32: Analog Output

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 32/51 When using the magnetic field amplitude monitoring MAG_THR(1:0) Addr. 0x0A; bit 5:4 reset: 00 feature a setting of MAG_THR = 0x01 is practical and Code Ht [kA/m] Bt [mT] usually achieves good results for pole and gear wheel 6.25...

  • Page 33: Agains And Againc: Actual Fine Gain Factor Sine And Cosine Channel (Read Only)

    Elec. Char. 201. To disable the automatic amplitude parameter AGAINS and AGAINC can be used to query (gain) control set ENAC = 0 and reboot iC-PVS. Without the automatically adjusted sine and cosine fine gain reboot the value of GAINF will stay at the last chosen factors.

  • Page 34: Current Consumption In Battery Mode

    = 60 ele. periods per minute. Code [ A] [ A] 160 10 2700 10 The current consumption of the iC-PVS can be config- 40 10 700 10 ured by parameter A_MAX. Besides the current con- 10 10 170 10 sumption, this parameter sets the maximum angular ac- 2.5 10...

  • Page 35: Frequency And Bias Current Adjustment

    0x02 + 10.0 % 0x01 + 5.0 % Calibrating the oscillator frequency is not absolutely 0x00 necessary to ensure iC-PVS operation, however it is 0x0F 4.5 % recommended to conduct the calibration. If left uncal- 0x0E 8.0 % ibrated mainly the values defined in Table 44 and 45 0x0D - 11.5 %...

  • Page 36: Zgate : Z Pulse Gating Scheme

    The BiSS serial proto- tion (SCD) and configuration data transmission. col used by iC-PVS is shown in Figure 16. In BiSS mode, iC-PVS acts as a BiSS slave and must CLK: MA nCDM Timeout...

  • Page 37: Ntoa_Biss : Fixed Or Adaptive Biss Timeout

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 37/51 lute position data format as defined in chapter Absolute Timeout Min. Max. Data Format on page 26. All values are transmitted 1.5 T 1.5 T + 3.0 T tout...

  • Page 38: Extended Ssi Slave Interface

    Note that a stop zero is added between the re- For Extended SSI the iC-PVS can provide a fixed or peated transmissions, requiring an additional SSI clock adaptive timeout depending on the setting of parameter cycle.

  • Page 39: Spi Slave Interface

    Activate Slave in Chain allows connecting multiple SPI slaves to a single SPI master. Refer to section "Multi-Slave configuration with Table 53: SPI Operation Codes iC-PVS" on page 42 for more information. CLK: SCLK MODE 0 CLK: SCLK MODE 3 SI: MOSI...

  • Page 40: Read Register

    0x00. Those first three bytes are also transmit- The position data contains the complete absolute po- ted by iC-PVS on MISO, before sending the requested sition data with optional configured error bit, warning data (DATA1) from the register at address (ADR). As bit and optionally a sign-of-life counter (LC).

  • Page 41: Read Status Register

    LINEAR/OFF-AXIS BATTERY-BUFFERED ABSOLUTE POSITION HALL SENSOR Rev A2, Page 41/51 Commands do require processing time until Read Status Register completed. Successful completion can be de- Opcode Read Status Register (0x9C) directly reads the tected by polling the CMD register. Refer to device status registers at address 0x6C - 0x6E.

  • Page 42: Multi-Slave Configurations With Ic-Pvs

    SPI daisy chain as shown in Figure 29. Table 54: SPI Status byte The MOSI of each iC-PVS is connected to the MISO of the next device in chain. The MISO of each iC-PVS is connected to the MOSI of the next device. As only a...

  • Page 43: Activate Slave In Chain

    Register communication with iC-PVS is only possible if RACTIVE = 1. Otherwise register com- munication attempts are ignored. Sensor data (position data) can only be acquired from iC-PVS if PACTIVE = MISO 1. Otherwise opcode Read Position (0xA6) is ignored.

  • Page 44: I 2 C Eeprom Interface

    0xA0 or "0b 1010 000", which is the standard I C EEPROM address. By default, the EEPROM is used to store the iC-PVS Notes: If several devices share one common configuration according to the register map on Page 14 EEPROM (e.g.

  • Page 45: C Slave Interface

    Additionally to the I C master interface described in Note: For a consistent position information it is neces- the previous chapter, iC-PVS will always act as an I2C sary to stop the register updating before read-out. The slave when V(VDD) > V...

  • Page 46: Commands

    Restart the device using internal config. data (from Sleep or Standby). Status bits are preserved. 0x12 SLEEP Complete halt of iC-PVS position sensing. Minimum power consumption. 0x13 STANDBY Send to Standby (no analog output). Reduced power consumption. Absolute position only.

  • Page 47: Reboot

    UNFORCE_REQ command first. After the the posi- behaviour is equivalent to a power-on reset. tion data has been acquired, command FORCE_REQ needs to be issued in order for iC-PVS to start up- RESET dating the position information at register addresses The RESET command reinitializes the internal circuitry.

  • Page 48: Status Registers

    Sleep working state NOMAG_L: NoMagnet Working State (latched) Table 60: Status Registers When entering the NoMagnet state, iC-PVS sets the status bit NOMAG_L. The bit is latched, i.e. it remains set even if the NoMagnet state is left again. Therefore, The iC-PVS has several error conditions.

  • Page 49: Pdr: Power Down Reset Detected

    MAG_L, ANA_STUP are visible at NERR. Additionally, issuing a SCLR instruction. This can be interpreted as NERR is pulled low during the iC-PVS startup phase, an acknowledgment that this startup was intentional. If if the device is in sleep state or a reset condition is the bit is set later during field operation, it is most likely currently active.

  • Page 50: Design Review: Notes On Chip Functions

    Parameter OSS/OSC/OSD Configuration bits are inverted Parameter POLEWID = 0x7 Parameter setting POLEWID = 0x7 is not functional. Do not use. Table 62: Notes on chip functions regarding iC-PVS chip release Y iC-PVS X Function, parameter/code Description and application notes Parameter POLEWID = 0x7 Parameter setting POLEWID = 0x7 is not functional.

  • Page 51: Revision History

    product.

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