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9 Block Diagram
9.1.
Main Block Diagram
REG
S15.7
LNB1
LNB1
S3.3/S1.8
EU-Sat
IEC
Double
TU-IIC1
EXT_IFAGC1
IF1
IFAGC1
F
IF2
For
2
nd
EXT_IFAGC2
Tuner
TU-IIC2
F
I_2
Q_2
SAT_AGC2
I_1
Q_1
SAT_AGC1
Analog AV
Input
Y
(V)
R
Pb
L
Pr
Output
R
L
Head
Audio Out L/R
Phone
Head Phone L/R
OPT
Optical OUT
HDMI1
HPD* < MT5811
HDMI_5V_DET* > MT5811
HDMI2
HPD* < MT5811
HDMI_5V_DET* > MT5811
Lch:10W
Rch:10W
<
ODU_ON
>
ODU_DET
BE-IIC
DiSEqC1
S3.3/ S1.2
<
FE_XRST
EXT_IFAGC1
Transport
IF1
BE-IIC
Stream
DVB-T2/T/C
DATAIN[7:0]
TU-IIC1
DVB-S/S2
TU_Serial_TS1
SAT_AGC1
CLKIN
DEMOD
(TU_Para_TS1)
SYNCIN
I_1
1
Q_1
VAL_IN
DiSEqC1
TU_Serial_TS2 / TU_Serial_TS2_JP
Wired OR
(TU_Para_TS2)
41MHz
TU_Serial_TS1 / TU_Serial_TS1_JP
Wired OR
(TU_Para_TS1)
FEAINP
Low-IF
SAW
FEAINN
IF1
ADC
FLT
DTV
IFAGC1
Decoder
ATSC
SUB
DVB-T/C
MAIN
ATV
DEMOD
Decoder
Digital SIF
Digital CVBS
TV Decoder
CVBS
ADC
CVBS VFE
SCART_CVBS
VBI/COMB
Non Use
[0]
V-SW
YPbPr
ADC
RGB/YUV
[3:1]
Processor
Non Use : SCART_RGB, FB, SLOW,
SCART_CVBS OUT
Non Use
VDAC
L/R in
S3.3
R
R
R
R
R
R
LPF
A-SW
ADC
6dB
DAC
amp
LPF
VDOIN
ARC OUT
EDID0
Rx0
HDMI1.4
DDC* > MT5811
HDCP1.4
MT5581P
EDID1
Rx1
HDMI
HDMI1.4
Rx
DDC* > MT5811
HDCP1.4
MUX
x3
MT5581P+DSP
AMP:
Hornet
EDID2
Rx2
HDMI1.4
HDCP1.4
S1.8
S3.3
F16V
I2S(MCLK/LRCLK/BCLK/SDAT0)
I2S AMP
<
KEY1
YDA174-QZ
<
AUDIO_XRST,
AMP/HP MUTE
CONTROL PANEL KEY
<
KEY3
With DSP
>
SOUND_SOS
Main SW Soft Control
LUMINANCE
REMOCON
Sensor
Reciever
RMIN
>
AI_SENSOR
>
S5
CI_POWER_ON
>
<
CI_OCP
CI
Power
Circuit
S3.3
CI
Debug
eMMC
Connector
32Gb
EA[14:0]
IRQ
SCLK
MMCCLK
DATAIN[7:0]
DATAOUT[7:0]
RESET
HS200
WAIT
SDI
MMCCMD
CLKIN
CLKOUT
CD1
CE1/WE
SDO
200MHz
XERST
SYNCIN
SYNCOUT
CD2
OE/IOWR
(eMMC/SD)
(DDR)
CE#1
MMCDAT0-7
(SDR)
VAL_IN
VALOUT
IORD
STB1.05
S1.0
S3.3
S1.8
S1.5
DDR3
Internal CI
SPI-IF
SPI-IF
eMMC-IF
4Gbx16
controller
2pcs
DDR3
x32bit
Controller
Trans Port Demux
1800MHz(DDR)
3D/2D NR
Color
Scaler
Space
Convert
AV Decoder
HEVC/ VP9
2Dto3D
Dec video
Dec
Main
Local
Scannig PWM
Audio
IMGRSZ
B2R
SCE
Dimming
Sub
External Video(Analog)
Scaler
External Video(HDMI)
Gamma
LVDS
Tx
CVBS
TV Encorder
FHD:
LVDS 148.5MHz
OSD
RGB8bit ,H,V,DE 5pair(4data+1clk 74.25M) Dual 24bit
3D GPU
Graphics
RGB10bit,H,V,DE 6pair(5data+1clk 74.25M) Dual 30bit
Audio
Graphic Processor
WXGA:
ARM11
GPU
LVDS 78MHz
DSP
RGB8bit ,H,V,DE 5pair(4data+1clk 78M) Single 24bit
ARM Mali-450 432MHz
For Audio
Dual Core
SPDIF
SW
UART
UART
UART-DMA(NonUse)
USB2.0-IF
UART-PD(TK serial / uP Debug)
UART-DBG(Soft Debug)
USB2.0
(Port 0)
Host CPU
IIC
USB-IF
ARM Coretex-A7
BE_IIC0
IIC
USB2.0-IF
Quad Core
USB2.0
BE_IIC1
VGA-IIC(NonUse)
924MHz
(port1)
HUB_XRST <
Standby CPU
USB2.0
8bit-CPU
ARM
(Port 2)
Turbo8032
Common-Reset
uP
USB2.0
(Port3)
SD-IF
ETHER-IF
24MHz
STB5V
F15V
Paragon
Reset
<
TV_SOS
Circuit
AMP/HP MUTE
Analog
MONITOROUT MUTE
ASIC
STB3.3
LED Information
OVP
Safety
SOS
S3.3/1.8
Circuit
<
MON_MUTE
<
SP_HP_MUTE
G_LED_ON >
PWMA
R_LED_ON >
PWM_ENB
>
SDVOLC
PWMOUT
25
PF_C10
S1.5
DDR
DD
DDR3
DDR3
R
3
3
DDR3
x16
x16
x16
LCD
Panel
S16
PANEL
P12
Power
PANEL_VCC_ON
DCDC
LED Driver
BL_ON
>
BL_SOS
<
T-CON
PANEL_TEST_ON
>
PANEL_VCOM_WP
>
P-IIC
S3.3
24MHz
S5
USB*VBUS >
USB2.0-IF
USB-HUB
USB
< OCP*
Power SW
GL850G
USB-1
S5
USB*VBUS >
USB
< OVCUR*
Power SW
USB2.0-IF
USB-2
S5
STB5.3
For Wake up On Wireless (Euro)
USB
Power SW
IEEE802.11n
Wireless UNIT
WOW_ON_IRQ <
< WOW_PWR_ON
> WOW_OVP
ETHER
10/100M
100Base-TX
SD XC
/UHS-I
TX-32FSR500
S3.3
BT Module
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