Sanyo DVD-SL25 Service Manual page 24

IC BLOCK DIAGRAM & DESCRIPTION
IC800 ZR36742(A/V Decoder)
Pin No. Name
Boot selection, debug interface, GPIO pin, test mode (23pin)
40 BOOTSEL1
GPCI/O[0]#
208 DUPTD
2 DUPRD
41 GPCI/O[1]
42 GPCI/O[2]#
SSCSRQ
43 GPCI/O[3]
44 GPCI/O[4]
45~47 GPCI/O[5-7]
49 GPCI/O[8]#
SSCRXD
51 GPCI/O[9]#
SSCTXD
8 GPCI/O[10]#
SSCCLK
7 GPCI/O[11]#
SSCRRQ
5,6 GPCI/O[12-13]
4 GPCI/O[14]
197 GPCI/O[15]#
HSYNC
196 GPCI/O[16]#
VSYNC
195 GPCI/O[17]#
VCLK x 2
177 GPCI/O[18]#
COSYNC
3 GPCI/O[19]#
BOOTSEL2
206 TESTMODE
PLL signal (4 pin)
157 RESET#
161 GCLK
160
194 PLLCFGP#
GPCI/O[20]
Analog video port (5pin)
169 CVBS/G/Y
(DAC A)
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I/O
I# CPU software starting basis select I. Low:starting by flash memory.
High : starting by down loaded program from UART.
I/O# Controled general I/O by microcomputer software.
NMI I MN1 interrupt I.
O Debug UART data O.
I Debug UART (or IrDA) data I.
I/O Controled general I/O by microcomputer software.
USE general interrupt I.
I/O# Controled general I/O by microcomputer software.
Use general interrupt I.
I SSC mode : synchronization communication requeat reception.
I/O Controled general I/O by microcomputer software.
Use general interrupt I.
N/C
I/O Controled general I/O by microcomputer software.
Use general interrupt I.
I/O Controled general I/O by microcomputer software.
Use general interrupt I.
I SSC mode : synchronization communication data reception.
I/O Controled general I/O by microcomputer software.
O SSC mode : synchronization communication data transmission.
I/O# Controled general I/O by microcomputer software.
I SSC made : synchronization communication clock reception.
I/O# Controled general I/O by microcomputer software.
O SSC mode : synchronization communication acknowledge transmission.
I/O Controled general I/O by microcomputer software.
I/O Controled general I/O by microcomputer software.
I/O# Controled general I/O by microcomputer software.
O Horizontal synchronization O.
I/O# Controled general I/O by microcomputer software.
O Vertical synchronization O.
I/O# Controled general I/O by microcomputer software.
O VCLK x 2 O.
I/O# Controled general I/O by microcomputer software.
O Cosync O.
I/O# Controled general I/O by microcomputer software.
I Readed by BOOT ROM after hardware reset and used when select flash
ROM or flash ROM + SRAM set.
ID Direct connect to GNDP when usually operation.
ID
Reset I (Active low).
Initialize process start RESET# signal deassert.
ID 27.000MHz clock for main process generation or xtal I.
XO AO Connected xyal to GCLK O.
N/C when not use xtal.
ID# Process clock PLL set I.
Can change when RESET# assert.
Usually operation : low, RESET assert term.
I/O
Controled general I/O by microcomputer software.
AO YC O : CVBS signal O.
RGB O : G signal O.
YUV O : Y signsl O.
Function
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