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"SCHEMATIC DIAGRAM-2"
SIGNAL LINE
J
H
I
4
F=16.9344MHz
5
C722
10P
3.3V
(0V)
C721
10P
C718
R712
0.22
220
G
R709
47K
K J
A
R728
3.9K
B
C
D
E
F
G
7
3.3V
3.3V
3.3V
2.4V
P-P
61
62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
3.3V
60
V
DD
1.6V
59
X2 OUT
1.6V
58
X1 IN
57
Vss
F=16.9344MHz
56
SBCK
55
SUBC
54
VCOF2
53
PCK
52
EFM
IC702
51
AVss2
MN662790RSC
3.3V
AV
50
2
DD
SERVO PROCESSOR/
DIGITAL SIGNAL PROCESSOR/
VCOF
49
0V
DIGITAL FILTER/
PLLF
48
D/A CONVERTER
1.7V
DSLF
47
R741
47K
1.7V
PLAY
DRF
46
1V
IREF
45
1.7V
ARF
44
R742
WVEL
43
0.5 s. 0.2V/DIV.
220K
1.5V
DSLF2
42
PLLF2
41
40
39
38
37
36
PLAY
0.4V
P-P
2ms. 0.1V/DIV.
I H G
F
A
S701
TP1
TP3
(REST SW)
TP16
7.3V
CN702
1
2
8
R717
1K
PLAY
C731
10V220
2.2V
P-P
1kHz, 0dB
C730
0.1
R718
1K
BCLK
LRCK
PLAY
0.8V
3.3V
SRDATA
P-P
DV
1
DD
0V
T
13.3ms.
DVss1
TX
PLAY
3.3V
MCLK
MDATA
0V
T
13.3ms.
MLD
PLAY
SENSE
3.3V
/FLOCK
0V
/TLOCK
F=75Hz
BLKCK
PLAY
3.3V
SQCK
SUBQ
0V
DMUTE
0.7V
T
13.3ms.
P-P
STAT
PLAY
3.3V
/RST
SMCK
0V
CSEL
T
13.3ms.
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2ms. 0.1V/DIV.
E D C B A
A
B
C
D
E
F
G
B
C
D
E
F
G
H
TP4
TP6 TP7
TP8
TP12
TP13
TP14
3
4
5
6
7
8
9
10
C
To
MAIN CIRCUIT(CN402)
on SCHEMATICDIAGRAM-2/11,12-B~D
9
10
TP23
C727
50V1
A
TP21
C728
50V1
B
PLAY
1
2
3
0V
3.3V
0.1
s. 2V/DIV.
4
5
1.7V
6
I
3.3V
(3V)
7
H
0V
(0.3V)
8
G
3.3V
9
F
10
11
12
0V
E
13
3.3V
D
14
3.3V (3V)
15
C
16
0V (3.3V)
17
B
3.3V
18
A
19
20
PLAY
0.1V
P-P
I
TP17
TP15
TP19
TP22
C743
C753
0.1
470P
11
12
13
14
15
16
17
18
SL-HD560(E) CD SERVO CIRCUIT DIAGRAM
11
TP20
3.3V
3.3V
3.3V
B
A
19
12
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