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AMD XILINX 7 Series User Manual

AMD XILINX 7 Series User Manual

Fpgas and zynq-7000 soc xadc dual 12-bit 1 msps analog-to-digital converter
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7 Series FPGAs and
Zynq-7000 SoC XADC Dual
12-Bit 1 MSPS
Analog-to-Digital Converter
User Guide
UG480 (v1.11) June 13, 2022
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Summary of Contents for AMD XILINX 7 Series

  • Page 1 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide UG480 (v1.11) June 13, 2022 Xilinx is creating an environment where employees, customers, and partners feel welcome and included. To that end, we’re removing non-inclusive language from our products and related collateral.
  • Page 2 XADC User Guide UG480 (v1.11) June 13, 2022 www.xilinx.com...

  • Page 3: Table Of Contents

    Table of Contents Guide Contents..............5 Chapter 1: Introduction and Quick Start XADC Overview .
  • Page 4 External Analog Inputs ............66 PC Board Design Guidelines .

  • Page 5: Guide Contents

    Preface About This Guide Xilinx® 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. The Spartan®-7 family is the lowest density with the lowest cost entry point into the 7 series portfolio. The Artix®-7 family is optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive, high volume applications.

  • Page 6: Chapter 1: Introduction And Quick Start

    Chapter 1 Introduction and Quick Start This chapter provides a brief overview of the Xilinx 7 series FPGAs XADC functionality. The XADC is available in all Artix®-7, Kintex®-7, Virtex®-7, and Zynq®-7000 SoC devices. The XADC is also available in many, but not all Spartan®-7 devices. To identify specific devices that support the XADC block, consult...
  • Page 7 Chapter 1: Introduction and Quick Start X-Ref Target - Figure 1-1 VREP_0 VREFN_0 Temperature Supply VCCINT Sensor Sensors VCCAUX VCCBRAM VCCPINT °C On-Chip Ref Temperature VCCPAUX 1.25V VCCO_DDR Status Control VP_0 Registers Registers 12-bit, VN_0 1 MSPS VAUXP[0] ADC A VAUXN[0] 64 x 16 bits 64 x 16 bits...

  • Page 8: Xadc Pinout Requirements

    Chapter 1: Introduction and Quick Start XADC Pinout Requirements Dedicated Package Pins All XADC dedicated pins are located in bank 0 and thus have the _0 suffix in the package file names. Figure 1-2 shows the basic pinout requirements for the XADC. There are two recommended configurations.
  • Page 9 Chapter 1: Introduction and Quick Start Table 1-1: XADC Package Pins Package Pin Type Description This is the analog supply pin for the ADCs and other analog circuits in the XADC. It can be tied to the 1.8V V supply; however, in a mixed-signal CCAUX system, the supply should be connected to a separate 1.8V analog, if available.
  • Page 10 Chapter 1: Introduction and Quick Start Table 1-1: XADC Package Pins (Cont’d) Package Pin Type Description These are multi-function pins that can support analog inputs or can be used as regular digital I/O (see Figure 1-1). These pins support up to 16 negative input terminals of the differential auxiliary analog input channels Auxiliary analog _AD0N_ to...

  • Page 11: Instantiating The Xadc

    Chapter 1: Introduction and Quick Start Auxiliary analog inputs must be connected to the top level of the design. Note: Auxiliary channels 6, 7, 13, 14, and 15 are not supported on Kintex-7 devices. Some auxiliary analog channels might also not be supported in certain Virtex-7, Artix-7, Spartan-7, and Zynq-7000 SoC device package options. Users should consult the package file for the device.
  • Page 12 Chapter 1: Introduction and Quick Start Table 1-2: XADC Port Descriptions Port Description DI[15:0] Inputs Input data bus for the DRP. DO[15:0] Outputs Output data bus for the DRP. DADDR[6:0] Input Address bus for the DRP. Input Enable signal for the DRP. Input Write enable for the DRP.
  • Page 13 Chapter 1: Introduction and Quick Start Table 1-2: XADC Port Descriptions (Cont’d) Port Description Logic OR of bus ALM[6:0]. Can be used to flag the ALM[7] Output occurrence of any alarm. Output Over-Temperature alarm output. These outputs are used in external multiplexer mode. They indicate the address of the next channel in a sequence to be MUXADDR[4:0] Outputs...
  • Page 14 Chapter 1: Introduction and Quick Start XADC Attributes The block diagram in Figure 1-1 shows the control registers that define the operation of the XADC. The control registers are a set of 32 16-bit registers. As mentioned, these registers can be read and written through the DRP or JTAG ports.
  • Page 15 Chapter 1: Introduction and Quick Start This design assumes an external 50 MHz clock is used for DCLK, and the XADC is configured to monitor temperature, supply voltages, and activate alarms if safe limits are exceeded. This example is explained in detail in XADC Software Support, page XADC #(...
  • Page 16 Chapter 1: Introduction and Quick Start ADC and Sensors More comprehensive information regarding the operation of the ADCs and on-chip sensors can be found Chapter 2, Analog-to-Digital Converter. This section provides a brief overview to help users to quickly interpret data read from the status registers and verify the operation of the XADC. Analog-to-Digital Converter The ADCs have a nominal analog input range from 0V to 1V.

  • Page 17: Chapter 2: Analog-To-Digital Converter

    Chapter 2 Analog-to-Digital Converter The XADC block contains two 12-bit, 1 MSPS ADCs. These ADCs are available for use with both external analog inputs and on-chip sensors. Several predefined operating modes are available that cover the most typical use cases for these ADCs. The various operating modes are covered in Chapter 4, XADC Operating Modes.
  • Page 18 Chapter 2: Analog-to-Digital Converter Unipolar Mode Figure 2-2 shows the 12-bit unipolar transfer function for the ADCs. The nominal analog input range to the ADCs is 0V to 1V in this mode. The ADC produces a zero code (000h) when 0V is present on the ADC input and a full scale code of all 1s (FFFh) when 1V is present on the input.
  • Page 19 Chapter 2: Analog-to-Digital Converter Bipolar Mode When the external analog input channels of the ADCs are configured as bipolar, they can accommodate true differential and bipolar analog signal types (see the Analog Inputs section). When dealing with differential signal types, it is useful to have both sign and magnitude information about the analog input signal.

  • Page 20: Analog Inputs

    Chapter 2: Analog-to-Digital Converter Analog Inputs The analog inputs of the ADC use a differential sampling scheme to reduce the effects of common-mode noise signals. This common-mode rejection improves the ADC performance in noisy digital environments. Figure 2-4 shows the benefits of a differential sampling scheme. Common ground impedances (R ) couple noise voltages (switching digital currents) into other parts of a system.
  • Page 21 Chapter 2: Analog-to-Digital Converter Auxiliary Analog Inputs The auxiliary analog inputs (VAUXP[15:0] and VAUXN[15:0]) are analog inputs that are shared with regular digital I/O package balls. The auxiliary analog inputs are automatically enabled when the XADC is instantiated in a design, and these inputs are connected on the top level of the design. The auxiliary analog inputs do not require any user-specified constraints or pin locations.
  • Page 22 Chapter 2: Analog-to-Digital Converter Analog Input Description Figure 2-5 illustrates an equivalent analog input circuit for the external analog input channels in both unipolar and bipolar configurations. The analog inputs consist of a sampling switch and a sampling capacitor used to acquire the analog input signal for conversion. During the ADC acquisition phase, the sampling switch is closed, and the sampling capacitor is charged up to the voltage on the analog input.
  • Page 23 Chapter 2: Analog-to-Digital Converter operation is enabled, the differential analog inputs (V and V ) have an input range of 0V to 1.0V. In this mode, the voltage on V (measured with respect to V ) must always be positive. Figure 2-6 shows a typical application of unipolar mode.
  • Page 24 Chapter 2: Analog-to-Digital Converter maximum differential input voltages of ±0.5V and assuming balanced inputs on V and V , the common mode voltage must lie in the range 0.25V to 0.75V. X-Ref Target - Figure 2-8 2.5V ±0.25V Common Voltage Common Mode Range 0.25V to 0.75V 0.25V to 0.75V...
  • Page 25 Chapter 2: Analog-to-Digital Converter X-Ref Target - Figure 2-9 FFFh FFEh FFDh 1 LSB 0.123°C Full Scale Transition B5Fh 977h 767h 002h 001h 000h Temperature (°C) X17025-110817 Figure 2-9: Temperature Sensor Transfer Function The temperature measurement result is stored in the status registers at DRP address 00h. Monitoring FPGA on-chip temperature avoids functional and irreversible failures by ensuring critical operating temperatures are not exceeded.
  • Page 26 Chapter 2: Analog-to-Digital Converter Figure 2-10 shows the power-supply sensor transfer function after digitizing by the ADC. The power supply sensor can be used to measure voltages in the range 0V to V + 5% with a resolution of CCAUX approximately 0.73 mV.

  • Page 27: Chapter 3: Xadc Register Interface

    Chapter 3 XADC Register Interface Figure 3-1 illustrates the XADC register interface. All registers in the register interface are accessible through the dynamic reconfiguration port (DRP). The DRP can be accessed through a FPGA logic port or the JTAG TAP. Access is governed by an arbitrator (see DRP Arbitration, page 43).
  • Page 28 Chapter 3: XADC Register Interface X-Ref Target - Figure 3-1 Status Registers (00h–3Fh) Control Registers (40h–7Fh) Read Only Read and Write Temp (00h) Temp Max (20h) Alarm Reg. #0 (50h) Config Reg. #0 (40h) (01h) Max (21h) Alarm Reg. #1 (51h) CCINT CCINT Config Reg.

  • Page 29: Status Registers

    Chapter 3: XADC Register Interface Status Registers The first 64 address locations (DADDR[6:0] = 00h to 3Fh) contain the read-only status registers. The status registers contain the results of an analog-to-digital conversion of the on-chip sensors and external analog channels. All sensors and external analog-input channels have a unique channel address (see Table 3-7, page 37).
  • Page 30 Chapter 3: XADC Register Interface Table 3-1: Status Registers (Read Only) (Cont’d) Name Address Description The result of the on-chip V supply monitor CCBRAM measurement is stored at this location. The data is MSB CCBRAM justified in the 16-bit register. The 12 MSBs correspond to the supply sensor transfer function shown in Figure 2-10.
  • Page 31 Chapter 3: XADC Register Interface Table 3-1: Status Registers (Read Only) (Cont’d) Name Address Description Minimum V measurement recorded since power-up CCINT Min V CCINT or the last XADC reset. Minimum V measurement recorded since power-up CCAUX Min V CCAUX or the last XADC reset.
  • Page 32 Chapter 3: XADC Register Interface Flag Register The Flag Register is shown in Figure 3-2. The bit definitions are described in Table 3-2. X-Ref Target - Figure 3-2 DI15 DI14 DI13 DI12 DI11 DI10 Flag Register JTGD JTGR REF ALM6 ALM5 ALM4 ALM3 OT ALM2 ALM1...
  • Page 33 Chapter 3: XADC Register Interface Calibration Coefficients Definition As mentioned previously, the offset and gain calibration coefficients are stored in the status registers. This section explains how to interpret the values in these registers. These are read-only registers, and it is not possible to modify the contents through the DRP.

  • Page 34: Control Registers

    Chapter 3: XADC Register Interface Control Registers The XADC has 32 control registers that are located at DRP addresses 40h to 5Fh (see Table 3-3). These registers are used to configure the XADC operation. All XADC functionality is controlled through these registers.
  • Page 35 Chapter 3: XADC Register Interface Configuration Registers (40h to 42h) The first three registers in the control register block configure the XADC operating modes. These registers are known as XADC configuration registers. Their bit definitions are illustrated in Figure 3-4. Note: Bits shown as 0 should always be left set to 0.
  • Page 36 Chapter 3: XADC Register Interface Table 3-4: Configuration Register 0 Bit Definitions (Cont’d) Name Description These bits are used to set the amount of sample averaging on selected channels in both single channel and sequence DI12, DI13 AVG0, AVG1 modes (see Table 3-8 Chapter 4, XADC Operating Modes).
  • Page 37 Chapter 3: XADC Register Interface Table 3-7: ADC Channel Select Description Channel On-chip temperature CCINT CCAUX – Dedicated analog inputs (1.25V) REFP (0V) REFN CCBRAM Invalid channel selection Carry out an XADC calibration 9–12 Invalid channel selection CCPINT CCPAUX CCO_DDR VAUXP[0], VAUXN[0] –...
  • Page 38 Chapter 3: XADC Register Interface Table 3-9: Sequencer Operation Settings SEQ3 SEQ2 SEQ1 SEQ0 Function Default mode Single pass sequence Continuous sequence mode Single channel mode (sequencer off) Simultaneous sampling mode Independent ADC mode Default mode Table 3-10: Calibration Enables Name Description CAL0...

  • Page 39: Drp Jtag Interface

    Chapter 3: XADC Register Interface Test Registers (43h to 47h) These registers, intended for factory test purposes only, have a default status of zero. You must not write to these registers. Channel Sequencer Registers (48h to 4Fh) These registers are used to program the channel sequencer functionality. For more information see Automatic Channel Sequencer, page Alarm Registers (50h to 5Fh) These registers are used to program the alarm thresholds for the automatic alarms on the internally...
  • Page 40 Chapter 3: XADC Register Interface XADC DRP JTAG Write Operation Figure 3-5 shows a timing diagram for a write operation to the XADC DRP through the JTAG TAP. The DRP is accessed through the XADC data register (XADC DR). Before the XADC DR is accessed, the instruction register (IR) must first be loaded with the XADC instruction.
  • Page 41 Chapter 3: XADC Register Interface DRP_DCLK JTAG_TCK  ---------------------------- - -------------------------- - Equation 3-1 Where: RTI = Required number of additional RTI states to ensure arbitration has fully resolved = Frequency of TCK used for JTAG JTAG_TCK = Frequency of DCLK used for XADC DRP interface DRP_DCLK XADC DRP JTAG Read Operation Figure 3-6...
  • Page 42 Chapter 3: XADC Register Interface result of a read operation is being shifted out of the XADC DR, an instruction for the next read can be shifted in. JTAG DRP Commands The data shifted into the 32-bit XADC DR during a DR-scan operation instructs the arbitrator to carry out a write, read, or no operation on the XADC DRP.
  • Page 43 Chapter 3: XADC Register Interface DRP Arbitration Because the DRP registers are accessed from two different ports (interconnect and JTAG TAP), access must be carefully managed. An arbitrator is implemented to manage potential conflicts between the FPGA logic (fabric) and JTAG port. Arbitration is managed on a per transaction basis (a transaction is a single read/write operation to the DRP).

  • Page 44: Zynq-7000 Soc Processing System (Ps) To Xadc Dedicated Interface

    Chapter 3: XADC Register Interface Zynq-7000 SoC Processing System (PS) to XADC Dedicated Interface The DRP JTAG interface described in DRP JTAG Interface, page 39 is also used to provide a dedicated interface between the processor subsystem and the XADC block located in the programmable logic region of the Zynq-7000 SoC.

  • Page 45: Chapter 4: Xadc Operating Modes

    Chapter 4 XADC Operating Modes The XADC includes several operating modes that cover some of the most common use cases for this kind of functionality. The most basic mode of operation is called default mode, where the XADC monitors all on-chip sensors and requires no configuration of the XADC.
  • Page 46 Chapter 4: XADC Operating Modes ADC Channel Selection Registers (48h and 49h) The ADC channel selection registers enable and disable a channel in the automatic channel sequencer. The bits for these registers are defined in Table 4-1 Table 4-2. The two 16-bit registers are used to enable or disable the associated channels.
  • Page 47 Chapter 4: XADC Operating Modes Table 4-2: Sequencer Auxiliary Channel Selection (49h) (Cont’d) Sequence Number ADC Channel Description 7 Series/Zynq-7000 VAUXP[5], VAUXN[5] – 14/17 Auxiliary channel 5 VAUXP[6], VAUXN[6] – 15/18 Auxiliary channel 6 VAUXP[7], VAUXN[7] – 16/19 Auxiliary channel 7 VAUXP[8], VAUXN[8] –...

  • Page 48: Sequencer Modes

    Chapter 4: XADC Operating Modes coefficient registers require 16 conversions before the coefficients are updated. Averaging is fixed at 16 samples for calibration. ADC Channel Analog-Input Mode (4Ch and 4Dh) These registers are used to configure an ADC channel as either unipolar or bipolar in the automatic sequence (see Analog Inputs, page 20).
  • Page 49 Chapter 4: XADC Operating Modes Table 4-3: Default Mode Sequence (Cont’d) Order Channel Address Description supply sensor CCBRAM CCBRAM Notes: 1. Only available on the Zynq-7000 SoC devices. Single Pass Mode In single pass mode, the sequencer operates for one pass through the sequencer channel select registers (48h and 49h) and then halts.
  • Page 50 Chapter 4: XADC Operating Modes Table 4-4: Sequencer Register (49h) Bit Definitions for Simultaneous Sampling Mode Sequence Number ADC Channel Description 16, 24 Auxiliary channels 0 and 8 17, 25 Auxiliary channels 1 and 9 18, 26 Auxiliary channels 2 and 10 19, 27 Auxiliary channels 3 and 11 20, 28...
  • Page 51 Chapter 4: XADC Operating Modes Only the dedicated channel and auxiliary analog input channels can be assigned to ADC B in this sequencer mode. The internal channels (sensors) are automatically assigned to ADC A, which automatically monitors these channels and generates alarms based on the user-defined alarm thresholds. As with simultaneous sampling mode, it is not possible to select an automatic calibration of ADC B in this sequencer mode.

  • Page 52: External Multiplexer Mode

    Chapter 4: XADC Operating Modes Table 4-6: Independent ADC Sequencer Mode Bit Definitions (49h) Sequence Number ADC Channel Description Auxiliary channel 0 Auxiliary channel 1 Auxiliary channel 2 Auxiliary channel 3 Auxiliary channel 4 Auxiliary channel 5 Auxiliary channel 6 Auxiliary channel 7 Auxiliary channel 8 Auxiliary channel 9...
  • Page 53 Chapter 4: XADC Operating Modes External Multiplexer Operation Figure 4-1 illustrates the external multiplexer concept. In this example an external 16:1 analog multiplexer is used instead of consuming the 32 FPGA I/Os required to implement the 16 auxiliary analog input channels using the internal multiplexer.
  • Page 54 Chapter 4: XADC Operating Modes X-Ref Target - Figure 4-2 VAUXP[0] VAUXN[0] FPGA VAUXP[1] VAUXP[0] VAUXN[1] 12-Bit, VAUXN[0] VAUXP[7] 1 MSPS ADC A VAUXN[7] ADDR VAUXP[8] VAUXN[8] 12-Bit, VAUXP[9] 1 MSPS VAUXP[8] VAUXN[9] ADC B VAUXP[15] VAUXN[8] VAUXN[15] MUXADDR[2:0] ADDR X17036-110817 Figure 4-2: External Multiplexer Mode for Simultaneous Sampling In both cases, the MUXADDR[4:0] bus is used to automatically select the external multiplexer channel.

  • Page 55: Maximum And Minimum Status Registers

    Chapter 4: XADC Operating Modes Maximum and Minimum Status Registers The XADC also tracks the minimum and maximum values recorded for the internal sensors since the last power-up or since the last reset of the XADC control logic. The maximum and minimum values recorded are stored in the DRP status registers starting at address 20h (see Status Registers, page 29).
  • Page 56 Chapter 4: XADC Operating Modes are MSB justified. Limits are derived from the temperature and power-supply sensor transfer functions (see Figure 2-9, page 25 Figure 2-10, page 26). Table 4-8: Alarm Threshold Registers Control Register Description Alarm Temperature upper ALM[0] upper ALM[1] CCINT...
  • Page 57 Chapter 4: XADC Operating Modes Thermal Management The on-chip temperature measurement is used for critical temperature warnings and also supports automatic shutdown to help prevent the device from being permanently damaged. The on-chip temperature measurements record the junction temperatures continuously during pre-configuration and automatic shutdown.
  • Page 58 Chapter 4: XADC Operating Modes As shown in Figure 4-4, when the die temperature exceeds the OT upper threshold (or the default 125°C), the over-temperature alarm logic output becomes active and 10 ms later the device initiates the shutdown sequence. When the automatic shutdown starts, the device is disabled and GHIGH is asserted to prevent any contention (see UG470, 7 Series FPGAs Configuration User Guide [Ref 3]).
  • Page 59 Chapter 4: XADC Operating Modes Changes to Offset and Gain Calibration Operation If the XADCEnhancedLinearity option is not enabled (that is, OFF), there is no change to the XADC operation when offset and gain calibration is enabled. See XADC Calibration Coefficients, page 32, for an explanation of how the ADC offset and gain calibration is enabled.

  • Page 60: Chapter 5: Xadc Timing

    Chapter 5 XADC Timing All XADC timing is synchronized to the DRP clock (DCLK). The ADCCLK is generated by dividing DCLK by the user selection in configuration register 2 (see Control Registers, page 34). ADCCLK is an internal clock used by the ADCs and is not available externally. ADCCLK is only included here to aid in describing the timing.

  • Page 61: Event-Driven Sampling

    Chapter 5: XADC Timing Acquisition Phase During the acquisition phase, the ADC acquires the voltage on a selected channel to perform the conversion. The acquisition phase involves charging a capacitor in the ADC to the voltage on the selected channel (see Analog Input Description, page 22 for more information).
  • Page 62 Chapter 5: XADC Timing X-Ref Target - Figure 5-2 X17039-110817 Figure 5-2: Event Driven Sampling Mode The DCLK must always be present when using event-driven sampling mode. If no DCLK is present, the XADC reverts to continuous mode timing using an internal clock oscillator. A Low-to-High transition (rising edge) on CONVST or CONVSTCLK defines the exact sampling instant for the selected analog-input channel.

  • Page 63: Dynamic Reconfiguration Port (Drp) Timing

    Chapter 5: XADC Timing Dynamic Reconfiguration Port (DRP) Timing Figure 5-3 illustrates a DRP read and write operation. When the DEN is logic High, the DRP address (DADDR) and write enable (DWE) inputs are captured on the next rising edge of DCLK. DEN should only go high for one DCLK period.

  • Page 64: Chapter 6: Application Guidelines

    Chapter 6 Application Guidelines The 7 series FPGAs XADC is a precision analog measurement system based on a 12-bit analog-to-digital converter (ADC) with an LSB size approximately equal to 250 µV. To achieve the best possible performance and accuracy with all measurements (both on-chip and external), several dedicated pins for the ADC reference and power supply are provided.
  • Page 65 Chapter 6: Application Guidelines circuit which needs to be considered. The filtering should ensure no more than 1 LSB (250 uV) of noise on the reference output to minimize any impact on ADC accuracy at 12 bits. The other source of noise coupling into the ADC is from the ground reference GNDADC. In mixed-signal designs, it is common practice to use a separate analog ground plane for analog circuits to isolate the analog and digital ground return paths to the supply.

  • Page 66: External Analog Inputs

    Chapter 6: Application Guidelines X-Ref Target - Figure 6-2 X17042-110817 Figure 6-2: Ferrite Bead Characteristic External Analog Inputs The analog inputs are high-impedance differential inputs. The differential input scheme enables the rejection on common mode noise on any externally applied analog-input signal. Because of the high impedance of each input (such as V and V ), the input AC impedance is typically determined by the...

  • Page 67: Pc Board Design Guidelines

    Chapter 6: Application Guidelines See XAPP795, Driving the Xilinx Analog-to-Digital Converter Application Note [Ref 7] for more details. In Figure 6-3, resistors R1 and R2 divide a 10V supply down to 1V to work with the XADC. R5 has been impedance matched to the parallel resistance of R1 and R2.
  • Page 68 Chapter 6: Application Guidelines X-Ref Target - Figure 6-4 X17044-110817 Figure 6-4: Routing Channels to Center of Array Created by Staggering Vias (Note1) GNDADC CCADC (Note 2) (Note 3) X17045-110817 X-Ref Target - Figure 6-5 Figure 6-5: Reference Inputs (V and V ) should be Routed as Differential Pairs into the Center of REFP...
  • Page 69 Chapter 6: Application Guidelines Notes relevant to Figure 6-5: Place anti-alias filters for analog inputs close to the FPGA. Place 100 nF decoupling for V and V here. REFP CCADC Place external reference IC and any dedicated analog power supply regulation as close to the FPGA as possible.
  • Page 70 Chapter 6: Application Guidelines For more information on the XADC wizard, see PG091, XADC Wizard LogiCORE IP Product Guide for Vivado Design Suite [Ref Example Design Instantiation The following HDL example sets up the XADC to monitor all the FPGA on-chip sensors, that is, Temperature, V , and V of a 7 series FPGA.
  • Page 71 Chapter 6: Application Guidelines parameter init_read = 8'h00, read_waitdrdy = 8'h01, write_waitdrdy = 8'h03, read_reg00 = 8'h04, reg00_waitdrdy = 8'h05, read_reg01 = 8'h06, reg01_waitdrdy = 8'h07, read_reg02 = 8'h08, reg02_waitdrdy = 8'h09, read_reg06 = 8'h0a, reg06_waitdrdy = 8'h0b, read_reg10 = 8'h0c, reg10_waitdrdy = 8'h0d, read_reg11...
  • Page 72 Chapter 6: Application Guidelines if (eos == 1) state <=reg00_waitdrdy; reg00_waitdrdy : if (drdy ==1) begin MEASURED_TEMP = do_drp; state <=read_reg01; else begin den_reg = { 1'b0, den_reg[1] } ; dwe_reg = { 1'b0, dwe_reg[1] } ; state = state; read_reg01 : begin daddr = 7'h01;...
  • Page 73 Chapter 6: Application Guidelines den_reg = 2'h2; // performing read state <= reg10_waitdrdy; reg10_waitdrdy : if (drdy ==1) begin MEASURED_AUX0 = do_drp; state <= read_reg11; else begin den_reg = { 1'b0, den_reg[1] } ; dwe_reg = { 1'b0, dwe_reg[1] } ; state = state;...
  • Page 74 Chapter 6: Application Guidelines endcase XADC #(// Initializing the XADC Control Registers .INIT_40(16'h9000),// averaging of 16 selected for external channels .INIT_41(16'h2ef0),// Continuous Seq Mode, Disable unused ALMs, Enable calibration .INIT_42(16'h0400),// Set DCLK divides .INIT_48(16'h4701),// CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration .INIT_49(16'h000f),// CHSEL2 - enable aux analog channels 0 - 3 .INIT_4A(16'h0000),// SEQAVG1 disabled .INIT_4B(16'h0000),// SEQAVG2 disabled...
  • Page 75 Chapter 6: Application Guidelines endmodule Example Design Test Bench The following is a simple test bench that sets up a DCLK of 50 MHz and then reads the status registers (conversion results) at the end of a sequence when EOS goes High. The test bench also does a write to the DRP after the reset to disable the averaging on the sensor channels.
  • Page 76 Chapter 6: Application Guidelines .RESET (RESET), .ALM (ALM), .DCLK (DCLK), .MEASURED_TEMP (MEASURED_TEMP), .MEASURED_VCCINT (MEASURED_VCCINT), .MEASURED_VCCAUX (MEASURED_VCCAUX), .MEASURED_VCCBRAM (MEASURED_VCCBRAM), .MEASURED_AUX0 (MEASURED_AUX0), .MEASURED_AUX1 (MEASURED_AUX1), .MEASURED_AUX2 (MEASURED_AUX2), .MEASURED_AUX3 (MEASURED_AUX3) endmodule Simulation Output The simulation output shown in Figure 6-6 shows two passes through the user-defined sequence in continuous sampling mode.
  • Page 77 Chapter 6: Application Guidelines X-Ref Target - Figure 6-7 Read (do_drp) valid on DRDY high for Config Reg0(40h) Write valid on DRDY DRP Read DRP Write For illustrative purposes, simulated with Config Reg0 (40H) set to 903Fh X17047-110817 Figure 6-7: DRP Write When the EOS signal pulses high for one DCLK period at the end of a sequence (at approximately 30 µs) the test bench reads the Status registers (see...

  • Page 78: Appendix 7: Additional Resources And Legal Notices

    Appendix 7 Additional Resources and Legal Notices Xilinx Resources For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx Support. Solution Centers See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design assistance, advisories, and troubleshooting tips.

  • Page 79: References

    Appendix 7: Additional Resources and Legal Notices References Additional material useful to this document can be found here: (PG019), LogiCORE IP AXI XADC (v1.0) Product Guide (UG475), 7 Series FPGAs Packaging and Pinout Product Specifications User Guide (UG470), 7 Series FPGAs Configuration User Guide (UG585), Zynq-7000 All Programmable SoC Technical Reference Manual (PG091), XADC Wizard LogiCORE IP Product Guide for Vivado Design Suite (XAPP554), XADC Layout Guidelines Application Note...

  • Page 80: Revision History

    Appendix 7: Additional Resources and Legal Notices Revision History The following table shows the revision history for this document. Date Version Revision 03/01/2011 Initial Xilinx release. 03/28/2011 Added “Dual 12-Bit MSPS Analog-to-Digital Converter” to document title. Modified first paragraph and added second paragraph in Chapter 1, Introduction and Quick Start.
  • Page 81 Appendix 7: Additional Resources and Legal Notices Date Version Revision 10/25/2012 Min/max register lists were updated for Zynq-7000 SoC devices in Figure 3-1. In (Cont’d) Table 3-1 the V description was updated, new Zynq-7000 device channels V REFN CCPINT , and V were added.

  • Page 82: Please Read: Important Legal Notices

    Appendix 7: Additional Resources and Legal Notices Date Version Revision 10/21/2014 Clarified 7 series terminology throughout. Updated Preface to include Zynq-7000 SoC description, and added link to design files. Modified location of ferrite beads in Figure 1-2 Figure 6-1. Added equation and explanation to XADC DRP JTAG Write Operation in Chapter 3.

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