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2.8.
A-Board (12/12)
A-BOARD (12/12)
!
ISDB-T/S/DVB-T2/DTMB/JPN_W
To Tuner
T2AGC1_T
T2_FEAINN
T2_FEAINP
R6804
R6805
680
680
FEF_FLAG
91
92
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SUB3.3V
R6882
0
R6813
R6812
68
68
C6830
C6806
R6818
16V
10V
68
0.1u
10u
C6820
C6822
16V
16V
0.1u
0.1u
IC6800
C6809
16V
25
12
0.1u
VSS
C6847
26
11
50V
R6840
VSS
TESTIN
CVDD
8p
27
TSDATA4
10
470
CVDD
TSDATA3
TSDATA1
28
9
RST_X
TSDATA0
29
8
SLVADR3
DVDD
30
7
X6800
C6844
NC
VSS
16V
31
6
41MHz
0.1u
NC
TSCLK
32
5
XVDD
TAINP
TSVALID
33
TAINM
4
XTALO
TIFAGC
TSSYNC
34
3
C6848
XTALI
50V
35
2
8p
36
1
R6881
R6880
FE_3.3V
3.3k
3.3k
R6884
10k
C6873
16V
0.1u
C6804
16V
0.1u
C6872
16V
0.1u
R6821
0
R6819
0
R6820
0
POWER_FE
IC5701
SUB3.3V
R5707
8
VOUT
1
VCC
C5704
C5703
R5709
10V
10V
1.2k
1u
1u
7
2
1%
FB
SUB3.3V
N.C.
R5710
3k
1%
6
GND
3
N.C.
R5736
10k
5
4
N.C.
EN
FIN
93
94
DMD_1.2/1.1V
FE_3.3V
L6801
L6802
L6800
C6832
C6805
C6864
10V
16V
10V
10u
10u
0.1u
To Paragon
P_HS1DIN7
P_HS1DIN6
P_HS1DIN5
R6846
68
P_HS1DIN4
R6847
68
P_HS1DIN3
R6848
68
P_HS1DIN2
R6861
68
P_HS1DIN1
C6838
16V
0.1u
C6840
16V
0.1u
R6849
68
P_HS1VALIN
R6850
68
P_HS1SYNCIN
R6862
68
P_HS1DIN0
R6863
68
P_HS1BCLKIN
R6810
3.3k
To tuner
RESET
P_XIRQ7
FE_XRST
To IIC
DEMOD_SCL
DEMOD_SDA
DMD_1.2/1.1V
0
95
96
12
DMD0
NIM-FE
R6731
R6728
To Peaks
680
680
BSIQ_I0_T
P_FEAINP0
BS0
R6730
R6729
IF2(ALIF)
680
680
BSIQ_Q0_T
P_FEAINN0
R6722
To 707
0
FEAINP0_T
T2_FEAINP
IF0(JPN)
R6723
IF1(DLIF)
0
FEAINN0_T
T2_FEAINN
To Peaks
R6734
10k
AGCI0_T
P_AGCI0
C6746
16V
0.1u
R6726
R6724
0
0
To 707
T2AGC1_T
AGCBS0_T
RESET
VJ6711
To Peaks
FE_SAT_XRST
P_AGCBS1
S
Reset_Low_Start
FE_SAT_XRST
VJ6712
Reset_Low_Start
FE_XRST_T
P_XIRQ7
S
FE_XRST
Pro4_DMD2
NIM-RRO4-DMD1
VJ6806
To Sheet Peaks
DMD_SDA1_T
JP_DMDSDA2
S
DMD_SCL1_T
JP_DMDSCL2
S
VJ6807
To Sheet Peaks
VJ6875
BSIQ_Q1_T
P_BSIQ_Q1
S
BSIQ_I1_T
P_BSIQ_I1
S
VJ6876
To Sheet Peaks
VJ6864
FEAINP1_T
P_FEAINP1
S
VJ6865
FEAINN1_T
P_FEAINN1
S
97
98
99
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