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Schematic Diagram
10-1-4 Input_Buffer
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Power
Signal
M
A
N I
_
Y
M
A
N I
_
C
S
U
B
_
Y
S
U
B
_
C
C
O
M
P
_ 1
Y
C
O
M
P
_ 1
P
C
O
M
P
_ 1
r P
C
O
M
P
_ 2
Y
C
O
M
P
_ 2
P
C
O
M
P
_ 2
r P
M
T
N
R
_
C
V
M
T
N
R
_
S
F I
S
T
N
R
_
C
V
S
T
N
R
_
S
F I
D
T
V
_
C
V
B
10-4
X
R
E
F
X
R
E
F
C
N
2
7 5
X
R
E
F
S
M
W
0 2
- 0
0 3
C
X
R
E
F
1
2
3
4
5
6
X
R
E
F
7
8
9
0 1
X
R
E
F
b
1 1
2 1
X
R
E
F
3 1
4 1
5 1
6 1
7 1
8 1
X
R
E
F
9 1
0 2
1 2
2 2
X
R
E
F
b
3 2
4 2
X
R
E
F
5 2
6 2
7 2
8 2
9 2
0 3
B
S
X
R
E
F
X
R
E
F
B
S
A
V
i S
n g
l a
C
n o
e n
i t c
n o
X
R
E
F
B
e
w t
e
n e
A
n
l a
g o
a
d n
D
i g i
X
R
E
F
S
X
R
E
F
R
2
1
K
R
2
3 1
X
R
E
F
M
O
N
_
M
X I
E
D
_
V
_
O
U
T
X
R
E
F
M
O
N
_
V
_
O
U
T
R
2
1 2
R
2
2 2
R
2
7 2
l a t
X
R
E
F
C
A
P
_
Y
_
O
U
T
X
R
E
F
C
A
P
_
V
_
O
U
T
R
2
3 3
8
V
_
4 6
5 2
0 1
R
2
1 1
R
2
2 1
X
R
E
F
M
O
N
_
V
O
U
T
C
2
4 0
R
2
8 1
Q
2
6 0
8
V
_
4 6
5 2
Q
2
1 1
R
2
1 3
X
R
E
F
C
A
P
_
C
V
B
S
R
2
4 3
Q
2
2 1
R
2
5 3
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