SiFive E300 Reference Manual

Hide thumbs

Table Of Contents

Table of Contents

Quick Links

Download this manual

SiFive E300 Platform Reference Manual

Version 1.0.1

c SiFive, Inc.

Table of Contents

Need help?

Do you have a question about the E300 and is the answer not in the manual?

Questions and answers

Summary of Contents for SiFive E300

Page 1 SiFive E300 Platform Reference Manual Version 1.0.1 c SiFive, Inc.
Page 2 SiFive E300 Platform Reference Manual, Version 1.0.1...
Page 3: Sifive E300 Platform Reference Manual
ﬁtness for a particular purpose and non-infringement. SiFive does not assume any liability rising out of the application or use of any product or circuit, and speciﬁcally disclaims any and all liability, including without limitation indirect, incidental, special, exemplary, or consequential damages.
Page 4 SiFive E300 Platform Reference Manual, Version 1.0.1...
Page 5: Table Of Contents
Contents SiFive E300 Platform Reference Manual Introduction Block Diagram ......... .
Page 6 Memory Map ......... . . 22 E300 Power, Reset, Clock, Interrupt (PRCI) Control and Status Registers PRCI Address Space Usage .
Page 8 SiFive E300 Platform Reference Manual, Version 1.0.1 13.13 Receive Watermark Register (rxmark) ......46 13.14 Interrupt Registers (ie and ip) .
Page 9: Introduction
This manual should be read together with the E3 Coreplex manual. All aspects of the base E300 platform can be ﬂexibly conﬁgured. In addition, the platform can be readily extended with customer-speciﬁc instruction-set extensions, custom coprocessors, custom accelerators, custom I/O, and custom always-on blocks.
Page 10: Custom Accelerators
Local Interrupts Reset Unit Freedom E300 Platform Figure 1.1: Top-Level Block Diagram of the E300 platform. Custom Accelerators Custom autonomous accelerators can be added to provide application-speciﬁc processing. The custom accelerators can directly access on-chip memories and peripheral devices, and can gen- erate and receive interrupts from the platform-level interrupt controller.
Page 11: Peripheral Devices
Always-On Block and Power Management E300 SoCs can be conﬁgured with active power management to reduce leakage current in sleep mode. The Always-On Block (AON) supports low-power sleep with wakeup from an internal real- time clock interrupt or external I/O stimulus, or custom always-on circuitry.
Page 12 SiFive E300 Platform Reference Manual, Version 1.0.1...
Page 13: E300 Platform Memory Map
Chapter 2 E300 Platform Memory Map The overall memory map of E300 is shown in Table 2.1. Base Description (see E3 Coreplex Manual) E3 Coreplex (256 MiB) 0x0000 0000 0x0FFF FFFF Always-On (AON) ( 32 KiB) 0x1000 0000 0x1000 7FFF...
Page 14 SiFive E300 Platform Reference Manual, Version 1.0.1...
Page 15: E300 Power Modes
Chapter 3 E300 Power Modes This chapter describes the different power modes available on E300 systems. E300 systems currently support three power modes: Run, Wait, and Sleep. Run Mode Run mode corresponds to regular execution where the processor is running. Power consumption can be adjusted by varying the clock frequency of the processor and peripheral bus, and by en- abling or disabling individual peripheral blocks.
Page 16 SiFive E300 Platform Reference Manual, Version 1.0.1 always initially runs from the HFROSC at the default setting, and must reconﬁgure clocks to run from an alternate clock source (HFXOSC or PLL) or at a different setting on the HFROSC.
Page 17: E300 Clock Generation
The Freedom E300 platform supports many alternative clock-generation schemes to match appli- cation needs. This chapter describes the basic structure of E300 clock generation. The various clock conﬁguration registers live either in the AON block (Chapter 5) or the PRCI block (Chapter 7).
Page 18: Internal Trimmable Programmable 72 Mhz Oscillator (Hfrosc)
SiFive E300 Platform Reference Manual, Version 1.0.1 Figure 4.1 shows an overview of the E300 clock generation scheme. Most digital clocks on the chip are divided down from a central high-frequency clock hfclk produced from either the PLL or an on-chip trimmable oscillator. The PLL can be driven from either the on-chip oscillator or an off- chip crystal oscillator.
Page 19: External 16 Mhz Crystal Oscillator (Hfxosc)
Copyright c 2016, SiFive Inc. All rights reserved. To save power, the HFROSC can be disabled by clearing hfroscen. The processor must be running from a different clock source (the PLL, external crystal, or external clock) before disabling HFROSC. HFROSC can be explicitly renabled by setting hfroscen. HFROSC will be automatically re-enabled at every reset.
Page 20 =2,4,..,128 =2,4,8 =1,2,3,4 Figure 4.2: Controlling the E300 PLL output frequency. reference divider (refr) must lie between 6–12 MHz. The pllf[5:0] ﬁeld encodes the PLL VCO multiply ratio as a 6-bit binary value, , signifying a divide ratio of 2 + 1) (i.e., 000000=2, 111111=128).
Page 21: Pll Output Divider
Copyright c 2016, SiFive Inc. All rights reserved. When pllsel is clear, the hfroscclk directly drives hfclk. The pllsel bit is clear on wakeup reset. The pllcfg register is reset to: bypass and power off the PLL pllbypass=1; input driven from external HFXOSC oscillator pllrefsel=1;...
Page 22 SiFive E300 Platform Reference Manual, Version 1.0.1...
Page 23: E300 Always-On (Aon) Domain
(VCDC) bridges TileLink between the two power and clock domains. AON Reset Unit An AON reset is the widest reset on an E300 system, and resets all state except for the JTAG debug interface. An AON reset can be triggered by an on-chip power-on reset (POR) circuit when power is ﬁrst applied to the AON domain, an external active-low reset pin (erst n), or expiration of the watchdog timer (wdogrst).
Page 24: Power-On Reset Circuit
External Reset Circuit The E300 can be reset by pulling down on the external reset pin (erst n), which has a weak pullup. An external power-on reset circuit consisting of a resistor and capacitor can be to provided to generate a sufﬁciently long pulse to allow supply voltage to rise and then initiate the reset...
Page 25: Reset Cause
Copyright c 2016, SiFive Inc. All rights reserved. Reset Cause The cause of an AON reset is latched in the Reset Unit and can be read from the pmucause register in the PMU. Watchdog Timer (WDT) The watchdog timer can be used to provide a watchdog reset function, or a periodic timer interrupt.
Page 26 SiFive E300 Platform Reference Manual, Version 1.0.1 Address Description 0x1000 0000 wdogcfg Reserved 0x1000 0004 0x1000 0008 wdogcount Reserved 0x1000 000C 0x1000 0010 wdogs Watchdog Timer Registers Reserved 0x1000 0014 0x1000 0018 wdogfeed 0x1000 001C wdogkey 0x1000 0020 wdogcmp 0x1000 0040...
Page 27: E300 Power-Management Unit (Pmu)
Chapter 6 E300 Power-Management Unit (PMU) The E300 power-management unit (PMU) is implemented within the AON domain and sequences the system’s power supplies and reset signals during power-on reset and when transitioning the “mostly off” (MOFF) block into and out of sleep mode.
Page 28: Initiate Sleep Sequence Register (Pmusleep)
SiFive E300 Platform Reference Manual, Version 1.0.1 pmukey pmusleep aonrst aonrst sleep PMU State wakeup Countdown 2 Machine done delay pmuprogram sleep µPC pmucause wakeup µPC resetcause aonrst end? wakeup? pmuie Signal Condition/ Synchronize Figure 6.1: E300 Power-Management Unit. Figure 6.2: PMU instruction format.
Page 29: Wakeup Signal Conditioning
AON clock edges before being accepted. The conditioning circuit also resynchro- nizes the dwakeup signal to the AON lfclk. The awakeup analog intput is not yet supported on E300 systems. PMU Interrupt Enables (pmuie) and Wakeup Cause (pmucause) The pmuie register indicates which events can wake the MOFF block from sleep.
Page 30: Memory Map
Sleep program instruction 7 0x13c pmuie PMU interrupt enables 0x140 pmucause PMU wakeup cause 0x144 pmusleep Initiate sleep sequence 0x148 pmukey PMU key register 0x14c Table 6.4: SiFive PMU register offsets within AON memory map. Only naturally aligned 32-bit memory accesses are supported.
Page 31: E300 Power, Reset, Clock, Interrupt (Prci) Control And Status Registers
The PRCI registers are generally only made visible to machine-mode software. The AON block contains registers with similar functions, but only for the AON block units. PRCI Address Space Usage Table 7.1 shows the memory map for PRCI on SiFive systems. Address Description Clock Conﬁguration Registers...
Page 32 SiFive E300 Platform Reference Manual, Version 1.0.1...
Page 33: E300 Watchdog Timer (Wdt)
Figure 8.1: E300 Watchdog Timer. Watchdog Count Register (wdogcount) The WDT is based around a 31-bit counter held in wdogcount[30:0]. The counter can be read or written over the TileLink bus. Bit 31 of wdogcount returns a zero when read.
Page 34: Watchdog Clock Selection
SiFive E300 Platform Reference Manual, Version 1.0.1 The counter is incremented at a maximum rate determined by the watchdog clock selection. Each cycle, the counter can be conditionally incremented depending on the existence of certain condi- tions, including always incrementing or incrementing only when the processor is not asleep.
Page 35: Watchdog Compare Register (Wdogcmp)
Copyright c 2016, SiFive Inc. All rights reserved. Figure 8.3: Watchdog compare register wdogcmp li t0, 0x51F15E # Obtain key. sw t0, wdogkey # Unlock kennel. li t0, 0xD09F00D # Get some food. sw t0, wdogfeed # Feed the watchdog.
Page 36: Watchdog Interrupts (Wdogcmpip)
SiFive E300 Platform Reference Manual, Version 1.0.1 Watchdog Interrupts (wdogcmpip) The WDT can be conﬁgured to provide periodic counter interrupts by disabling watchdog re- sets (wdogrsten=0) and enabling auto-zeroing of the count register when the comparator ﬁres (wdogzerocmp=1). The sticky single-bit wdogcmpip register captures the comparator output and holds it to provide an interrupt pending signal.
Page 37: E300 Real-Time Clock (Rtc)
Chapter 9 E300 Real-Time Clock (RTC) The E300 real-time clock (RT) is located in the always-on domain, and is clocked by a se- lectable low-frequency clock source. For best accuracy, the RTC should be driven by an external 32.768 kHz watch crystal oscillator (LFXOSC), but to reduce cost, can be driven by a factory- trimmed on-chip oscillator.
Page 38: Rtc Compare Register Rtccmp
SiFive E300 Platform Reference Manual, Version 1.0.1 Figure 9.2: RTC counter register pair rtchi/rtclo Figure 9.3: RTC conﬁguration register rtccfg The 4-bit rtcscale ﬁeld scales the real-time counter value before feeding to the real-time interrupt comparator. The value in rtcscale is the bit position within the rtclo/rtchi register pair of the start of a 32-bit ﬁeld rtcs.
Page 39: E300 Backup Registers
Chapter 10 E300 Backup Registers The backup registers live in the Always-On domain, and provide a place to store critical data during sleep. Each register is 32-bits wide, and the number of backup registers is a conﬁgurable option.
Page 40 SiFive E300 Platform Reference Manual, Version 1.0.1...
Page 41: General Purpose Input/Output Controller (Gpio)
Atomic operations such as toggles are natively possible with the RISC-V ’A’ extension. Memory Map The memory map for the SiFive GPIO control registers is shown in Table 11.1. The GPIO memory map has been designed to only require naturally aligned 32-bit memory accesses.
Page 42 SiFive E300 Platform Reference Manual, Version 1.0.1 OVAL IVAL IOF0_OVAL IOF0_OE IOF_OE OVAL … IOF_OUT … IOF1_OVAL IOF1_OE … IOF_SEL IOF_EN OUT_XOR Sync VALUE IOF_IVAL HIGH_IE HIGH_IP LOW_IE LOW_IP Not Shown: Low Power Clamping Wake-on-Interrupt Logic IOF Signal Derivation RISE_IE...
Page 43: Internal Pull-Ups
0x03C out xor Output XOR (invert) 0x040 Table 11.1: SiFive GPIO Register Offsets. Only naturally aligned 32-bit memory accesses are supported. Registers marked with an are asynchronously reset to 0. All other registers are synchronously reset to 0. Once the interrupt is pending, it will remain set until a 1 is written to the * ip register at that bit.
Page 44: Behavior During Sleep Mode
SiFive E300 Platform Reference Manual, Version 1.0.1 controlled by the software registers are ﬁxed in the hardware on a per-IOF basis. Those that are not controlled by the hardware continue to be controlled by the software registers. If there is no IOFx for a pin conﬁgured with IOFx, the pin reverts to full software control.
Page 45: Universal Asynchronous Receiver/Transmitter (Uart)
Chapter 12 Universal Asynchronous Receiver/Transmitter (UART) This chapter describes the operation of the SiFive Universal Asynchronous Receiver/Transmitter (UART). UART Overview The UART peripheral supports the following features: 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start bit, 1 or 2 stop bits...
Page 46: Transmit Data Register (Txdata)
SiFive E300 Platform Reference Manual, Version 1.0.1 Transmit Data Register (txdata) Writing to the txdata register enqueues the character contained in the data ﬁeld to the transmit FIFO if the FIFO is able to accept new entries. Reading from txdata returns the current value of the full ﬂag and zero in the data ﬁeld.
Page 47: Receive Control Register (Rxctrl)
Copyright c 2016, SiFive Inc. All rights reserved. Receive Control Register (rxctrl) The read-write rxctrl register controls the operation of the receive channel. The rxen bit controls whether the Rx channel is active. When cleared, the state of the rxd pin is ignored, and no characters will be enqueued into the Rx FIFO.
Page 48 SiFive E300 Platform Reference Manual, Version 1.0.1 The input clock is the bus clock tlclk. Table 12.2 shows divisors for some common core clock rates and commonly used baud rates. Note the table shows the divide ratios, which are one greater than the value stored in the div register.
Page 49: Serial Peripheral Interface (Spi)
Chapter 13 Serial Peripheral Interface (SPI) This chapter describes the operation of the SiFive Serial Peripheral Interface (SPI) controller. SPI Overview The SPI controller supports master-only operation over the single-lane, dual-lane, and quad-lane protocols. The baseline controller provides a FIFO-based interface for performing programmed I/O.
Page 50: Serial Clock Mode Register (Sckmode)
SiFive E300 Platform Reference Manual, Version 1.0.1 Address Name Description sckdiv Serial clock divisor 0x000 sckmode Serial clock mode 0x004 csid Chip select ID 0x010 csdef Chip select default 0x014 csmode Chip select mode 0x018 delay0 Delay control 0 0x028...
Page 51: Chip Select Id Register (Csid)
Copyright c 2016, SiFive Inc. All rights reserved. Value Description Data is sampled on the leading edge of SCK and shifted on the trailing edge of SCK Data is shifted on the leading edge of SCK and sampled on the trailing edge of SCK Table 13.3: Serial clock phase.
Page 52: Delay Control Registers (Delay0 And Delay1)
SiFive E300 Platform Reference Manual, Version 1.0.1 Value Name Description AUTO Assert/de-assert CS at the beginning/end of each frame HOLD Keep CS continuously asserted after the initial frame Disable hardware control of the CS pin Table 13.4: Chip select modes.
Page 53: Transmit Data Register (Txdata)
Copyright c 2016, SiFive Inc. All rights reserved. Figure 13.8: Format of fmt register. Value Description Data Pins Single DQ0 (MOSI), DQ1 (MISO) Dual DQ0, DQ1 Quad DQ0, DQ1, DQ2, DQ3 Table 13.5: SPI protocol. Unused DQ pins are tri-stated.
Page 54: Transmit Watermark Register (Txmark)
SiFive E300 Platform Reference Manual, Version 1.0.1 The empty ﬂag indicates whether the receive FIFO contains new entries to be read; when set, the data ﬁeld does not contain a valid frame. Writes to rxdata are ignored. Figure 13.10: Format of rxdata register.
Page 55: Spi Flash Interface Control Register (Fctrl)
Copyright c 2016, SiFive Inc. All rights reserved. Figure 13.13: Format of ie and ie registers. SPI Flash Interface Control Register (fctrl) When the en bit of the fctrl register is set, the controller enters SPI ﬂash mode. Accesses to the direct-mapped memory region causes the controller to automatically sequence SPI ﬂash reads in...
Page 56 SiFive E300 Platform Reference Manual, Version 1.0.1...
Page 57: One-Time Programmable Memory (Otp) Peripheral
(OTP) Peripheral This chapter describes the operation of the One-Time Programmable Memory (OTP) Controller on SiFive systems. Device conﬁguration and power-supply control is principally under software control. The controller is reset to a state that allows memory-mapped reads, under the assumption that the controller’s clock rate is between 1 MHz and 37 MHz.
Page 58 OTP device data output 0x30 otp rsctrl OTP read sequencer control 0x34 Table 14.1: SiFive OTP Register Offsets. Only naturally aligned 32-bit memory accesses are supported. la t0, otp_lock li t1, 1 loop: sw t1, (t0) lw t2, (t0) beqz t2, loop # Programmed I/O sequence goes here.
Page 59: Programmed-I/O Sequencing
Copyright c 2016, SiFive Inc. All rights reserved. Programmed-I/O Sequencing The programmed-I/O interface exposes the OTP device’s and power-supply’s control signals di- rectly to software. Software is responsible for respecting these signals’ setup and hold times. The OTP device requires that data be programmed one bit at a time and that the result be re-read and retried according to a speciﬁc protocol.
Page 60 SiFive E300 Platform Reference Manual, Version 1.0.1...
Page 61: E300 Pulse-Width Modulation (Pwm) Peripheral
Chapter 15 E300 Pulse-Width Modulation (PWM) Peripheral This chapter describes the operation of the E300 Pulse-Width Modulation peripheral (PWM). PWM Overview Figure 15.1 shows an overview of the PWM peripheral. The default conﬁguration described here has four independent PWM comparators (pwmcmp0–pwmcmp3), but custom conﬁgurations with ncmp comparators are available on request.
Page 62: Pwm Configuration Register (Pwmcfg)
SiFive E300 Platform Reference Manual, Version 1.0.1 reset pwmoneshoten pwmcfg wurst pwmdeglitch reset pwmcount carryout pwmstickyip pwms pwmscale pwmcmp0 pwmcmp0ip >=? pwms[15] pwmcmp0gpio pwmcmp0center pwmcmp0gang pwmcmp1 >=? pwmcmp1ip pwms[15] pwmcmp1gpio pwmcmp1center pwmcmp1gang pwmcmp2 >=? pwmcmp2ip pwms[15] pwmcmp2gpio pwmcmp2center pwmcmp2gang pwmcmp3 >=?
Page 63: Pwm Compare Registers (Pwmcmp0-Pwmcmp3)
0x2C pwmcmp3 Table 15.1: SiFive PWM memory map, offsets relative to PWM peripheral base address. to replay the one-shot waveform. The pwmen* bits are reset at wakeup reset, which disables the PWM counter and saves power. The 4-bit pwmscale ﬁeld scales the PWM counter value before feeding it to the PWM comparators.
Page 64: Deglitch And Sticky Circuitry
Figure 15.4: E300 basic right-aligned PWM waveforms. All possible base waveforms are shown for a 7-clock PWM cycle (pwmcmp0=6). The waveforms show the single cycle delay caused by registering the comparator outputs in the pwmcmp ip bits. The signals can be inverted at the GPIOs to generate left-aligned waveforms.
Page 65: Generating Center-Aligned (Phase-Correct) Pwm Waveforms
Figure 15.6: E300 center-aligned PWM waveforms generated from one comparator. All possible waveforms are shown for a 3-bit PWM precision. The signals can be inverted at the GPIOs to generate opposite-phase waveforms. When a comparator is operating in center mode, the deglitch circuit allows one 0-1 transition during...
Page 66: Generating Arbitrary Pwm Waveforms Using Ganging
SiFive E300 Platform Reference Manual, Version 1.0.1 the ﬁrst half of the cycle, and one 1-0 transition on the second half of the cycle. Generating Arbitrary PWM Waveforms using Ganging A comparator can be ganged together with its next-highest-numbered neighbor to generate arbi- trary PWM pulses.