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Altima AC101 Series Manual

Ultra low power 10/100 ethernet transceiver
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AC101QF/TF Ultra Low Power 10/100
GENERAL DESCRIPTION
The AC101QF/TF is a highly integrated, 3.3V, low power,
10BASE-T/100BASE-TX/FX, Ethernet transceiver implement-
ed in 0.35 µm CMOS technology. Multiple modes of operation,
including normal operation, test mode and power saving mode,
are available through either hardware or software control.
Features include MAC interfaces, encoder/decoders (EN-
DECs), Scrambler/Descrambler, and Auto-Negotiation (ANeg)
with support for parallel detection. The transmitter includes a
dual-speed clock synthesizer that only needs one external clock
source (crystal or clock oscillator). The chip has built-in wave
shaping driver circuit for both 10 Mbps and 100 Mbps, eliminat-
ing the need for an external hybrid filter. The receiver has an
adaptive equalizer/DC restoration circuit for accurate clock and
data recovery for the 100BASE-TX signal. It also provides an
on-chip low pass filer/Squelch circuit for the 10BASE-T signal.
MAC interfaces to support 10/100 MII, 100M only Symbol
Mode, 10M only Symbol Mode and 10M only 7 wire interface
are included.
The AC101TF and the AC101QF are the same product in differ-
ent packages.
MII Data
Interface
MAC
or
RIC
MII Serial
Mgmt
Interface
16215 Alton Parkway • P.O. Box 57013 • Irvine, CA 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710
PCS
PMA
o Framer
o Clk Recov
o Carrier
o Link Mon
Detect
o Signal Det
o 4B/5B
Interface
10BASE-T
Control/Status
MII Serial Management
Interface and Registers
Test/LED Control
PHYAD[4:0]
XTLP/N CKIN TEST[3:0] LED Drivers
Figure 1: Functional Block Diagram
PRELIMINARY DATA SHEET
AC101
Ethernet Transceiver
FEATURES
•
MII MAC connection
- 5 Volt tolerant and 2.5 Volt capable
•
10/100 TX/FX
- Full-duplex or half-duplex
- FEFI on 100FX
•
Two packages: 80TQFP and 100PQFP
•
Industrial temperature: -40°C to +85°C
•
Very low power – TYP < 280 mW (Total)
- Cable Detect mode – TYP < 40 mW (Total)
- Power Down mode – TYP < 3.3 mW (Total)
- Selectable TX drivers for 1:1 or 1.25:1 transformers for
additional power reduction
•
3.3 Volt .35 micron CMOS
•
Fully compliant with
- IEEE 802.3/802.3u
- MII
•
Baseline Wander Compensation
•
Multi-Function LED outputs
•
Legacy 10BASE-T 7 wire interface
•
100M Symbol Mode/10M Symbol Mode
•
Cable length indicator
•
Reverse polarity detection and correction with register bit
indication – automatic or forced
•
8 programmable interrupts
•
Diagnostic registers
TP_PMD
100TX
o MLT-3
o BLW
o Stream
100RX
Cipher
10TX
10RX
20 MHz
PLL Clk Gen
25 MHz
Negotiation
TXOP/TXON
RXIP/RXIN
Mux
FXTP/FXTN
FXRP/FXRN
RX
FLP
Auto-
AC101-DS01-405-R¥¥¥¥¥
06/04/01

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Summary of Contents for Altima AC101 Series

  • Page 1 PRELIMINARY DATA SHEET AC101 AC101QF/TF Ultra Low Power 10/100 Ethernet Transceiver GENERAL DESCRIPTION FEATURES The AC101QF/TF is a highly integrated, 3.3V, low power, • MII MAC connection 10BASE-T/100BASE-TX/FX, Ethernet transceiver implement- - 5 Volt tolerant and 2.5 Volt capable ed in 0.35 µm CMOS technology. Multiple modes of operation, •...
  • Page 2 A Wholly Owned Subsidiary of Broadcom Corporation P.O. Box 57013 16215 Alton Parkway Irvine, CA 92619-7013 © 2001 by Altima Communications, Inc. All rights reserved Printed in the U.S.A. ® Broadcom , the pulse logo, and QAMLink are registered trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries.

  • Page 3: Table Of Contents

    Preliminary Data Sheet AC101 06/04/01 ABLE OF ONTENTS Section 1: Functional Description..................1 Overview ............................... 1 MAC Interface ............................... 1 Media Independent Interface (MII) ......................1 Serial Management Interface (SMI) ....................1 Interrupts............................2 Carrier Sense/RX_DV........................2 7-Wire Serial Interface ..........................2 PCS Bypass ............................

  • Page 4: Able Of

    AC101 Preliminary Data Sheet ABLE OF ONTENTS 06/04/01 PLL Clock Synthesizer ........................7 Jabber and SQE (Heartbeat)......................7 Reverse Polarity Detection and Correction ..................7 Hardware Configuration...........................7 Software Configuration ..........................7 LED Outputs............................. 7 Auto-Negotiation............................8 Parallel Detection ............................ 9 Diagnostics .............................. 9 Loopback Operation .........................
  • Page 5 Register 5: Auto-Negotiation Link Partner Ability Register..............27 Register 6: Auto-Negotiation Expansion Register................. 28 Register 7: Auto-Negotiation Next Page Transmit Register..............28 Altima-Specified Registers........................29 Register 16: Polarity and Interrupt Level Register ................29 Register 17: Interrupt Control/Status Register ..................30 Register 18: Diagnostic Register ......................
  • Page 6 AC101 Preliminary Data Sheet ABLE OF ONTENTS 06/04/01 10BASE-T MII Transmit System Timing....................42 10BASE-T MII Receive System Timing....................44 10BASE-T 7-Wire Transmit System Timing ..................45 10BASE-T 7-Wire Receive System Timing ...................46 10BASE-T 7-Wire Collision Timing......................46 Recommended Board Circuitry.........................47 TX Application Termination ........................47 FX Application Termination ........................48 Power and Ground Filtering for AC101QF ....................49 Power and Ground Filtering for AC101TF .....................50...
  • Page 7 Preliminary Data Sheet AC101 06/04/01 IST OF IGURES Figure 1: Functional Block Diagram .........................i Figure 2: Multifunction LED Pin Connection....................19 Figure 3: Dual-color LED Indicator for Link, Duplex, and Activity Status ............. 20 Figure 4: AC101QF Pinout Diagram ......................21 Figure 5: AC101TF Pinout Diagram ......................
  • Page 8 AC101 Preliminary Data Sheet IST OF IGURES 06/04/01 Br oad com Page viii Document AC101-DS01-405-R¥¥¥¥¥...
  • Page 9 Preliminary Data Sheet AC101 06/04/01 IST OF ABLES Table 1: PHY Address Pins......................... 11 Table 2: MDI (Media Dependent) Pins......................11 Table 3: MII (Media Independent Interface) 100 PCS Bypass Pins............12 Table 4: 10 Mbps PCS Bypass Pins ......................13 Table 5: 10 Mbps 7-Wire Interface Pins......................
  • Page 10 AC101 Preliminary Data Sheet IST OF ABLES 06/04/01 Table 33: REFCLK and XTAL Pin Characteristics ..................36 Table 34: I/O Characteristics – LED/CFG Pin Characteristics ..............36 Table 35: 100BASE-TX Transceiver Characteristics..................36 Table 36: 10BASE-T Transceiver Characteristics ..................37 Table 37: 100BASE-FX Transceiver Characteristics..................37 Table 39: Power On Reset Timing ........................39 Table 40:...

  • Page 11: Section 1: Functional Description

    Preliminary Data Sheet AC101 06/04/01 S e c ti o n 1 : Fu nc t io na l D e s c r i pt i on VERVIEW The AC101TF/QF PHYsical layer device (PHY) integrates the 100BASE-X and 10BASE-T functions in a single chip that is used in Fast Ethernet 10/100 Mbps applications.

  • Page 12: Interrupts

    AC101 Preliminary Data Sheet 06/04/01 Independent Interface) 100 PCS Bypass Pins” on page 12). MDC is a clock input to the PHY which is used to latch in or out data and instructions for the PHY. The clock can run at any speed from DC to 25 MHz. MDIO is a bi-directional connection used to write instructions to, write data to, or read data from the PHY.

  • Page 13: Pcs Bypass

    Preliminary Data Sheet AC101 06/04/01 PCS B YPASS The AC101TF/QF is put into PCS bypass mode when the PCSBP pin is pull high (see ”Control and Status Pins” on page 14). 100 Mbps PCS Bypass In MII designs, the encoding/decoding functions are performed in the PHY, thereby allowing 4-bit data exchange. Certain designs, however, require MAC/PHY data transfer to be in the form of 5-bit symbols.

  • Page 14: Transmit Function

    AC101 Preliminary Data Sheet 06/04/01 Transmit Function In 100BASE-TX mode, the PHY transmit function converts synchronous 4-bit data nibbles from the MII to a pair of 125 Mbps differential serial data streams. The serial data is transmitted over network twisted pair cables via an isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel to serial, NRZ to NRZI, and MLT-3 encoding.

  • Page 15: Baseline Wander Compensation

    Preliminary Data Sheet AC101 06/04/01 Baseline Wander Compensation The 100BASE-TX data stream is not always DC balanced. The transformer blocks the DC components of the incoming sig- nal, thus the DC offset of the differential receive inputs can drift. The shifting of the signal level, coupled with non-zero rise and fall times of the serial stream can cause pulse-width distortion.

  • Page 16: 100Base-Fx Interface

    AC101 Preliminary Data Sheet 06/04/01 100BASE-FX I NTERFACE When configured to run in 100BASE-FX mode, either through hardware configuration or software configuration (100BASE- FX does not support ANeg) the PHY will support all the features and parameters of the industry standards. Transmit Function The serialized data bypasses the scrambler and 4B/5B encoder in FX mode.

  • Page 17: Adaptive Equalizer

    Preliminary Data Sheet AC101 06/04/01 Adaptive Equalizer The PHY is designed to accommodate a maximum of 150 meters UTP CAT-5 cable. An AT&T 1061 CAT-5 cable of this length typically has an attenuation of 31 dB at 100 MHz. A typical attenuation of 100-meter cable is 21 dB. The worst case cable attenuation is around 24-26 dB as defined by TP-PMD specification.

  • Page 18: Auto-Negotiation

    AC101 Preliminary Data Sheet 06/04/01 put states. If a multi-function pin is pulled up during reset to select a particular function, then that LED output would become active low, and the LED circuit must be designed accordingly, and vice versa. In addition to the individual LED configurations, an advanced LED circuit has been implemented, as illustrated in ”Advanced LED Selections”...

  • Page 19: Parallel Detection

    Preliminary Data Sheet AC101 06/04/01 The technology priorities are: 100BASE-TX, full-duplex 100BASE-TX, half-duplex 10BASE-T, full-duplex 10BASE-T half-duplex Once the ANeg is complete, Reg. 1.5 is set, Reg. 1.[14:11] reflects negotiated speed and duplex mode, and the PHY enters the negotiated transmission and reception state. This state will not change until link is lost or the PHY is reset through either hardware or software, or the restart negotiation bit (Reg.

  • Page 20: Reset And Power

    AC101 Preliminary Data Sheet 06/04/01 ESET AND OWER The PHY can be reset in three ways: During initial power on. Hardware Reset: (See pin descriptions). Software Reset: (See register descriptions). The power consumption of the device is significantly reduced due to its built-in power management features. Separate power supply lines are used to power the 10BaseT circuitry and the 100BaseTX circuitry.

  • Page 21: Section 2: Signal Definitions And Pin Assignments

    Preliminary Data Sheet AC101 06/04/01 S e c t i on 2: Si g na l D e f i n it i o ns a nd P i n A s s i g n- ments Many of the pins of these devices have multiple functions. The multi-function pins will be designated by bolding of the pin number.

  • Page 22: Mii (Media Independent Interface) 100 Pcs Bypass Pins

    AC101 Preliminary Data Sheet 06/04/01 Table 2: MDI (Media Dependent) Pins (Cont.) Pin Name 101TF 101QF Type Description FXRN AO/AI Receive input positive and negative for 100BASE-FX when FX_DIS pin is pulled low. FXRP AO/AI FXTP Transmit output positive and negative for 100BASE-FX when FX_DIS pin is pulled low.

  • Page 23: Mbps Pcs Bypass Pins

    Preliminary Data Sheet AC101 06/04/01 Table 3: MII (Media Independent Interface) 100 PCS Bypass Pins (Cont.) Pin Name 101TF 101QF Type Description TXD [3] Transmit Data. The MAC will source TXD[3:0] synchronous with TX_CLK when TX_EN is asserted. TXD [2] TXD [1] PCS Bypass TXD[3:0] TXD [0]...

  • Page 24: Special/Test Pins

    AC101 Preliminary Data Sheet 06/04/01 PECIAL Table 6: Special/Test Pins Pin Name 101TF 101QF Type Description CLK25 CLK25 provides a continuous 25 MHz clock if CLK25EN is asserted dur- ing reset. Reserved I, D TEST0 AO/AI TEST [3:0] pins are used as the test-mode output monitor pin. Internal pull-down in normal 100BASE-TX or 10BASE-T mode.
  • Page 25 Preliminary Data Sheet AC101 06/04/01 Table 7: Control and Status Pins (Cont.) Pin Name 101TF 101QF Type Description TECH [2] I, U Technology Select. /DUPLEX • When ANEGA pin is set to high, TECH[2:0] will then set the negotia- ble capabilities. (See ”Technology Selections” on page 18.) •...

  • Page 26: Led Indicators Pins

    AC101 Preliminary Data Sheet 06/04/01 LED I NDICATORS Table 8: LED Indicator Pins Pin Name 101TF 101QF Type Description LEDBTX* I/O, U LEDBTX - 100BASE-X LED. Active low indicates 100BASE-TX, active high indicates 10BaseT. LEDBTA LEDBTA - This pin is to be used in conjunction with LEDBTB pin that drives a 10BASE-T status LED.

  • Page 27: Power And Ground Pins

    Preliminary Data Sheet AC101 06/04/01 Table 8: LED Indicator Pins (Cont.) Pin Name 101TF 101QF Type Description LEDBT* I/O, U LEDBT - 100BASE-X LED output. Active low indicates 10BaseT, high in- dicates 100BASE-TX. LEDTXA LEDTXA - This pin is to be used in conjunction with LEDTXB pin that drives a 100B-T status LED.

  • Page 28: No Connect Pins

    AC101 Preliminary Data Sheet 06/04/01 ONNECT Table 10: No Connect Pins Pin Name 101TF 101QF Type Description 1, 2, 3, 4, 5, No Connect pin 26, 27, 28, 29, 30, 51, 52, 53, 54, 55, 76, 77, 78, 79, 80 ECHNOLOGY ELECTIONS Table 11: Technology Solutions...

  • Page 29: Advanced Led Selections

    Preliminary Data Sheet AC101 06/04/01 LED S DVANCED ELECTIONS Table 12: Advanced LED Selections 10BASE-T LED 100BASE-TX LED Condition LEDBTA LEDBTB LED color LEDTXA LEDTXB LED color No Link 10B-T HDX Link Yellow 10B-T HDX RX Flashing Yellow 10B-T FDX DX Link Green 10B-T FDX RX Flashing...

  • Page 30: Figure 3: Dual-Color Led Indicator For Link, Duplex, And Activity Status

    AC101 Preliminary Data Sheet 06/04/01 A suggested LED connection diagram is shown in Figure 3 that could simplify the board design. LEDTXA LEDBTA Green Yellow Green Yellow LEDTXB LEDBTB 100Base-TX 10Base-T Figure 3: Dual-color LED Indicator for Link, Duplex, and Activity Status Br oad com Page 20 Technology Selections...

  • Page 31: Section 3: Pinout Diagrams

    Preliminary Data Sheet AC101 06/04/01 Sec tion 3 : Pinout Diagrams AC101QF P INOUT IAGRAM RPTR TXD[3] TEST3/SDP TXD[2] RXIN TXD[1] RXIP TXD[0]/10TD GNDEQ CVDD NC/TEST0/FXRN CGND NC/TEST1/FXRP TX_EN/10TXEN TEST2 TX_CLK/10TCLK/CLK20 NC/FXTP TXER/TXD[4] NC/FXTN RXER/RXD[4] GNDREF AC101QF RX_CLK/SYM_RCLK/10RCLK RIBB RX_DV VAAREF CGND XTLN...

  • Page 32: Ac101Tf Pinout Diagram

    AC101 Preliminary Data Sheet 06/04/01 AC101TF P INOUT IAGRAM TXD[3] RPTR TXD[2] TEST3/SDP TXD[1] RXIN TXD[0]/10TD RXIP CVDD GNDEQ CGND NC/TEST0/FXRN TX_EN/10TXEN NC/TEST1/FXRP TX_CLK/10TCLK/CLK20 TEST2 TXER/TXD[4] NC/FXTP AC101TF RXER/RXD[4] NC/FXTN RX_CLK/SYM_RCLK/10RCLK GNDREF RX_DV RIBB CGND VAAREF CVDD XTLN RXD[0]/10RD XTLP RXD[1] GNDT RXD[2]...

  • Page 33: Section 4: Register Descriptions

    The first eight registers of the MII register set are defined by the MII specification. In addition to these required registers are several Altima-specific registers. There are reserved registers and/or bits that are for Altima internal use only. (Register num- bers are in Decimal format, the values are in Hex format).

  • Page 34: Mii-Specified Registers

    AC101 Preliminary Data Sheet 06/04/01 Table 13: Register Summary (Cont.) Register Description Default Reserved XXXX Reserved 0000 Receive Error Counter Register 0000 25-31 Reserved XXXX MII-S PECIFIED EGISTERS 0: C EGISTER ONTROL EGISTER Table 14: Register 0: Control Register Reg.bit Name Description Mode...

  • Page 35: Register 1: Status Register

    Preliminary Data Sheet AC101 06/04/01 Table 14: Register 0: Control Register (Cont.) Reg.bit Name Description Mode Default Collision Test • 1 = Enable collision test, which issues the COL signal in re- sponse to the assertion of TX_EN signal (see ”MII (Media In- dependent Interface) 100 PCS Bypass Pins”...

  • Page 36: Register 2: Phy Identifier 1 Register

    AC101 Preliminary Data Sheet 06/04/01 Table 15: Register 1: Status Register (Cont.) Reg.bit Name Description Mode Default Extended Ca- 1 = Extended register capable. This bit is tied permanently to pability one. 2: PHY I EGISTER DENTIFIER EGISTER Table 16: Register 2: PHY Identifier 1 Register Reg.bit Name Description...

  • Page 37: Register 5: Auto-Negotiation Link Partner Ability Register

    Preliminary Data Sheet AC101 06/04/01 Table 18: Register 4: Auto-Negotiation Advertisement Register (Cont.) Reg.bit Name Description Mode Default 100BASE-TX • 1 = 100BaseTX full-duplex capable. TECH [2:0] Full-duplex • 0 = Not 100BaseTX full-duplex capable. 100BASE-TX • 1 = 100BaseTX half-duplex capable. TECH [2:0] •...

  • Page 38: Register 6: Auto-Negotiation Expansion Register

    AC101 Preliminary Data Sheet 06/04/01 6: A EGISTER EGOTIATION XPANSION EGISTER The ANeg Complete bit of Register 1: Status Register (see ”Register 1: Status Register” on page 25) must be set for this register to be valid. Table 20: Register 6: Auto-Negotiation Expansion Register Reg.bit Name Description...

  • Page 39: Altima-Specified Registers

    Preliminary Data Sheet AC101 06/04/01 LTIMA PECIFIED EGISTERS 16: P EGISTER OLARITY AND NTERRUPT EVEL EGISTER Table 22: Register 16: Polarity and Interrupt Level Register Reg.bit Name Description Mode Default 16.15 Repeater • 1= Repeater mode, full-duplex will be inactive, and CRS Set by RPTR only responses to receive activity.

  • Page 40: Register 17: Interrupt Control/Status Register

    AC101 Preliminary Data Sheet 06/04/01 17: I EGISTER NTERRUPT ONTROL TATUS EGISTER Table 23: Register 17: Interrupt Control/Status Register Reg.bit Name Description Mode Default 17.15 Jabber_IE Jabber Interrupt Enable. 17.14 Rx_Er_IE Receive Error Interrupt Enable. 17.13 Page_Rx_IE Page Received Interrupt Enable. 17.12 PD_Fault_IE Parallel Detection Fault Interrupt Enable.

  • Page 41: Register 19: Power/Loopback Register

    Preliminary Data Sheet AC101 06/04/01 Table 24: Register 18: Diagnostic Register (Cont.) Reg.bit Name Description Mode Default 18.[7:0] Reserved 19: P EGISTER OWER OOPBACK EGISTER Table 25: Register 19: Power/Loopback Register Reg.bit Name Description Mode Default 19.[14:7] Reserved Reserved 19.6 TP125 Transmit transformer ratio selection.

  • Page 42: Register 21: Mode Control Register

    AC101 Preliminary Data Sheet 06/04/01 21: M EGISTER ONTROL EGISTER Table 27: Register 21: Mode Control Register Reg.bit Name Description Mode Default 21.15 Reserved 21.14 NLP Disable • 1 = Force 10B-T link up without checking NLP. • 0 = Normal Operation. 21.13 Force_link_up •...

  • Page 43: Register 24: Receive Error Counter Register

    Preliminary Data Sheet AC101 06/04/01 Table 27: Register 21: Mode Control Register (Cont.) Reg.bit Name Description Mode Default 21.0 FX_SEL • 1 = FX mode selected. Set by FX_DIS • 0 = Disable FX mode. 24: R EGISTER ECEIVE RROR OUNTER EGISTER Table 28: Register 24: Receive Error Counter Register...

  • Page 44: Smi Read/Write Sequence

    AC101 Preliminary Data Sheet 06/04/01 Table 29: 4B/5B Code-Group Table (Cont.) PCS Code Group MII (TXD/RXD [3:0]) SYMBOL Name Description [4 3 2 1 0] [3 2 1 0] 10001 0101 Start of stream delimiter, part 2 of 2; always use in pair with J symbol.

  • Page 45: Section 5: Electrical Characteristics

    Preliminary Data Sheet AC101 06/04/01 Se ction 5: Electr ic al C ha rac te ristics The following electrical characteristics are design goals rather than characterized numbers. Note PERATING ANGE • Operating Temperature (Ta) C to +85 • Vcc Supply Voltage Range (Vcc) 2.97V to 3.63V •...

  • Page 46: Refclk And Xtal Pin Characteristics

    AC101 Preliminary Data Sheet 06/04/01 REFCLK XTAL P HARACTERISTICS Table 33: REFCLK and XTAL Pin Characteristics Parameter Symbol Conditions Units Input Voltage Low Input Voltage High Input Clock Frequency ±50 Tolerance Input Clock Duty Cycle Input Capacitance I/O C – LED/CFG P HARACTERISTICS HARACTERISTICS Table 34: I/O Characteristics –...

  • Page 47: 10Base-T Transceiver Characteristics

    Preliminary Data Sheet AC101 06/04/01 Table 35: 100BASE-TX Transceiver Characteristics (Cont.) Parameter Symbol Conditions Units Common Mode Input Voltage Common Mode Input Current Differential Input Resis- KΩ tance Note 1: 50Ω (± 1%) resistor to VCC on each output. 10BASE-T T RANSCEIVER HARACTERISTICS Table 36: 10BASE-T Transceiver Characteristics...

  • Page 48: 10Base-T Link Integrity Timing Characteristics

    AC101 Preliminary Data Sheet 06/04/01 Table 37: 100BASE-FX Transceiver Characteristics (Cont.) Parameter Symbol Conditions Units Differential Output Volt- Note 1 age Low Signal Rise/Fall Time Output Jitter Differential Output Volt- age High Differential Output Volt- age Low Output Current Sink Note 1: 69Ω...

  • Page 49: Section 6: Timing And Ac Characteristics

    Preliminary Data Sheet AC101 06/04/01 Se ction 6: Timing and AC Char acte ristics IGITAL IMING HARACTERISTICS OWER ON ESET IMING Table 39: Power On Reset Timing Parameter Conditions Units µs RST* Low Period tRST Configuration tCONF tRST RST* tCONF Configuration Pins Figure 6: Power-on Reset Timing...

  • Page 50: 100Base-Tx/Fx Mii Transmit System Timing

    AC101 Preliminary Data Sheet 06/04/01 tMDCH tMDCL MDIO Figure 7: Management Data Interface Timing 100BASE-TX/FX MII T RANSMIT YSTEM IMING Table 41: 100BASE-TX/FX MII Transmit System Timing Parameter Conditions Units TX_CLK period 39.998 40.000 40.002 TX_CLK High period tCKH 18.000 20.000 22.000 TX_CLK Low period...

  • Page 51: 100Base-Tx/Fx Mii Receive System Timing

    Preliminary Data Sheet AC101 06/04/01 Start of Packet End of Packet tCKH tCKL TX_CLK tTX_TX tTXS TX_EN tTXH TXD[3:0] TX_ER TXOP/N FXTP/N tTCSA tTCSD tTCLA tTCLD Figure 8: 100BASE-TX/FX MII Transmit Timing 100BASE-TX/FX MII R ECEIVE YSTEM IMING Table 42: 100BASE-TX/FX MII Receive System Timing Parameter Conditions Units...

  • Page 52: 10Base-T Mii Transmit System Timing

    AC101 Preliminary Data Sheet 06/04/01 Table 42: 100BASE-TX/FX MII Receive System Timing (Cont.) Parameter Conditions Units RXD[3:0], RX_DV, tRXH From rising edge of RX_CLK RX_ER Hold Start of Packet End of Packet tCKH tCKL RX_CLK tRDVA tRDVD RX_DV tRXS tRXH RXD[3:0] RX_ER RX_DV...

  • Page 53: Figure 10: 10Base-T Mii Transmit Timing

    Preliminary Data Sheet AC101 06/04/01 Table 43: 10BASE-T MII Transmit System Timing (Cont.) Parameter Conditions Units TX_EN sampled to tTCLA RPTR is logic low !TX_EN to EOP !TX_EN sampled to tTCSD RPTR is logic low !CRS !TX_EN sampled to tTCLD RPTR is logic low !COL TX Propagation Delay...

  • Page 54: 10Base-T Mii Receive System Timing

    AC101 Preliminary Data Sheet 06/04/01 10BASE-T MII R ECEIVE YSTEM IMING Table 44: 10BASE-T MII Receive System Timing Parameter Conditions Units RX_CLK period 399.98 400.00 400.02 RX_CLK High period tCKH 180.00 200.00 220.00 RX_CLK Low period tCKL 180.00 200.00 220.00 CRS to RX_DV tRDVA SOP to CRS...

  • Page 55: 10Base-T 7-Wire Transmit System Timing

    Preliminary Data Sheet AC101 06/04/01 10BASE-T 7-W RANSMIT YSTEM IMING Table 45: 10BASE-T 7-Wire Transmit System Timing Parameter Conditions Units 10TCLK period 99.995 100.00 100.005 10TCLK High period tCKH 45.00 50.00 55.00 10TCLK Low period tCKL 45.00 50.00 55.00 10TXEN to SOP 10TXEN sampled to tTCSA RPTR is logic low...

  • Page 56: 10Base-T 7-Wire Receive System Timing

    AC101 Preliminary Data Sheet 06/04/01 10BASE-T 7-W ECEIVE YSTEM IMING Table 46: 10BASE-T 7-Wire Receive System Timing Parameter Conditions Units 10RCLK period 99.995 100.00 100.005 10RCLK High period tCKH 45.00 50.00 55.00 10RCLK Low period tCKL 45.00 50.00 55.00 SOP to 10CRS tRCSA 10CRS to 10RD tRDVA...

  • Page 57: Recommended Board Circuitry

    10COL Figure 14: 10BASE-T 7-Wire Collision Timing ECOMMENDED OARD IRCUITRY TX A PPLICATION ERMINATION Please contact Altima Communications Inc. for the latest component value recommendation. 3.3V 0.1 µ F AC101-TF/QF RJ45 Transformer 1 TX+ TXON TXC_P TXC_S 2 TX-...

  • Page 58: Fx Application Termination

    FX A PPLICATION ERMINATION Please contact Altima Communications Inc. for the latest component value recommendation. To enable the FX mode, FX_DIS pin (see ”LED Indicators Pins” on page 16) must be pulled low by a 1 kilohm resistor. 3.3V HFBR-5903...

  • Page 59: Power And Ground Filtering For Ac101Qf

    Preliminary Data Sheet AC101 06/04/01 Power and Ground Filtering for AC101QF Please contact Altima Communications Inc. for the latest component value recommendation. Components placed < 3mm from pin VCC Via VAAEQ 75 VAAADP 74 GND Via 9 GNDT 15 VAAPLL...

  • Page 60: Power And Ground Filtering For Ac101Tf

    AC101 Preliminary Data Sheet 06/04/01 AC101TF OWER AND ROUND ILTERING FOR Please contact Altima Communications Inc. for the latest component value recommendations. Components placed < 3mm from pin . 1u VCC Via GND Via . 1u . 1u . 1u...

  • Page 61: Section 7: Mechanical Information

    Preliminary Data Sheet AC101 06/04/01 S e c t i o n 7 : M e c h a n ic a l I n f or m a t i on AC101QF (100 PQFP) ACKAGE IMENSIONS FOR Table 48: Quad Flat Pack Outline: 20 x 14 mm 2.70 ±...

  • Page 62: Package Dimensions For Ac101Tf (80 Pin Tqfp)

    AC101 Preliminary Data Sheet 06/04/01 AC101TF (80 TQFP) ACKAGE IMENSIONS FOR Table 49: Quad Flat Pack Outline: 12 x 12 mm 1.00 ± 0.22 ± 14.20 ± 12.00 ± 1.20 0.05 14.20 ± 12.00 ± 0.50 0.60 ± 1.00 ± 0.05 0.05 0.25...
  • Page 63 Preliminary Data Sheet AC101 06/04/01 Br oad com Document AC101-DS01-405-R¥¥¥¥¥ Page 53...
  • Page 64 AC101 Preliminary Data Sheet 06/04/01 Altima Communications, Inc. A Wholly Owned Subsidiary of Broadcom Corporation 16215 Alton Parkway P.O. Box 57013 Irvine, CA 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710 Broadcom Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.

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