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Connecting the Switch to the Network
Figure 11: The Cisco Nexus 3550-T Triton FPGA transceiver layout
Connecting Interface Ports to Other Devices
There is a high speed PCIe interface between the Atom x86 CPU and FPGA module, which is capable of
approximately 50Gb/s when configured in Gen3 x8 mode. Please refer to the UltraScale+ Device Integrated
Block for PCI Express PG-213.
High-Bandwidth Memory
There is 8 GB of High-Bandwidth Memory (HBM2) integrated in the FPGA for applications requiring high
density and high bandwidth (up to 460GB/s). This can be accessed using the Xilinx Integrated Memory
Interface HBM IP. Please refer to the AXI High Bandwidth Memory Controller v1.0
information.
Connecting Interface Ports to Other Devices
Cisco Nexus 3550-T Hardware Installation Guide
PG-276
for more
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