Page 1 Embedded Computing for Business-Critical Continuity CPCI-6200 Installation and Use P/N: 6806800J66C August 2011...
Page 2 Emerson reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Emerson to notify any person of such revision or changes.
Page 3: Table Of Contents
Connectors and Headers ............47 CPCI-6200 Installation and Use (6806800J66C)
Page 4 Timers ................75 CPCI-6200 Installation and Use (6806800J66C)
Page 5 Overview ................95 CPCI-6200 Installation and Use (6806800J66C)
Page 6 Emerson Specific Commands ........
Page 7 CPCI-6200 Memory Map ........
Page 8 Related Documentation ............. . 181 Emerson Network Power - Embedded Computing Documents ......181 Manufacturer’s Publications .
Page 9 CPCI-6200 Environmental Requirements ........
Page 10 FRU Information CPCI-6200 ........
Page 11 CPCI-6200 Address Memory Map ........
Page 12 Related Specifications ............183 CPCI-6200 Installation and Use (6806800J66C)
Page 13 CPCI-6200 Clock Distribution Diagram ........
Page 14 List of Figures CPCI-6200 Installation and Use (6806800J66C)
Page 15: About This Manual
 Sicherheitshinweise lists the German version of the safety notes.  Abbreviations This document uses the following abbreviations: Abbreviation Definition ANSI American National Standard Institute Base Board Management Controller Chip Enable Communications CPCI-6200 Installation and Use (6806800J66C)
Page 16 Intelligent Platform Management Bus IPMC Intelligent Platform Management Interface Controller IPMI Intelligent Platform Management Interface Inter Integrated Circuit JTAG Joint Test Access Group Local Bus Controller Linear Feet per Minute Least Significant Byte Multi Purpose Unit CPCI-6200 Installation and Use (6806800J66C)
Page 17 Single Board Computer Sensor Data Record SDRAM Synchronous Dynamic Random Access Memory System Event Log SMBus System Management Bus Surface Mount Technology SO-DIMM Small-Outline Dual In-line Memory Module SO-UDIMM Small-Outline Unbuffered Dual In-line Memory Module CPCI-6200 Installation and Use (6806800J66C)
Page 18 File > Exit Notation for selecting a submenu <text> Notation for variables and keys [text] Notation for software buttons to click on the screen and parameter description Repeated item for example node 1, node 2, ..., node CPCI-6200 Installation and Use (6806800J66C)
Page 19 This manual has been revised and replaces all prior editions. Part Number Publication Date Description 6806800J66C August 2011 Updated Appendix P, Safety Notes, on page 185 6806800J66B December 2010 Updated MOTLoad Command List on page 100 6806800J66A September 2009 First edition CPCI-6200 Installation and Use (6806800J66C)
Page 20 About this Manual About this Manual CPCI-6200 Installation and Use (6806800J66C)
Page 21: Introduction
Chapter 1 Introduction Features The CPCI-6200 is a high performance, hot swappable universal Compact PCI board based on the MPC8572 integrated processor. Table 1-1 Summary of Features Function Features Processor One 8572 integrated processor  Host Controller Two e500 cores with integrated 1 MB L2 cache ...
Page 22 8-channel analog/digital converter  Three serial ports  512 KB flash  40 KB SRAM  1 MB (64K x 16 bit) external SRAM  External user EEPROM, SDR/FRU, SEL flash of 512 KB each  CPCI-6200 Installation and Use (6806800J66C)
Page 23 User/Fail LED on the face plate   Blue hot swap LED on the face plate One standard 16-pin JTAG/COP header  Support for boundary scan  Software Support VxWorks  Linux  Compatible with RTM-CPCI-6115 (01-W3766F11A) CPCI-6200 Installation and Use (6806800J66C)
Page 24: Standard Compliances
Introduction Standard Compliances The CPCI-6200 is designed to be CE compliant and to meet the following standard requirements. Standard Description UL 60950-1 Safety Requirements (legal) EN 60950-1 IEC 60950-1 CAN/CSA C22.2 No 60950-1 CISPR 22 EMC requirements (legal) on system level...
Page 25: Figure 1-1 Declaration Of Conformity
Introduction Figure 1-1 Declaration of Conformity CPCI-6200 Installation and Use (6806800J66C)
Page 26: Mechanical Data
Introduction Mechanical Data The CPCI-6200 is a full 6U 18-layer board. It is designed with ruggedization holes to support ruggedization application. This board occupies a single CPCI card slot with PMC modules installed. Ordering Information Use the information in the following sections when ordering boards and accessories.
Page 27: Product Identification
Introduction Product Identification Figure 1-2 Location of the Product Serial Number Serial Number Label CPCI-6200 Installation and Use (6806800J66C)
Page 28 Introduction CPCI-6200 Installation and Use (6806800J66C)
Page 29: Hardware Preparation And Installation
Hardware Preparation and Installation Overview This chapter provides instructions on preparing and installing the CompactPCI board. A fully implemented CPCI-6200 consists of the baseboard, PMC modules, and an optional rear transition module. Unpacking the CPCI Baseboard 1. Make sure that you receive all items of your shipment: Printed Quick Start Guide and Safety Notes ...
Page 30: Environmental Requirements
High humidity and condensation on surfaces cause short circuits. Do not operate the product outside the specified environmental limits. Make sure the product is completely dry and there is no moisture on any surface before applying power. Table 2-1 CPCI-6200 Environmental Requirements Characteristics Operating...
Page 31: Power Requirements
Hardware Preparation and Installation Table 2-1 CPCI-6200 Environmental Requirements (continued) Characteristics Operating Non-Operating Shock Half-sine, 11 ms, 30 ms Blade-level packaging Half-sine, 6 ms at 180 ms Free Fall Blade-level packaging 100 mm (unpackaged) per GR-63- CORE Power Requirements The board's power requirements depend on the installed hardware accessories. The following table gives examples of typical power requirements for a processor running without any accessories.
Page 32: Installing Accessories
Installing a PMC Module on the CPCI Baseboard One double-width or two single-width PCI mezzanine cards (PMC) can be mounted on the CPCI-6200 baseboard. Each PMC slot has four connectors that provide a PCI interface to two PMC slots that provide user I/O to the backplane.
Page 33 PMC Alignment PMC Filler Plate Voltage Key 5. Make sure that hole on the PMC matches the voltage key on CPCI-6200. Do not remove the PMC voltage key. CPCI-6200 supports only 3.3 V I/O PMC modules. 6. Slide the edge connector of the PMC module into the front panel opening from behind, and then place the PMC module on top of the baseboard.
Page 34: Installing The Rear Transition Module
2.6.1 Inspecting the CPCI Baseboard You can use the CPCI-6200 as a system controller in a system slot, an intelligent I/O board in a peripheral slot, or in stand-alone mode. The board is fully compliant to CompactPCI Hot Swap Specification PICMG 2.1 R2.0, and can run in both 3.3 V and 5 V CompactPCI system.
Page 35: Equipment Required For Installation
Most options on the board are configured by software. Configuration changes are made by setting the bits in control registers after the board is installed in a system. The control registers are described in Memory Maps and Addresses on page 137 and other vendor publications. CPCI-6200 Installation and Use (6806800J66C)
Page 36: Board Configuration Switch, S1
Configuration Switch, S1 IPMI Configuration Switch, S2 2.6.3.1 Board Configuration Switch, S1 The CPCI-6200 uses an 8-position SMT configuration switch to: Control the flash bank write-protect.  Select the flash boot image.  Control the safe start ENV settings. ...
Page 37: Table 2-3 S1 Switch Settings
When the PMC1_PCI_FSEL switch is OFF, the maximum PCI bus operation is 100 MHz on PMC1. When it is ON, the maximum PCI bus operation is 100 MHz on PMC1. For more information, PCI Bus Frequency on page CPCI-6200 Installation and Use (6806800J66C)
Page 38: Ipmi Configuration Switch, S2
12 V supply is not available in the system or chassis. 2.6.3.2 IPMI Configuration Switch, S2 The CPCI-6200 uses an 8-position SMT configuration switch to control the IPMI controller settings. The default switch position is OFF. Table 2-4 S2 Switch Settings...
Page 39: Installing The Cpci Baseboard
3. Turn off the AC or DC power, and then remove the AC cord or DC power lines from the system. 4. Remove the chassis or system cover(s) as necessary for access to the CompactPCI modules. CPCI-6200 Installation and Use (6806800J66C)
Page 40 The firmware is shipped from the factory with an appropriate set of defaults. In most cases there is no need to modify the firmware configuration before you boot the operating system. For more information on MOTLoad, see MOTLoad Firmware on page CPCI-6200 Installation and Use (6806800J66C)
Page 41: Removing The Cpci Baseboard
1. Unfasten the two screws on the front panel until the board is detached from the rack frame. 2. Press the red button to unlock handles. 3. Open handles until resistance is encountered. The hot swap switch opens automatically. CPCI-6200 Installation and Use (6806800J66C)
Page 42: Connecting To A Console Port
5. Remove the board from the slot by fully opening the ejector handles. Connecting to a Console Port When the CPCI-6200 is installed in the chassis, you are ready to connect peripherals and apply power to the board. On the CPCI-6200 baseboard, the standard serial console port (COM1) serves as the MOTLoad debugger console port.
Page 43 Login as root with no password. If you want to use IPMI, load the IPMI SMBus driver using: # modprobe ipmi_smb Contact Emerson for kernel patches and additional information on using Linux on the CPCI- 6200. CPCI-6200 Installation and Use (6806800J66C)
Page 44 Hardware Preparation and Installation CPCI-6200 Installation and Use (6806800J66C)
Page 45: Controls, Leds, And Connectors
PCI Bridge 1,2,3 IPMI Controller PCI Express Switch DDR3 DIMM JTAG Header LBC PLD Boot Flash DDR3 DIMM COP Header PCI x1 Battery PCI Bridge PCI Express Expansion Configuration Configuration Connector Switch, S1 Switch, S2 USB Controller CPCI-6200 Installation and Use (6806800J66C)
Page 46: Front Panel
Cutout for PMC Slot 2 covered with filler panel Cutout for PMC Slot 1 covered with filler panel Ethernet Port 1 Ethernet Port 2 USB Port User/Fail LED (Green/Yellow) Serial Port Reset/Abort Switch Hot Swap LED (Blue) CPCI-6200 Installation and Use (6806800J66C)
Page 47: Connectors And Headers
Reset/abort switch on the front panel IPMI serial port (COM2) Planar header for debugging IPMI Serial Port Processor debug header Planar header for probing debug signals Boundary scan header Planar header for boundary scan and PLD/flash programming CPCI-6200 Installation and Use (6806800J66C)
Page 48: Cpci Bus Connector, J1
+3.3 V C/BE[1]# +3.3 V IPMB0_SCL IPMB0_SDA GND1 PERR# DEVSEL# PCIXCAP V(IO) STOP# LOCK# +3.3 V FRAME# IRDY# BD_SEL# TRDY# KEY AREA (Pins 12 - 14) AD[18] AD[17] AD[16] GND1 C/BE[2]# AD[21] +3.3 V AD[20] AD[19] CPCI-6200 Installation and Use (6806800J66C)
Page 49: Cpci Bus Connector, J2
Row A Row B Row C Row D Row E BRSVP2A18 BRSVP2B18 BRSVP2C18 BRSVP2E18 BRSVP2A17 BRSVP2A16 BRSVP2B16 BRSVP2E16 BRSVP2A15 AD[35] AD[34] AD[33] AD[32] AD[38] V(IO) AD[37] AD[36] AD[42] AD[41] AD[40] AD[39] AD[45] V(IO) AD[44] AD[43] CPCI-6200 Installation and Use (6806800J66C)
Page 50: Cpci User I/O Connector, J3
BRSVP2B4 C/BE[7]# C/BE[6]# SYSEN# 1. Defined as SYSEN#. This OV allows the CPCI-6200 to ensure that it is installed into a peripheral slot. 3.3.3 CPCI User I/O Connector, J3 J3 is a five-row user I/O CPCI connector. Note: Row F is ground and is not shown in the table.
Page 51: Cpci Connector, J4
IPMI_PWR—+3.3 V derived from IPMB input power  3.3.4 CPCI Connector, J4 J4 is a five-row CPCI connector that is not used on the CPCI-6200. It is not populated. 3.3.5 CPCI User I/O Connector, J5 J5 is a five-row user I/O CPCI connector.
Page 52: Pci Mezzanine Card (Pmc) Connectors
PMCIO6 PMCIO5 PMCIO4 PMCIO3 PMCIO2 PMCIO1 TMCOM3# I2C_CLK I2C_DATA MXCLK MXSYNC# MXDI MXDO COM4_RXD COM3_RXD COM4_TXD COM4_TXD 3.3.6 PCI Mezzanine Card (PMC) Connectors There are four 64-pin connectors for each PMC slot on the CPCI-6200. CPCI-6200 Installation and Use (6806800J66C)
Page 53 +5 V INTD# PCI_RSVD NC (+3.3Vaux) GNT#/XREQ0# REQ#/XGNT0# +5 V AD31 AD28 AD27 AD25 C/BE3# AD22 AD21 AD19 +5 V AD17 FRAME# IRDY# DEVSEL# +5 V PCIXCAP LOCK# PCI_RSVD PCI_RSVD AD15 AD12 AD11 AD09 +5 V CPCI-6200 Installation and Use (6806800J66C)
Page 54: Table 3-6 Pmc Connector Pinout, J11/J21
Table 3-7 PMC Connector Pinout, J12/J22 +12 V TRST# PCI_RSVD PCI_RSVD PCI_RSVD MOT_RSVD +3.3 V RST# MOT_RSVD +3.3 V MOT_RSVD NC (PME#) AD30 AD29 AD26 AD24 +3.3 V IDSEL AD23 +3.3 V AD20 AD18 AD16 C/BE2# IDSELB CPCI-6200 Installation and Use (6806800J66C)
Page 55: Table 3-7 Pmc Connector Pinout, J12/J22
REQB_L +3.3 V GNTB_L MOT_RSVD MOT_RSVD EREADY NC (RESETOUT_L) ACK64# +3.3 V NC (MONARCH#) Table 3-8 PMC Connector Pinout, J13/J23 J13/J23 PCI_RSVD C/BE7# C/BE6# C/BE5# C/BE4# (Note 1) PAR64 AD63 AD62 AD61 AD60 AD59 AD58 CPCI-6200 Installation and Use (6806800J66C)
Page 56 AD51 AD50 AD49 AD48 AD47 AD46 AD45 AD44 AD43 AD42 AD41 AD40 AD39 AD38 AD37 AD36 AD35 AD34 AD33 AD32 PCI_RSVD PCI_RSVD PCI_RSVD PCI_RSVD Table 3-9 PMC Connector Pin Assignments , J14/J24 J14/J24 PMCIO1 PMCIO2 CPCI-6200 Installation and Use (6806800J66C)
Page 57: Table 3-9 Pmc Connector Pin Assignments , J14/J24
PMCIO22 PMCIO23 PMCIO24 PMCIO25 PMCIO26 PMCIO27 PMCIO28 PMCIO29 PMCIO30 PMCIO31 PMCIO32 PMCIO33 PMCIO34 PMCIO35 PMCIO36 PMCIO37 PMCIO38 PMCIO39 PMCIO40 PMCIO41 PMCIO42 PMCIO43 PMCIO44 PMCIO45 PMCIO46 PMCIO47 PMCIO48 PMCIO49 PMCIO50 PMCIO51 PMCIO52 PMCIO53 PMCIO54 PMCIO55 PMCIO56 CPCI-6200 Installation and Use (6806800J66C)
Page 58: Ethernet Connector
J6 is a single housing with two RJ-45 ports. The pin configuration is based on IEEE standards 802.3ab-1999. 3.3.8 USB Connector There is one standard 4-pin USB connector located on the front panel. Figure 3-2 USB Connector Pinout USB_DATA + USB_DATA - CPCI-6200 Installation and Use (6806800J66C)
Page 59: Serial Port Connector, J16
Pins 1 and 2 indicate board insertion or extraction status. Pin 2 is used with the PCI Bridge while pin 3 is used with the IPMI controller. A closed latch indicates board insertion. In this case, pin 2 and 3 are shorted and FP_EJECTSW = 1, BOARD_EJECT = 0. CPCI-6200 Installation and Use (6806800J66C)
Page 60: Ddr3 So-Dimm Connectors, Xj1 And Xj2
Controls, LEDs, and Connectors 3.3.11 DDR3 SO-DIMM Connectors, XJ1 and XJ2 The CPCI-6200 provides two 204-pin DDR3 SO-UDIMM connectors for installing DDR3 SDRAMs. Table 3-11 DDR3 SO-DIMMs Pinout, XJ1 and XJ2 Pin Number Signal Pin Number Signal Pin Number Signal...
Page 61 DQ43 DQ47 DQS3 DQ26 DQ48 DQ52 DQ27 DQ30 DQ49 DQ53 DQ31 DQS6# DQS6 DQ54 DQ55 DQS8# DQ50 DQS8 DQ51 DQ60 DQ61 DQ56 VREFCA DQ57 DQS7# DQS7 CKE0 CKE1 DQ58 DQ62 DQ59 DQ63 A12/BC# EVENT# VDDSPD CPCI-6200 Installation and Use (6806800J66C)
Page 62: Pci Express Expansion Connector, J17
Pin Number Signal Pin Number Signal Pin Number Signal 3.3.12 PCI Express Expansion Connector, J17 The CPCI-6200 provides PCI Express expansion capability through 76-pin Mictor connector. Table 3-12 PCI Express Expansion Connector Pinout, J17 Pin Number Signal Pin Number Signal TX0_P...
Page 63 Controls, LEDs, and Connectors Table 3-12 PCI Express Expansion Connector Pinout, J17 Pin Number Signal Pin Number Signal TRST# I2C_CLK I2C_DATA PRESENT# CPCI-6200 Installation and Use (6806800J66C)
Page 64: Ipmi Debug And Fw Programming Header, P3
Table 3-13 IPMI Debug Pinout, P3 Pin Number Signal 3.3.14 Processor Debug Header, P4 The CPCI-6200 has a 10-pin header for debugging. This header can debug a DDR or LBC interface. Table 3-14 Processor Debug Header Pinout, P4 Pin Number...
Page 65: Boundary Scan Header, P5
Controls, LEDs, and Connectors 3.3.15 Boundary Scan Header, P5 The CPCI-6200 uses a standard 20-pin boundary scan port header that provides an interface for programming the onboard PLDs, and boundary scan testing and debugging. Table 3-15 Boundary Scan Header Pinout, P5...
Page 66: Pci Express Switch Header, P7
Pin Number CPU_CKSTPO# 3.3.17 PCI Express Switch Header, P7 There is one standard 10-pin header located on the CPCI-6200 that provides the debug capability of the PCI Express device PLX8624 using the I C bus. The connector connects to the Aardvark I C/SPI Host Adapter.
Page 67: Reset/Abort Switch, P2
When switch is pushed for five or more seconds, it is treated as reset function. Front Panel LEDs The CPCI-6200 provides two physical (three logical) LEDs on the front panel. The blue LED indicates hot swap status, and is used during board insertion and extraction.
Page 68: Status Indicators
Controls, LEDs, and Connectors Status Indicators The CPCI-6200 provides four front panel status indicators as well as multiple planar status indicators that are used for general board function status and Ethernet link/speed/activity status. Table 3-19 CPCI-6200 Status Indicators Function Location...
Page 69 Controls, LEDs, and Connectors Table 3-19 CPCI-6200 Status Indicators (continued) Function Location Label Color Description TSEC4 Link/Speed Onboard Yellow - D30 No link Green - D29 Yellow 10/100 BASE-T operation Green 1000 BASE-T operation TSEC4 Activity Onboard No activity Blinking Green Activity is proportional to bandwidth utilization.
Page 70 Controls, LEDs, and Connectors CPCI-6200 Installation and Use (6806800J66C)
Page 71: Functional Description
This board supports front and rear I/O. Access to rear I/O is available with a rear transition module (RTM). The CPCI-6200 provides front panel access to one serial port with a mini DB-9 connector, two10/100/1000 Ethernet ports with two RJ-45 connectors, and one USB port with a type A connector.
Page 72: Figure 4-1 Cpci-6200 Block Diagram
Temp ADT7461 VPD / FRU/SDR 5482 512 Kb XCVR COM1 RS232 512 Kb Tsi381 COM3 PCI6466 COM4 PCI to PCI Universal Bridge Controller SROM 5482 IPMB 1 IPMB 0 Front Panel cPCI cPCI cPCI J1/J2 CPCI-6200 Installation and Use (6806800J66C)
Page 73: Mpc8572 Integrated Processor
The processor is configured to operate at 1.33 or 1.5 GHz core frequency with up to 800 MHz data rate DDR3 memory bus. C Serial Interface and Devices The CPCI-6200 has several I C buses, including two on the processor. The following sections describe each bus and the serial devices connected to each bus.
Page 74: I2C Bus 3
This board supports one bank of memory on each controller, using either 1 GB or 2 GB DDR3 SODIMM. This provides memory configurations of 2 and 4 GB. This board also supports memory speeds of up to 400 MHz. CPCI-6200 Installation and Use (6806800J66C)
Page 75: Timers
I/O registers. The LBC has programmable timing modes to support devices of different access times, as well as device widths of 8, 16, and 32 bits. The CPCI-6200 uses the LBC in general purpose chip select machine (GPCM) mode to interface to two physical banks of onboard flash, MRAM, and onboard 32-bit timers, along with control and status registers.
Page 76 F_WP_SW bit supports both read and write operations. CPCI-6200 provides a dual boot option. You can boot from one of two separate boot images in the boot flash bank called boot block A and boot block B. Boot blocks A and B are both 1 MB in size and are located at the top (highest address) 2 MB of the boot flash memory space.
Page 77: Mram (Magnetoresistive Random Access Memory)
The MRAM is organized as 256 K by 16. 4.7.3 Control and Timers PLD The CPCI-6200 control and timers PLD resides on the local bus. This device provides the following functions: Local bus address latch ...
Page 78: Serial Com Ports
J5 connector. DUART Interface The DUART interface provides two serial ports COM1 and COM2 to CPCI-6200. COM1 provides a front access asynchronous serial port interface using Serial Port 0 from the MPC8572 DUART. The TTL-level signals SIN, SOUT, RTS and CTS from Serial Port 0 are routed through onboard EIA-232 drivers and receivers to the mini DB-9 front panel connector.
Page 79: Pci Express Port
PCIE1[3:0] STN 2, Port 9 STN 2, Port 8 STN 1, Port 6 PCIE4[0] PCIE3[3:0] PCIE2[3:0] Tsi381 Tsi384 Tsi384 Tsi384 PCI-X PCI-X Bus 4 Bus 2 Bus 1 Bus 3 PMC 2 PMC 1 Bridge CPCI-6200 Installation and Use (6806800J66C)
Page 80: Pci/Pci-X Bus
Only 3.3 V I/O PMC modules are supported. 4.10.2 PCI 6466 Universal Bridge (PCI Bus 3) The Compact PCI interface for CPCI-6200 is provided by the PLX PCI6466 universal bridge. The PCI6466 can operate in transparent and non-transparent mode, allowing CPCI-6200 to operate in the system slot or peripheral slot of a chassis.
Page 81: Usb (Pci Bus 4)
1. Switch S1, Position 5 selects PCI 1 bus frequency, while Switch S2, position 8 selects PCI 2 bus frequency. 4.11 Operation Modes CPCI-6200 can be operated in three modes, with the PCI to PCI bridge (PCI6466) behaving differently in each mode.
Page 82: System Controller Mode
In this mode, PCI6466 is configured in universal transparent mode. The red lines indicate active signals, while the gray lines indicate inactive signals. Figure 4-5 System Controller Mode 4.11.2 Peripheral Mode In this mode, PCI6466 is configured in universal non-transparent mode. CPCI-6200 Installation and Use (6806800J66C)
Page 83: Stand Alone Mode
Functional Description The red lines indicate active signals, while the gray lines indicate inactive signals. Figure 4-6 Peripheral Mode 4.11.3 Stand Alone Mode In this mode, PCI6466 is configured in non-transparent mode. CPCI-6200 Installation and Use (6806800J66C)
Page 84: Pci Express Expansion
The red lines indicate active signals, while the gray lines indicate inactive signals. Figure 4-7 Stand Alone Mode 4.12 PCI Express Expansion CPCI-6200 provides an additional module capability through the a 76-pin stacking connector. This connector is connected to the second PCI Express port on the processor. CPCI-6200 Installation and Use (6806800J66C)
Page 85: System Interrupts
Functional Description 4.13 System Interrupts CPCI-6200 provides several sources of interrupts that are handled by the processor. The processor supports 12 external interrupts. Interrupts coming through PCI Express switch (PEX8624) are routed to the first four interrupts (IRQ0 — IRQ3). Interrupts coming through the PCI Express expansion interface are routed to the next four interrupts (IRQ4-IRQ7).
Page 86: Clock Distribution
9446 (Not Used) S_PB_CLK 33/66MHz PCI_BP_CLK0, 33/66MHz PCI_BP_CLK1, 33/66MHz Clock C_PLD_CLK, 66MHz CPCI PCI_BP_CLK2, 33/66MHz J1 / CPLD Buffer PCI_BP_CLK3, 33/66MHz PCI_BP_CLK4, 33/66MHz CY2309 32.6KHz PCI_BP_CLK5, 33/66MHz Crystal 10MHz PCI_BP_CLK6, 33/66MHz M41T83 COM 3/4 TL16C552 CPCI-6200 Installation and Use (6806800J66C)
Page 87: Mpc8572 System Clock
(divide by 2 internally) 4.16 Reset Control Logic There are multiple sources of reset on the CPCI-6200. The following table shows the reset sources and their effect on board reset. The effect of each reset source depends on the board's...
Page 88 Table 4-4 Reset Functions Note Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Reset Type System Wide Local Reset CPU SRESET CPU TRESET HSC Reset IPMI Reset CPU, HRESET CPU, SRESET CPCI-6200 Installation and Use (6806800J66C)
Page 89: Abort/Reset Switch
Secondary CPCI Backplane 4.16.1 Abort/Reset Switch CPCI-6200 uses a single push button switch to provide both the abort and reset functions. When the switch is depressed for less than three seconds, an abort interrupt is generated to the MPC8572 PIC.
Page 90: Reset Timing
Functional Description 4.16.2 Reset Timing Different devices have different reset timing requirements. CPCI-6200 uses a Reset Control PLD to meet their requirements. Table 4-5 Reset Timing Requirements Minimum Reset Actual Reset Device Reset Signal Source of Reset Time Time 8572...
Page 91: Rtc Battery
2. PCI Specification 4.17 RTC Battery The CPCI-6200 provides onboard battery clips for holding a coin cell type battery. The clips allow for the quick and easy replacement of a 3 V button cell lithium battery (CR2430), which provides back-up power to the onboard M41T83 real-time clock (RTC). A battery switching circuit that is built into the RTC provides automatic switching between the 3.3 V and battery...
Page 92: Programming The Ipmi Firmware
4.18.1 Programming the IPMI Firmware The CPCI-6200 provides a 4-pin planar header (P3) for programming IPMI firmware. The IPMI firmware is programmed at the factory before the board is shipped. This section is included to explain how the firmware can be upgraded in the field if needed.
Page 93: Programmable Devices
Functional Description 4.19 Programmable Devices The CPCI-6200 uses many programmable devices that include Boot Flash, CPLDs and SROMs. The following table shows the all programmable devices, their functions and programming methods. Table 4-6 Programming Devices Reference Designator Description Function Pgm Method...
Page 94: Local Bus Control Cpld
This multiplexes the control lines of two serial port interfaces and routes them to the RTM through the backplane. This allows fewer signals to be routed to the RTM thereby conserving the total pin count requirement on J5 connector. CPCI-6200 Installation and Use (6806800J66C)
Page 95: Motload Firmware
The implementation of the CPCI-6200 and its memory requirements are product specific. The CPCI-6200 is offered with a wide range of memory (for example, DRAM, flash). Typically, the smallest amount of onboard DRAM that an Emerson SBC has is 32 MB. Each supported Emerson product line has its own unique CPCI-6200 binary image(s).
Page 96: Motload Commands
MOTLoad Commands CPCI-6200 supports two types of commands (applications): utilities and tests. Both types of commands are invoked from the CPCI-6200 command line in a similar fashion. Beyond that, CPCI-6200 utilities and CPCI-6200 tests are distinctly different. MOTLoad Utility Applications The definition of a MOTLoad utility application is very broad.
Page 97: Using Motload
MOTLoad then performs the specified action. An example of a MOTLoad command line prompt is shown below. The MOTLoad prompt changes according to what product it is used on (for example, HXEB100, CPCI6200, MVME5500). CPCI-6200 Installation and Use (6806800J66C)
Page 98 MOTLoad RTOS Version 2.0, PAL Version 1.1 RM02 Fri Sep 11 09:20:17 MST 2009 If the partial command string cannot be resolved to a single unique command, MOTLoad will inform the user that the command was ambiguous. Example: CPCI-6200 Installation and Use (6806800J66C)
Page 99: Command Line Help
There are a few things to remember when entering a MOTLoad command: Multiple commands are permitted on a single command line, provided they are separated  by a single semicolon(";"). Spaces separate the various fields on the command line (command/arguments/options).  CPCI-6200 Installation and Use (6806800J66C)
Page 100: Motload Command List
Block Fill Byte/Halfword/Word blkCp Block Copy blkFmt Block Format blkRd Block Read blkShow Block Show Device Configuration Data blkVe Block Verify blkWr Block Write bmb bmh bmw Block Move Byte/Halfword/Word Assign/Delete/Display User-Program Break-Points CPCI-6200 Installation and Use (6806800J66C)
Page 101 FAT File System Directory Listing fatGet FAT File System File Load fdShow Display (Show) File Discriptor flashProgram Flash Memory Program flashShow Display Flash Memory Device Configuration Data Go Execute User-Program Direct (Ignore Break-Points) gevDelete Global Environment Variable Delete CPCI-6200 Installation and Use (6806800J66C)
Page 102 Display Network Interface Configuration Data netShut Disable (Shutdown) Network Interface netStats Display Network Interface Statistics Data noCm Turns off Concurrent Mode pciDataRd Read PCI Device Configuration Header Register pciDataWr Write PCI Device Configuration Header Register CPCI-6200 Installation and Use (6806800J66C)
Page 103 Trace (Single-Step) User Program to Address testDisk Test Disk testEnetPtP Ethernet Point-to-Point testNvramRd NVRAM Read testNvramRdWr NVRAM Read/Write (Destructive) testRam RAM Test (Directory) testRamAddr RAM Addressing testRamAlt RAM Alternating testRamBitToggle RAM Bit Toggle testRamBounce RAM Bounce CPCI-6200 Installation and Use (6806800J66C)
Page 104 Tests the accuracy of the watchdog timer device. tftpGet TFTP Get tftpPut TFTP Put time Display Date and Time transparentMode Transparent Mode (Connect to Host) tsShow Display Task Status upLoad Up Load Binary-Data from Target version Display Version String(s) CPCI-6200 Installation and Use (6806800J66C)
Page 105 Then, the data retrieved through the sromRead command will appear as: 16 15 00 1E B5 10 40 65 CB 00 04 06 01 40 09 06 This behavior is normal for these commands on the CPCI-6200. CPCI-6200 Installation and Use (6806800J66C)
Page 106 MOTLoad Firmware CPCI-6200 Installation and Use (6806800J66C)
Page 107: Control Via Ipmi
The watchdog commands are supported by boards providing a system interface and a watchdog type 2 sensor. Table 6-2 Supported Watchdog Commands Command NetFn (Request/Response) Reset Watchdog Timer 0x06/0x07 0x22 Set Watchdog Timer 0x06/0x07 0x24 Get Watchdog Timer 0x06/0x07 0x25 CPCI-6200 Installation and Use (6806800J66C)
Page 108: Ipmi Messaging Commands
0x40 Get SEL Allocation Info 0x0A/0x0B 0x41 Reserve SEL 0x0A/0x0B 0x42 Get SEL Entry 0x0A/0x0B 0x43 Add SEL Entry 0x0A/0x0B 0x44 Clear SEL 0x0A/0x0B 0x47 Get SEL Time 0x0A/0x0B 0x48 Set SEL Time 0x0A/0x0B 0x49 CPCI-6200 Installation and Use (6806800J66C)
Page 109: Sdr Repository Commands
This command returns the error code 0x80 if you attempt to write to the common header, Product Info Area, Board Info Area, Chassis Info Area, Board Connectivity record, Board Address table, Board Power Distribution Record of FRU ID 0. CPCI-6200 Installation and Use (6806800J66C)
Page 110: Sensor Device Commands
0x04/0x05 0x29 Rearm Sensor Events 0x04/0x05 0x2A Get Sensor Reading 0x04/0x05 0x2D Set Sensor Type 0x2E Get Sensor Type 0x04/0x05 0x2F Set Event Receiver 0x04/0x05 0x00 Get Event receiver 0x04/0x05 0x01 Platform Event 0x04/0x05 0x02 CPCI-6200 Installation and Use (6806800J66C)
Page 111: Chassis Device Commands
The IPMC supports the following CompactPCI commands as defined in the PICMG 2.9 specification. Table 6-9 Supported PICMG 2.9 Commands Command NetFn (Request/Response) Get PICMG Properties 0x2C/0x2D 0x00 Get Address Info 0x2C/0x2D 0x01 Get Shelf Address Info 0x2C/0x2D 0x02 CPCI-6200 Installation and Use (6806800J66C)
Page 112: Emerson Specific Commands
Control via IPMI Emerson Specific Commands The Emerson IPMC supports several commands which are not defined in the IPMI or PICMG 2.9 specification but are introduced by Emerson: Firmware upgrade and status change commands. Before sending any of these commands, the shelf management software must check ...
Page 113: Start Firmware Upgrade
Table 6-11 Response Data of Start Firmware Upgrade Byte Data Field Completion Code 0x00: Command executed successfully and target IPMC entered firmware upgrade mode 0x01..0xFF: Error, that means IPMC cannot enter into firmware upgrade mode CPCI-6200 Installation and Use (6806800J66C)
Page 114: Continue Firmware Upgrade
Completion Code 0x00: Command executed successfully 0x1..0xFF: Error, that means the IPMC left the firmware upgrade mode 6.3.1.3 Finish Firmware Upgrade The Finish Firmware Upgrade command makes the target IPMC leave the firmware upgrade mode. CPCI-6200 Installation and Use (6806800J66C)
Page 115: Oem Commands
The following table shows the OEM commands together with their network function and command code. Table 6-16 OEM Commands Command Name NetFn (Request/Response) Description BMC/PM Change Role 0x30 0x03 BMC/PM Change Role on page 116 Get Geographical Address 0x30 0x04 Get Geographical Address on page 116 CPCI-6200 Installation and Use (6806800J66C)
Page 116: Bmc/Pm Change Role
Table 6-18 Response Data of BMC/PM Change Role Byte Data Field Completion code (IPMI) 6.3.2.2 Get Geographical Address This command is used to get the geographical address of the slot which contains the management controller. CPCI-6200 Installation and Use (6806800J66C)
Page 117: Table 6-19 Request Data Of Get Geographical Address
BMC, byte 3 is 0x20 and byte 4 is the I2C address it will have if acting as PM. This last fixed information is needed by system management software to identify the management controller. CPCI-6200 Installation and Use (6806800J66C)
Page 118: Fru Information
Control via IPMI FRU Information The CPCI-6200 provides the following FRU information in FRU ID 0. Table 6-21 FRU Information CPCI-6200 Area Description Value Access Internal use area Not used Board info area Manufacturing According to Intel's Platform Management date/time FRU information Storage Definition v1.0...
Page 119: Table 4-3 Table
Table 6-37 on page 133 VCC5_0 Voltage 0x03 Table 6-38 on page 134 VCC1_0 Voltage 0x07 Table 6-39 on page 135 VPCore Voltage 0x04 Table 6-40 on page 136 The following tables describe the IPMI sensors in detail. CPCI-6200 Installation and Use (6806800J66C)
Page 120 Threshold Mask(Byte 20) 0x00 Base Unit 0x00 (unspecified) Rearm mode 0x01 Auto Hysteresis Support 0x00 No Hysteresis or unspecified Threshold Access Support 0x00 No Tresholds Event Message Control 0x00 Per Threshold / Discrete State Reading Definition CPCI-6200 Installation and Use (6806800J66C)
Page 121: Table 6-24 Aggregate V Sensor
Threshold Access Support 0x00 No Tresholds Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Table 6-25 CPCI Signal Sensor Feature Raw Value Description Sensor Name CPCI Signal Sensor LUN 0x00 Sensor Number 0x83 CPCI-6200 Installation and Use (6806800J66C)
Page 122 Description Sensor Name CPU Status Sensor LUN 0x00 Sensor Number 0x87 Entity ID 0x03 Sensor Type 0x07 Processor Event/Reading Type 0x6F Discrete (sensor-specific) Assertion Event Mask(Byte 15) 0x02 Assertion Event Mask(Byte 16) 0x00 Assertion Events CPCI-6200 Installation and Use (6806800J66C)
Page 123 Sensor Type 0xD2 Emerson-specific Discrete Digital Event/Reading Type 0x6F Discrete (sensor-specific) Assertion Event Mask(Byte 15) 0x0B Assertion Event Mask(Byte 16) 0x00 Deassertion Event Mask(Byte 17) 0x0B Deassertion Event Mask(Byte 18) 0x00 Threshold Mask(Byte 19) 0x0F CPCI-6200 Installation and Use (6806800J66C)
Page 124: Table 6-28 Ejector Switch Sensor
0x01 Threshold Mask(Byte 20) 0x00 Base Unit 0x00 (unspecified) Rearm mode 0x01 Auto Hysteresis Support 0x00 No Hysteresis or unspecified Threshold Access Support 0x00 No Tresholds Event Message Control 0x00 Per Threshold / Discrete State CPCI-6200 Installation and Use (6806800J66C)
Page 125: Table 6-29 Max1617Temp Sensor
Upper critical threshold 0xE4 Upper non-critical threshold 0xDA Lower non-recoverable threshold 0x76 Lower critical threshold 0x79 Lower non-critical threshold 0x7B Rearm mode 0x01 Auto Hysteresis Support 0x03 Readable and Setable Threshold Access Support 0x03 Readable and Setable CPCI-6200 Installation and Use (6806800J66C)
Page 126 0xAA Upper non-recoverable threshold 0xEE Upper critical threshold 0xE4 Upper non-critical threshold 0xDA Lower non-recoverable threshold 0x76 Lower critical threshold 0x79 Lower non-critical threshold 0x7B Rearm mode 0x01 Auto Hysteresis Support 0x03 Readable and Setable CPCI-6200 Installation and Use (6806800J66C)
Page 127 (unspecified) Nominal Reading 0x00 Upper non-recoverable threshold 0x5A Upper critical threshold 0x50 Upper non-critical threshold 0x4B Lower non-recoverable threshold 0x00 (unspecified) Lower critical threshold 0x00 (unspecified) Lower non-critical threshold 0x00 (unspecified) Rearm mode 0x01 Auto CPCI-6200 Installation and Use (6806800J66C)
Page 128: Table 6-32 Signal Status Sensor
Threshold Mask(Byte 20) 0x00 Base Unit 0x00 (unspecified) Rearm mode 0x01 Auto Hysteresis Support 0x00 No Hysteresis or unspecified Threshold Access Support 0x00 No Tresholds Event Message Control 0x00 Per Threshold / Discrete State Reading Definition CPCI-6200 Installation and Use (6806800J66C)
Page 129 1.08 Rearm mode 0x01 Auto Hysteresis Support 0x02 Readable and Setable Threshold Access Support 0x02 Readable and Setable Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading CPCI-6200 Installation and Use (6806800J66C)
Page 130 1.42 Rearm mode 0x01 Auto Hysteresis Support 0x03 Readable and Setable Threshold Access Support 0x03 Readable and Setable Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading CPCI-6200 Installation and Use (6806800J66C)
Page 131 1.71 Rearm mode 0x01 Auto Hysteresis Support 0x03 Readable and Setable Threshold Access Support 0x03 Readable and Setable Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading CPCI-6200 Installation and Use (6806800J66C)
Page 132 3.14 Rearm mode 0x01 Auto Hysteresis Support 0x03 Readable and Setable Threshold Access Support 0x03 Readable and Setable Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading CPCI-6200 Installation and Use (6806800J66C)
Page 133 2.38 Rearm mode 0x01 Auto Hysteresis Support 0x03 Readable and Setable Threshold Access Support 0x03 Readable and Setable Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading CPCI-6200 Installation and Use (6806800J66C)
Page 134 4.74 Rearm mode 0x01 Auto Hysteresis Support 0x03 Readable and Setable Threshold Access Support 0x03 Readable and Setable Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading CPCI-6200 Installation and Use (6806800J66C)
Page 135 0.95 Rearm mode 0x01 Auto Hysteresis Support 0x02 Readable and Setable Threshold Access Support 0x02 Readable and Setable Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading CPCI-6200 Installation and Use (6806800J66C)
Page 136 0.88 Rearm mode 0x01 Auto Hysteresis Support 0x07 Readable and Setable Threshold Access Support 0x07 Readable and Setable Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading CPCI-6200 Installation and Use (6806800J66C)
Page 137: Memory Maps And Addresses
For more information, see to the MPC8572 Reference Manual. Table 7-1 Default Processor Address Map Processor Address Size Definition Start 0x0_0000_0000 0x0_FF6F_FFFF 4087 MB Not mapped 0x0_FF70_0000 0x0_FF7F_FFFF 1 MB MPC8572 CCSR Registers 0x0_FFF8_0000 0x0_FFFF_FFFF 8 MB Flash CPCI-6200 Installation and Use (6806800J66C)
Page 138: Cpci-6200 Memory Map
0x0_F110_0000 0x0_F800_0000 Reserved (15 MB) Flash A 0x0_F1FF_FFFF (128 MB) CS0 0x0_F200_0000 0x0_FFFF_FFFF (224 MB) 0x0_FFFF_FFFF Table 7-2 CPCI-6200 Address Memory Map Processor Address Size Definition Start 0x0_0000_0000 top_dram - 1 dram_size (3.5 GB max) System Memory (DDR3 SO-DIMMs) 0x0_E000_0000...
Page 139: Local Bus Controller Memory Map
Memory Maps and Addresses Table 7-2 CPCI-6200 Address Memory Map (continued) Processor Address Size Definition 0x0_F0C0_0000 0x0_F0FF_FFFF 8 MB PCI 1 I/O Space 0x0_F100_0000 0x0_F10F_FFFF 1 MB MPC8572 CCSR 0x0_F110_0000 0x0_F1FF_FFFF 15 MB Reserved 0x0_F200_0000 0x0_FFFF_FFFF 224 MB Local Bus Controller...
Page 140: System I/O Memory Map
System resources, including system control and status registers, external timers, flash, and DUART, are mapped to a 224 MB address range that is accessible from the CPCI-6200 local bus via the MPC8572 LBC. The memory map is defined in the following table including the LBC bank chip select used to decode the register.
Page 141 F202 0000 External PLD Tick Timer Prescaler Register F202 0010 External PLD Tick Timer 1 Control Register F202 0014 External PLD Tick Timer 1 Compare Register F202 0018 External PLD Tick Timer 1 Counter Register CPCI-6200 Installation and Use (6806800J66C)
Page 142 F203 0000 Nand Chip 1 Data Register F203 0001—F203 7FFF Reserved F203 8000 Nand Chip 2 Data Register F203 8001—F203 FFFF Reserved 1. Reserved for future implementation. 2. 32-bit write only 3. Byte read/write capable CPCI-6200 Installation and Use (6806800J66C)
Page 143: System Status Register
+12 V is not good. PWR_12N_STS -12V Power Status -12 V is good. -12 V is not good. Switch 5 Status Switch 5 is in OFF position (reserved). Switch 5 is in ON position (reserved). CPCI-6200 Installation and Use (6806800J66C)
Page 144: System Control Register
Board Type. These bits indicate the board type. VME SBC PrPMC CPCI Reserved 7.4.2 System Control Register This register provides general board control bits. Table 7-7 System Control Register, 0xF200_0001 Field Operation Reset BRD_RST RSVD RSVD RSVD EEPROM_WP RSVD CPCI-6200 Installation and Use (6806800J66C)
Page 145: Front Panel Leds Control And Status Register
LEDs, or written to by system software to make the corresponding onboard LEDs light up. Table 7-9 Front Panel LED Control/Status Register, 0xF200_0002 Field Operation Reset RSVD RSVD RSVD RSVD RSVD RSVD USR1_LED USR2_LED CPCI-6200 Installation and Use (6806800J66C)
Page 146: Nor Flash Control And Status Register
NOR flash. Table 7-11 NOR Flash Control/Status Register, 0xF200_0003 Field Operation Reset RSVD RSVD RSVD MAP_SEL F_WP_SW F_WP_HW FBT_BLK_SEL FLASH_RDY Table 7-12 NOR Flash Control/Status Register Field Definition RSVD Reserved CPCI-6200 Installation and Use (6806800J66C)
Page 147 Boot block A is selected and mapped to the highest address. See Figure 4-2 on page FLASH_RDY Flash Ready. This bit provides the current state of the flash devices’ Ready/Busy# pins. FLASH is ready. FLASH is not ready. CPCI-6200 Installation and Use (6806800J66C)
Page 148: Interrupt Register 1
TSEC3 interrupt is asserted. TSEC3 interrupt is not asserted. PHY 2 TSEC2 Interrupt TSEC2 interrupt is asserted. TSEC2 interrupt is not asserted. PHY 1 TSEC1 Interrupt TSEC1 interrupt is asserted. TSEC1 interrupt is not asserted. CPCI-6200 Installation and Use (6806800J66C)
Page 149: Interrupt Register 2
CPCI CPLD interrupt is asserted. CPCI CPLD interrupt is not asserted. IPMI_INT IPMI Controller Interrupt IPMI interrupt is asserted. IPMI interrupt is not asserted. RTC_INT RTC Interrupt RTC interrupt is asserted. RTC interrupt is not asserted. CPCI-6200 Installation and Use (6806800J66C)
Page 150: Interrupt Mask Register
TEMP sensor and Abort switch. This register can be read or written by the system software. Table 7-17 Interrupt Mask Register, 0xF200_0006 Field Operation Reset RSVD RSVD RSVD CPCI_PLD_INT_MASK IPMI_INT_MASK RTC_INT_MASK TEMP_INT_MASK ABORT_MASK Table 7-18 Interrupt Mask Register RSVD Reserved CPCI-6200 Installation and Use (6806800J66C)
Page 151: Presence Detect Register
7.4.8 Presence Detect Register This register may be read by the system software to determine the presence of optional devices. Table 7-19 Presence Detect Register, 0xF200_0008 Field Operation Reset RSVD RSVD ERDY2 ERDY1 CPCI-6200 Installation and Use (6806800J66C)
Page 152: Table 7-20 Presence Detect Register Field Definition
PCI Express Expander module is installed. PCI Express Expander module is not installed. PMC2P PMC Module 2 Present PMC module is installed at PMC site 2. PMC module is not installed at PMC site 2. CPCI-6200 Installation and Use (6806800J66C)
Page 153: Nand Flash Chip 1 Control Register
Table 7-22 NAND Flash Chip 1 Control Register Field Definition Command Latch Enable CLE is asserted when the device is accessed. CLE is not asserted when the device is accessed. Address Latch Enable ALE is asserted when the device is accessed. CPCI-6200 Installation and Use (6806800J66C)
Page 154: Nand Flash Chip 1 Select Register
Reset RSVD RSVD RSVD RSVD Table 7-24 NAND Flash Chip 1 Select Register Field Definition Chip Enable 1 CE1 is asserted when the device is accessed. CE1 is not asserted when the device is accessed. CPCI-6200 Installation and Use (6806800J66C)
Page 155: Nand Flash Chip 1 Presence Register
CE4 is not asserted when the device is accessed. RSVD Reserved 7.4.11 NAND Flash Chip 1 Presence Register Table 7-25 NAND Flash Chip 1 Presence Register, 0xF200_0012 Field Operation Reset RSVD RSVD RSVD RSVD RSVD RSVD RSVD CPCI-6200 Installation and Use (6806800J66C)
Page 156: Nand Flash Chip 1 Status Register
Reset RSVD RSVD RSVD RSVD Table 7-28 NAND Flash Chip 1 Status Register Field Definition Ready/Busy 1 Device 1 is ready. Device 1 is busy. Ready/Busy 2 Device 2 is ready. Device 2 is busy. CPCI-6200 Installation and Use (6806800J66C)
Page 157: Nand Flash Chip 2 Control Register
RSVD RSVD RSVD RSVD RSVD Table 7-30 NAND Flash Chip 2 Control Register Field Definition Command Latch Enable CLE is asserted when the device is accessed. CLE is not asserted when the device is accessed. CPCI-6200 Installation and Use (6806800J66C)
Page 158: Nand Flash Chip 2 Select Register
Field Operation Reset RSVD RSVD RSVD RSVD Table 7-32 NAND Flash Chip 2 Select Register Chip Enable 1 CE1 is asserted when the device is accessed. CE1 is not asserted when the device is accessed. CPCI-6200 Installation and Use (6806800J66C)
Page 159: Nand Flash Chip 2 Presence Register
7.4.15 NAND Flash Chip 2 Presence Register Table 7-33 NAND Flash Chip 2 Presence Register, 0xF200_0016 Field Operation Reset RSVD RSVD RSVD RSVD RSVD RSVD RSVD Table 7-34 NAND Flash Chip 2 Presence Register Field Definition Chip 2 Present CPCI-6200 Installation and Use (6806800J66C)
Page 160: Nand Flash Chip 2 Status Register
Reset RSVD RSVD RSVD RSVD Table 7-36 NAND Flash Chip 2 Status Register Field Definition Ready/Busy 1 Device 1 is ready. Device 1 is busy. Ready/Busy 2 Device 2 is ready. Device 2 is busy. CPCI-6200 Installation and Use (6806800J66C)
Page 161: Cpci Control And Status Register
1. Reset value is 0 for system slot and 1 for peripheral slot. Table 7-38 CPCI Control/Status Register Field Definition HS_LED_MASK Hot Swap (Blue) LED Mask Disable the illumination of Blue LED. Enable the illumination of Blue LED. CPCI-6200 Installation and Use (6806800J66C)
Page 162: Geographic Address Read Register
1. The software cannot turn off the hot swap LED by writing this bit to 0 if the hardware has turned on the LED. To turn it off, software must write 1 to mask bit above. 7.4.18 Geographic Address Read Register Table 7-39 Geographic Address Read Register, 0xF200_0019 Field Operation Reset RSVD CPCI-6200 Installation and Use (6806800J66C)
Page 163: Watchdog Timer Load Register
7.4.19 Watchdog Timer Load Register Table 7-41 Watchdog Timer Load Register, 0xF200_0020 Field Operation Reset LOAD Write only, read returns zero LOAD–Counter Load; When the pattern 0xDB is written, the watchdog counter is loaded with the count value. CPCI-6200 Installation and Use (6806800J66C)
Page 164: Watchdog Timer Control Register
Watchdog timer is enabled. Watchdog timer is disabled. SYS_RST System Reset Board and CPCI Backplane reset is generated when a time- out occurs. Board level reset is generated when a time out occurs. RSVD Reserved CPCI-6200 Installation and Use (6806800J66C)
Page 165: Watchdog Timer Resolution Register
Memory Maps and Addresses 7.4.21 Watchdog Timer Resolution Register Table 7-44 Watchdog Timer Resolution Register, 0xE200_0025 Field Operation Reset RSVD RSVD RSVD RSVD WDG_RES Table 7-45 Watchdog Timer Resolution Register RSVD Reserved CPCI-6200 Installation and Use (6806800J66C)
Page 166: Watchdog Timer Count Register
1111 64 ms 7.4.22 Watchdog Timer Count Register Table 7-46 Watchdog Timer Counter Register, 0xF200_0026 Field Operation Reset 15:0 WDG_COUNT 1. This register is not byte writable. It must be written half word (16 bits). CPCI-6200 Installation and Use (6806800J66C)
Page 167: Pld Revision Register
Table 7-47 PLD Revision Register, 0xF200_0030 Field Operation Reset MAJOR_REV MINOR_REV Table 7-48 PLD Revision Register Field Definition MAJOR_REV PLD's Major Revision Bits. It starts from 00. MINOR_REV PLD's Minor Revision Bits. It starts with 01. CPCI-6200 Installation and Use (6806800J66C)
Page 168: Pld Date Code Register
This is a 32-bit general purpose read/write register that is used by software for PLD test or general status bit storage. Table 7-51 Test Register 1, 0xF200_0038 Field Operation Reset 31:0 TEST_1 TEST_1– General purpose 32-bit R/W field CPCI-6200 Installation and Use (6806800J66C)
Page 169: Test Register 2
Register 1. A write to this address will write the uncomplemented data to register TEST_1. 7.4.27 External Timer Registers The CPCI-6200 provides a set of tick timer registers that is used to access four external timers implemented in the PLD. These registers are 32-bit registers and are not byte writable.
Page 170: Control Registers
Tick Timer 4 Control Register–0xF202_0040 (32 bits)  Table 7-54 Tick Timer Control Registers Field Operation Reset 31:11 RSVD INTS CINT EN_INT RSVD COVF Table 7-55 Tick Timer Control Field Definition RSVD Reserved INTS Interrupt Status CINT Clear Interrupt CPCI-6200 Installation and Use (6806800J66C)
Page 171: Compare Registers
Tick Timer 2 Compare Register –0xF202_0024 (32 bits)  Tick Timer 3 Compare Register–0xF202_0034 (32 bits)  Tick Timer 4 Compare Register–0xF202_0044 (32 bits)  Table 7-56 Tick Timer Compare Registers Field Operation Reset 31:0 Tick Timer Compare Value CPCI-6200 Installation and Use (6806800J66C)
Page 172: Counter Registers
Table 7-57 Tick Timer Counter Register Field Operation Reset 31:0 Tick Timer Counter Value When enabled, the tick timer counter register increments with the reference clock value. Software may read or write the counter at any time. CPCI-6200 Installation and Use (6806800J66C)
Page 173: Interrupt Controller
Memory Maps and Addresses Interrupt Controller The CPCI-6200 uses the MPC8572 integrated programmable interrupt controller (PIC) to manage locally generated interrupts.The following table shows the external interrupting devices and interrupt assignments along with corresponding edge/levels and polarities. Table 7-58 Interrupt Assignments...
Page 174: I2C Device Addresses
INTA_N INTB_N INTC_N C Device Addresses A two-wire serial interface for the CPCI-6200 is provided by an I C compatible serial controller integrated into the MPC8572. The MPC8572 I C controller is used by the system software to read the contents of the various I C devices located on the CPCI-6200.
Page 175: Pci/Pci-X Configuration
Reserved 0xA8 Reserved 0xAA Reserved 0xAC Reserved 0xAE Reserved 1. Each SPD defines the physical attributes of each bank of memory. PCI/PCI-X Configuration The following sections detail the PCI/PCI-X configuration of the onboard PCI devices. CPCI-6200 Installation and Use (6806800J66C)
Page 176: Pci Idsel And Interrupt Assignment
Vendor ID Device ID System Controller MPC8572 0x1957 0x0041 PCI-E Switch PEX8624 0x10B5 0x8624 PCI-E-to-PCI Bridge Tsi381 0x10E3 0x8111 PCI-E-to-PCI-X Bridge Tsi384 0x10E3 0x8114 PCI - PCI Bridge PCI6466 0x10B5 0x6540 USB Controller μPD720101 0x1033 0x0035 CPCI-6200 Installation and Use (6806800J66C)
Page 177: Pci Arbitration Assignments
PMC site 2 primary master Tsi384 REQ/GNT[1] PMC site 2 secondary master Tsi384 REQ/GNT[0] PCI6466 primary Side Tsi381 REQ/GNT[0] USB Controller CPCI Bus PCI6466 Secondary Side Backplane CPCI Devices REQ/GNT[6:0] 1. When CPCI-6200 operates in system slot CPCI-6200 Installation and Use (6806800J66C)
Page 178 Memory Maps and Addresses CPCI-6200 Installation and Use (6806800J66C)
Page 179: A Replacing The Battery
Appendix A Replacing the Battery Battery Location For information on the battery’s functional description, see RTC Battery on page RTC Battery CPCI-6200 Installation and Use (6806800J66C)
Page 180: Replacing The Battery
When exchanging the on-board lithium battery, make sure that the new and the old battery are exactly the same battery models. If the respective battery model is not available, contact your local Emerson sales representative for the availability of alternative officially approved battery models.
Page 181: B Related Documentation
Navigate to Solution Services > Technical Documentation Search. Use the search field to look for the appropriate publication. This Web site provides the up-to-date copies of Emerson product documentation. Table B-1 Related Publications Document Title and Source Publication Number...
Page 182: Manufacturer's Publications
MPC8572 Errata Maxim/Dallas Semiconductor MAX3221E/MAX3223E/MAX3243E, 19-1283 Rev 5, 10/03 http://www.maxim-ic.com/ MAX811/MAX812 4-Pin μP Voltage Monitors with Manual Reset Input, 19-0411 Rev 3, 3/99 NEC Electronics America μPD720101 USB2.0 HOST CONTROLLER, S16265EJ3V0DS00, April 2003 http://www.necelam.com http://www.necelam.com/docs/files/S16265EJ3V0DS00.pdf CPCI-6200 Installation and Use (6806800J66C)
Page 183: Related Specifications
PCI Local Bus Specification, PCI Rev 2.2 December 18, 1998 http://www.pcisig.com PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, PCI-X EM 2.0a, August 22, 2003 PCI-X Protocol Addendum to the PCI Local Bus Specification, PCI-X PT 2.0a, July 22, 2003 CPCI-6200 Installation and Use (6806800J66C)
Page 184 CPCI System Management Specification, PICMG 2.9 R 1.0 CPCI Packet Switching Backplane Specification, PICMG 2.16 R1.0 Universal Serial Bus Universal Serial Bus Specification, Revision 2.0 April 27, 2000 http://www.usb.org/developers /docs/ VITA Standards Organization PPMC, ANSI/VITA 32-2003 http://www.vita.com/ PCI-X on PMC, ANSI/VITA 39-2003 CPCI-6200 Installation and Use (6806800J66C)
Page 185: Safety Notes
Emerson and our suppliers take significant steps to make sure that there are no bent pins on the backplane or connector damage to the boards prior to leaving the factory. Bent pins caused by improper installation or by inserting boards with damaged connectors could void the Emerson warranty for the backplane or boards.
Page 186 Before touching the product make sure that your are working in an ESD-safe environment or wear an ESD wrist strap or ESD shoes. Hold the product by its edges and do not touch any components or circuits. CPCI-6200 Installation and Use (6806800J66C)
Page 187 When exchanging the on-board lithium battery, make sure that the new and the old battery are exactly the same battery models. If the respective battery model is not available, contact your local Emerson sales representative for the availability of alternative officially approved battery models.
Page 188 Before removing the RTM from a powered system, power down the slot and the front blade’s payload by opening the lower handle of the front blade and wait until the blue LED is permanently ON. CPCI-6200 Installation and Use (6806800J66C)
Page 189: Sicherheitshinweise
Produkts in einer anderen Anwendung erfordert eine Sicherheitsüberprüfung für diese spezifische Anwendung. Einbau, Wartung und Betrieb dürfen nur von durch Emerson ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden. Die in diesem Handbuch enthaltenen Informationen dienen ausschließlich dazu, das Wissen von Fachpersonal zu ergänzen, können dieses jedoch nicht ersetzen.
Page 190 Sie sicher, dass ausreichend Schutz vor Störstrahlung vorhanden ist. Die Blades müssen mit der Frontblende installiert und alle freien Steckplätze müssen mit Blindblenden abgedeckt sein. Änderungen, die nicht ausdrücklich von Emerson erlaubt sind, können Ihr Recht das System zu betreiben zunichte machen. CPCI-6200 Installation and Use (6806800J66C)
Page 191 Hohe Luftfeuchtigkeit und Kondensat auf den Oberflächen der Produkte kann zu Kurzschlüssen führen. Betreiben Sie die Produkte nur innerhalb der angegebenen Grenzwerte für die relative Luftfeuchtigkeit und Temperatur und stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf den Produkten kein Kondensat befindet. CPCI-6200 Installation and Use (6806800J66C)
Page 192 Wenn SIe die Lithium-Batterie auf dem Produkt austauschen, stellen Sie sicher, dass die alte und die neue Batterie vom gleichen Typ sind. Ist der Batterietyp nicht verfügbar, wenden Sie sich an Emerson um herauszufinden, welcher Batterietyp offiziell alternativ verwendet werden darf.
Page 193: Index
CPCI user I/O connector, J3 CPCI-6200 single board computer CPCI user I/O connector, J5 PMC module DDR3 memory module installing PMC Ethernet connector, J6 interrupts front panel IPMI controller front panel latch, P1 memory module, XJ1 and XJ2 CPCI-6200 Installation and Use (6806800J66C)
Page 194 P2 PCI Express port switches pin assignments configuration switches J12/J22 connectors (905) onboard J13/J23 connectors (905) system interrupts J14/J24 connectors (905) system memory installing PMC module timers installing PMC sites processor unpacking programmable devices board CPCI-6200 Installation and Use (6806800J66C)
Page 196 Precision Cooling Surge & Signal Protection Emerson, Business-Critical Continuity, Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co. All other product or service names are the property of their respective owners.

Emerson CPCI-6200 Installation Manual

Quick Links

Need help?

Questions and answers

Related Manuals for Emerson CPCI-6200

Summary of Contents for Emerson CPCI-6200

Table of Contents