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abi SYSTEM 8 Instruction Manual

Training exercise board fault locator
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TRAINING EXERCISES
SYSTEM 8
Board Fault Locator
ABI Electronics Limited
Dodworth Business Park, Dodworth
Barnsley, South Yorkshire, S75 3SP, United Kingdom.
tel: (01226) 207420 fax: (01226) 207620
web: www.abielectronics.co.uk
email: sales@abielectronics.co.uk

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  • Page 1 TRAINING EXERCISES SYSTEM 8 Board Fault Locator ABI Electronics Limited Dodworth Business Park, Dodworth Barnsley, South Yorkshire, S75 3SP, United Kingdom. tel: (01226) 207420 fax: (01226) 207620 web: www.abielectronics.co.uk email: sales@abielectronics.co.uk...
  • Page 2 Diagnostic Solution and the BoardMaster 8000 PLUS, can be used on the entire board. The board can be used in two ways. The relevant SYSTEM 8 instrument (e.g. the IC Tester) can be opened manually and configured to test a particular component on the training board.
  • Page 3 The purpose of the Training Board is to demonstrate all the functions of BOARDMASTER or SYSTEM 8 modules. By providing examples of circuit and fault conditions the techniques of fault with the equipment will be highlighted. The PCB includes simple circuits for training in basic electronic principles.
  • Page 4 EXERCISE 1 : DIGITAL IC TESTER ACTION Identify the sections of the IC Tester using description and Schematics. DESCRIPTION On first opening the IC Tester there is normally no part loaded from the device library. Within the TestFlow the part is already loaded and cannot be changed by the user, this reduces operator error and speeds up testing.
  • Page 5 DESRIPTION Device selection can be done in different ways. The simplest way is to type the number of the device directly into the test box. The devices can be filtered down to specific groups to make browsing easier. Multiple groups can be selected pressing the SHIFT key and then selecting groups COMMENT For many devices there are prefixes and suffixes.
  • Page 6 COMMENTS If you require a higher current for the UUT you can use an external supply for testing. It is important that the external supply isreferenced to the BFL ground so that its measurements are accurate. By not doing this it might be that the BFL will detect High Voltages and not start the test.
  • Page 7 EXERCISE 5 : TEST RESULTS ANALYSIS ACTION Press START on the IC Tester and observe the Test Results Analysis window. DESCRIPTION The Test Results Analysis window contains three sections, each giving different information. 1. The Truth Table Test Result gives a pass or fail result (green or red) when a Truth Table test has been carried out.
  • Page 8 The connections test on its own may not always highlight the fault but it is an integral part of the ABI test philosophy, without it you will not be able to effectively diagnose a PCB. With a truth table test the integrity of the IC is tested, to test it the system needs to obtain the circuit connections to the IC, these Connections in turn can be used to compare against the connections of a good IC or against the schematic of the PCB.
  • Page 9 DESCRIPTION Operating the NO VCC switch alters the circuit so that there is no supply voltage. This puts the supply voltage below the threshold allowed by the BFL. This is the reason why the VCC pin indicates NOV+. To ensure the correct operation of the Training board a good comparison is achieved when the condition being covered is applied.
  • Page 10 It is important that the PCB be as stable as possible when testing to reduce the effect of interference from external sources to the DUT. Please view presentation titled, "ABI Test Methodology" and "Backdriving: The force behind the functional test" for more detailed information on testing IC's.
  • Page 11 EXERCISE 12 : FLOATING PINS / DRIVEN PINS ACTION Press START on IC Tester. Observe 'FLOT IPML' on pin 10. Press INPUT DRIVEN switch to apply drive to Pin 10 from output on pin 11. Observe FLOT signal change to L1 and also an L1 appearing on pin 11. DESCRIPTION In this step the circuit shows that there is a connection to input pin 10 but it is not being driven as the relay is not being energised.
  • Page 12 DESCRIPTION The Connections test finds Links by changing the input state of one pin and monitoring all subsequent pins for the same change. Pins found to be linked in this manner are then checked by reversing the order of test. There is no limit to how many pins can be shown as linked but there is differentiation between the groups as can be seen by two pins with L1 (one linked pair) and L2 (a separate linked pair not linked to L1).
  • Page 13 DESCRIPTION The shorted pins are directly connected to VCC & GND. The tester cannot drive these pins and they remain in the same state throughout the test. Stimulus is not applied to the pins and the Truth Table test is adjusted accordingly. The OPCT indication on Pin 9 would, in normal circumstances indicate a pin not being driven and not presenting any impedance.For CMOS it could be normal condition from high impedance inputs, it could be a broken bond wire in IC, Tri-state output in OFF state or even...
  • Page 14 DESCRIPTION The Load 0V is caused by the input pin being connected to VCC with a low resistance to Ground (3.5Ohm) The drive channel of the system attempts to pull the pin to a high logic level (>2.4V for this device) but cannot obtain a valid logic High and so indicates that it is loaded to 0V.
  • Page 15 EXERCISE 18 : OUTPUT MID LEVEL WITH LOGIC TRACE ACTION Go to SETUP and select the LOGIC TRACE then exit SETUP. Press START on the IC Tester and note the LOGIC TRACE window. Press the MID-LEVEL switches again and observe the changes to the monitored values on Pin 6 by clicking on the LOGIC TRACE display at the relevant step.
  • Page 16 COMMENTS The indication of an output short is a very positive indicator of a problem. Tri-state or open- collector circuit design can be checked easily against a known good board or, as in all cases, the circuit can be investigated further by checking the components being driven by the output and a choice being made to remove a component and test independently.
  • Page 17 EXERCISE 21 : SIGNAL REMOVAL - BUS DISABLE OUTPUT ACTION Attach clip to U15 (74LS161). Identify and attach the Bus Disable Output (BDO) cable as shown in Schematic. (If Schematics are not available identify the clock signal by using the MIS Oscilloscope). Press START on the IC tester and observe the SIG Pin 2.
  • Page 18 (a relatively high current output IC) to drive a clock signal into a 74LS161. As part of the 74LS161 test, the SYSTEM 8 pin drivers must output a clock signal to the CLK pin (pin 2) to test the functionality of the IC. In this situation, the existing clock on the board under test is "backdriven"...
  • Page 19 Note that the SYSTEM 8 software is aware of the ICs that may require the ground clip and a warning is given in the analysis box after the test.
  • Page 20 COMMENTS Invalid LINKS can be caused by solder shorts, PCB faults or internal IC faults and can be in many configurations on numerous ICs. They may also be caused by novel or unexpected ways of using an IC in a design, which the AUTOMATIC CIRCUIT COMPENSATION software is incapable of resolving.
  • Page 21 EXERCISE 25 : CONFLICTS ACTION Attach SOIC Clip to U10 74LS244. Press STARTon the IC tester and observe Conflict indications CFLT. Attach a BDO LOW to TP1 DIS ADD BUFF (Near the Blue Connector). Observe test result PASS. DESCRIPTION The device being tested has common tri-state outputs on Pins 14,16 & 18. These are conflicting with the outputs on pins 3,5 &...
  • Page 22 ICs which are functionally and pin compatible (providing that the IC is in the SYSTEM 8 test library). If there are changing signals on the device then these need to be removed to allow the proper tests to be carried out.
  • Page 23 EXERCISE 28 : MEMORY ACTION Attach a 40 way clip to the 64 - Way ribbon cable. Connect cable to BFL and clip to U12 EPROM. Note the SETUP and press START on the IC tester. Attach BDO LOW to TP84 DIS CLK stopping counter U15.
  • Page 24 EXERCISE 31 : DIGITAL VI ACTION Clip SOIC Test Clip on U16 74ABT574 Note the SETUP of the test especially V-I voltage range and tolerance. Press STARTon the IC tester and observe results display. Familiarise yourself with the display controls, (<< < > >>), to step through the screens and zoom into single trace made by clicking on the required trace.
  • Page 25 EXERCISE 32 : DIGITAL VI (II) ACTION Clip on U17. Note the SETUP differences, Voltage range +/- 5V (Normal setup +/- 10V). Press START on the IC tester and view the traces in comparison to the MASTER traces. DESCRIPTION In this test the SETUP has been changed to give a more detailed trace around the +/- 5V range.
  • Page 26 EXERCISE 34 : GRAPHICAL TEST GENERATOR ACTION Study the format of the Graphical test Generator Window and consult the supplied document on using the Graphical Test Generator. Practise using outside the TestFlow DESCRIPTION The Graphical Test Generator instrument is designed to allow a user definable digital waveform sequence to be produced.
  • Page 27 EXERCISE 36 : SHORT LOCATION (II) ACTION Remove clip from U10. Leave the jumper in place across the pins. Remove BDO cable and attach Short Locator probes to Auxiilliary I/O on BFL (See Schematic). Using the schematic as guide probe across the IC pins where Link is present. Turn the Tome ON (If not already on) and you will hear the differnent Tones the closer you get to the short.