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[2] Circuit description of control PWB
1. General description
Fig. 2 shows the functional blocks of the control PWB, which is com-
posed of 4 blocks.
MAIN CONTROL BLOCK
(2)
(1)
SFE-LC
(3)
Fig. 2 Control PWB functional block diagram
2. Description of each block
(1) Main control block
The main control block is composed of ROCKWELL 1 chip fax engine
(SFE-LC), ROM (128KByte), RAM (32KByte) and Modem (R96DFXL-
CID). Devices are connected to the bus to control the whole unit.
1) SFE-LC (IC8) : pin-144 QFP (SFE-LC)
2) R96DFXL (IC5) : pin-100 QFP (MODEM)
The FAXENGINE Integrated Facsimile Controllers.
SFE-LC, contains an internal 8 bit microprocessor with an external 2
Mbyte address space and dedicated circuitry optimized for facsimile
image processing and facsimile machine control and monitoring.
MIRQN
A [23:0]
D [7:0]
RDN
WRN
ROMCSN
CSN [1:0]
MCSN
SYNC
REGDMA
WAITN
RASN
CASN[2:0]
DWRN
TONE
GPIO [7:0]/V ID [7:0]
GPIO [10:8]/VDC [2:0]
GPO11/BE/SERIN
GPIO12/CS2N/SCLK
GPIO13/CS3N/TXD
GPIO14/CS4N/RXD
GPIO15/CS5N
GPIO16/IRQ8
GPIO17/IRQ5N
GPIO18/IRQ10N
GP19/RDY/SERO
PM [3:0]/GPO [3:0]
SM [3:0]/GPO [3:0]
–VREF
+VREF
VIN
START
CLK1
CLK1N
CLK2
VIDCTL[1:0]
ROM
MODEM BLOCK
(4)
MODEM
RAM
1K Intermal RAM
MC24 CPU
Shading correction
Line butter
Internal & External Bus Control
External CPU Bus
Internal & External Decode
General I/O
Motor Control
GPIO
Tone
Video Port
SART
Autobaud
Scanner Control & Video
Processing
6-Bit FADC
CCD/CIS Scanner
5ms,A4/B4 Lines
Shading Correction (1:1,1:8)
Edge Enhancement & Dithering
Multilevel B4-A4 Reduction
Dynamic ABC & Contrast Control
PWR/GND
3) 27C1000 (IC1): pin-32 DIP (ROM)
1 time ROM of 1Mbit equipped with software for the main CPU.
4) M5M5255CFP-70LL (IC3): pin-28 SOP (RAM)
Line memory for the main CPU system RAM area and coding/decod-
ing process. Used as the transmission buffer.
Memory of recorded data such as daily report and auto dials. When
the power is turned off, this memory is backed up by the lithium
battery.
MC24 Megacell (8bit Data,24bit Address)
BUS Interface
CPU Bus
DRAM Control
DMA controller
Internal CPU Bus
T.4/T.6 CODEC
BI-level Resolution
Convention
MH, MR, MMR
Haroware
Programmable
Altemate
Reduction &
Compression &
Expansion
Decompression
TEST
Fig. 3
5 – 2
MC24 CPU Control IF
WatchdogTimer
Real Time Clock
Crystal Oscillator
Battery Back-up Circuit
Interrupt Controller
Operator Panel IF
32 keys
8 LEDs
LCD Module
Thermal Printer IF
5 ms Line Time
A4/B4 Lines
TPH ADC
4 Strobe TPH
Latchless TPH
External DMA I/F
DMA Bus
UX-177H
SYSCLK
TSTCLK
DEBUGN
RESETN
XIN
XOUT
VBAT
VDRAM
PWRDWNN
BATRSTN
BATRSTN
OPO [7:0]
OPI [3:0]
LEDCTL
LCDCS
THADIN
PCLK/DMAACK
PDAT
PLAT
STRB [3:0]
STRBPOL/DMAREQ
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