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Pin No.
Pin Name
49
AVSS1
50
OUTR
51
AVDD1
52
FSEL
53
TMOD1
54
TMOD2
55
FLAG
56
CLVS/IPFLAG
57
EXT0/ISRDATA
58
EXT1/ILRCK
59
EXT2/IBCLK
60
TX
61
MCLK
62
MDATA
63
MLD
64
BLKCK
65
SQCK/BCLK
66
SUBQ/LRCK
67
DMUTE/SRDATA
68
STAT
69
NRST
70
SPPOL
71
PMCK
72
SMCK
73
SUBC/SSYNC
74
SBCK/64FS
75
NCLDCK
76
NTEST
77
X1
78
X2
79
DVDD1
80
DVSS1
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I/O
I
Analogue circuit GND.
O
Rch audio output.
I
Analogue circuit power.
I
Noise filter ON/OFF switch input. "L" = ON, "H" = OFF. (Connected to VDD)
I
Terminal mode switch input terminal 1. Normally set to "L". (Connected to GND)
I
Terminal mode switch input terminal 2. Normally set to "L". (Connected to GND)
O
Flag signal output. (Not used)
Command switch: Spindle servo phase synchronizing signal output.
O
"H" = CLV, "L" = Rough servo.
Interpolation flag signal output. "H" = Interpolation. (Not used)
I/O
Command switch: Extension input/output port 0, SRDATA input. (Not used)
Command switch: Extension input/output port 1, LRCK input.
I/O
"H" = Lch audio data, "L" = Rch audio data. (Not used)
I/O
Command switch: Extension input/output port 2, BCLK input. (Not used)
O
Digital audio interface output signal. (Not used)
I
Microcomputer command clock signal input. (Data is latched at loading edge)
I
Microcomputer command data signal input.
I
Microcomputer command load signal input. "L" = Load.
O
Sub-code block clock signal fBLKCK = 75 Hz. (In normal PLAY mode)
I/O
Command switch: Sub-code Q resistor external clock input, SRDATA bit clock output. (Not used)
Command switch: Sub-code Q data output, L, R discrimination signal output.
O
"H" = Lch audio data, "L" = Rch audio data. (Not used)
I/O
Command switch: Muting input, "H" = MUTE. Serial data output. (Connected to GND)
Status signal (CRC, RESY, CLVS, NTTSTOP, SQOK, FLAG6, SENSE,NFLOCK
O
NTLOCK, BSSEL, SUBQ DATA, CDTEXT DATA, SHOCK RESISTANCE READ
DATA).
I
Reset input. "L" = Reset.
O
Spindle motor drive signal output. (Polar output)
O
88.2 kHz clock signal output. (Not uesed)
O
4.2336 MHz clock signal output.
O
Command switch: Sub-code serial output, Sector SYNC output. (Not uesed)
I
Command switch: Clock input for sub-code serial output, 64FS output. (Not used)
O
Sub-code frame clock signal output. (fCLDCK = 7.35 kHz) (Not used)
I
Test terminal, normally set to "H". (Connected to VDD)
I
Quartz oscillator circuit input terminal f = 16.93 MHz.
O
Quartz oscillator circuit output terminal f = 16.93 MHz.
I
Digital circuit power.
I
Digital circuit GND.
– 19 –
Description
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