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SM00026 CL43WP910TAN CL55WP910AN SERVICE MANUAL MANUEL D'ENTRETIEN WARTUNGSHANDBUCH CAUTION: Before servicing this chassis, it is important that the service technician read the “Safety Precautions” and “Product Safety Notices” in this service manual. Data contained within this Service manual is subject to alteration for improvement.
ALL PRODUCTS CE MARK Before any service is performed on the chassis an 1. HITACHI products may contain the CE mark on isolation transformer should be inserted between the the rating plate indicating that the product power line and the product.
POUR TOUS LES PRODUITS LABEL CE Avant d’effectuer une intervention d’entretien sur le 1. Les produits HITACHI peuvent avoir reçu le label châssis, vous devez insérer un transformateur d’isolement CE qui figure sur la plaque signalétique pour indiquer entre la ligne d’alimentation électrique et le produit.
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Hochspannung sollte immer auf den festgelegten Der Gebrauch von Ersatzteilen, die nicht dieselben Wert des Gehäuses beschränkt bleiben und nicht Sicherheitsmerkmale haben wie die empfohlenen mehr. Betrieb bei höherer Spannung kann zum HITACHI Ersatzteile, wie sie in der Ersatzteilliste Versagen Bildröhre oder hoher aufgeführt sind, kann zu elektrischem Schlag, Feuer,...
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BLOCK DIAGRAM EXPLANATION POWER SUPPLY BLOCK Normally Power Supply switching is operated as following. T901:43k–91kHz(Normal),100-125kHz(Stand by) TP91:31k-59kHz(Normal) POWER SUPPLY UTILIZED FOR THE SIGNAL AND AUDIO CIRCUITS: (POWER SUPPLY P.W.B.) The voltages produced are; +33V Stand By +12V also called A12V TV +8.3V TV +5V +36V for Audio Out circuit.
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UP91 POWER SUPPLY BLOCK DIAGRAM POWER SW (POWER SUB P.W.B.) (POWER / DEFLECTION P.W.B.) STAND BY SWITCHED SWITCHED RELAY VT(+33V) +130 REG. LINE VIDEO FUSE +220V FILTER VM OUT 24.5V STBY 12V SW.REG. CONVERGENC +28V RELAY SWITCHING SWITCHED MAIN REGULATOR +8.3V SW.REG.
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Audio Circuit The output from the Tuner U101 is fed via a gain and buffer stage formed by Q209 and Q210 to the SAW Filter X208. The saw filter has two separate characteristics depending on which of the two inputs (on pin 1 and 2 of the SAW Filter) the signal is applied to. Selection is achieved by the combination of Q211 and Q212.
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The SCART outputs on I401 use the following protocol. SCART output Output signal TV audio Monitor Monitor The device is I2C Controlled via pins 9 and 10 and receives a reset from the micro at power up on pin 24. The clock is provided by X401 on pins 62 and 63. The device has three supply rails, 5V Digital (Pin 18), 5v Analogue (Pin 57), and 8v Analogue (Pin 39).
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AUDIO OUTPUT The left and right signals are output from pins 1 and 2 of the PSA1 connector and are then applied to audio amplifier I402(TDA7482) and I403(TDA7482) via the attenuation networks R459 / R461 & R466 / R468. The left and right output stage consists of two TDA7482 which are Class-D amplifier which in this case is driven to give 15W per channel @ 10% thd.
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Auto Digital Convergence (MAGIC FOCUS) System The auto digital convergence system can readjust convergence with one touch operation. The system is composed of 8 photo detectors, an A/D converter, and an optical pattern generator internal GATE ARRAY compared with conventional systems.(As shown in follow Fig.) The System can measure the dislocation of the image in each overscanned area, where 8 photo detectors are located, with respect to another.
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Auto Digital Convergence (MAGIC FOCUS) System Convergence errors If an error message or code appears while performing MAGIC FOCUS or INITIALIZE, ([MUTE],[LANG] while Digital convergence mode ),follow this confirmation and repair method. Turn on power and input any PAL/NTSC signal. Press service switch on Deflection board.
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Note : Error code 6 and 8 are not used . *1 Check RK42,46,50,54,58,62 resistors first. *2 Procedure is shown below Press [MUTE], then [LANG]Key. Initialization process is now in process. Several windows will appear and error will be displayed. *3 Example of error display: Sensor position No.(viewed from front side) CONNECT 1 !
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DEFLECTION Block Diagram of UP91 Deflection Circuit. T he operation of UP91 Deflection Circuit is as shown below. From SIGNAL P.W.B. VERTICAL HORIZONTAL SYNC SYNC VERTICAL DRIVE DEFLECTION CONTROL I702 VERTICAL HORIZONTAL VERTICAL OUTPUT DRIVE PARABOLA 1 I601 Q751 HORIZONTAL HORIZONTAL SIZE VERTICAL COIL OUTPUT...
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SYNC Signal Processor - uPC1885A Vertical Deflection & Geometry Controls. The drive circuit for the vertical and E-W deflection circuits are generated by means of a vertical divider which gets its clock from the line oscillator. The divider is synchronised b y the incoming vertical pulse, generated by the input processor or the feature box.
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Dynamic Focus The operation of the Dynamic Focus circuit is as shown below. 1200Vp-p C.PULSE DF07 DF08 RF35 CF18 RF15 RF21 RF14 RF22 RF25 CF11 V.PARABOLA RF13 DF15 QF09 QF05 QF07 +12V RF08 CF12 CF05 RF16 RF23 RF12 CF06 RF24 CF09 QF03 H.
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H.Linearity The H.Linearity Circuit uses two linearity coils (L752:G,B common and L753:R). T he circuit is as shown below. B H.DY G H.DY R H.DY C765 C766 L 752 L 753 R759 R760 TO S CURVE COLLECTOR PULSE CORRECTION C APACITOR (C762, C763) Fig.
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MicroController Section on the UP91 Chassis The main microcontroller on the UP91 chassis is located at I001 (ST92R195B). This is an 80-pin QFP (quad-flat package) that is surface mounted for compactness. This highly complex device controls many of the other integrated circuits via dedicated input/output lines or the I C bus.
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be accessed from the EPROM/MTP (I002). These lines are also connected to I003 if an SRAM is to be fitted in future. Normally these lines will be changing state (0V to approx. +5V). By placing an oscilloscope on pin 12 of the EPROM/MTP (I002) it can be confirmed that the microcontroller is operating successfully.
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Horizontal and Vertical Synchronisation Connections Pin 48 is the vertical synchronisation input from the deflection stage. This input is used to ensure that the OSD is displayed in a stable vertical position. When the TV is in the standby state, this input is normally low. The vertical input is triggered on the rising edge (positive polarity).
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EEPROM Write Enable Output Pin 22 is the E2 write enable output line, which is connected to pin 7 of the EEPROM (E2). When this output is HIGH (approx. +5V), the E2 cannot be written to (write disable) but data from the device can be read. When this output is low (0V), then data can be written to the E2.
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when the TV is powered up and normally changes state between (+5V and 0V). Pin 24 is the I C bus clock output for clocking the data to other I C peripherals/devices. The clock line is also isconnected from the main chassis when in the standby state or when writing to the EEPROM. This line oscillates at a frequency around 90KHz RS232 Connections Pin 30 is the RS232 Transmit line from the microcontroller.
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This output is high output is high when a PTV is indicated to Horizontal center axis. HBLK-PH Output Pin 41 is used to adjust the phase of the horizontal blanking . EPROM/MTP (I002) The device located in position I002 is used to store the program code needed by the microcontroller to operate the television correctly.
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Miscellaneous Pin 1 (VPP) is the programming voltage input pin (+12.75V needed) used to re-program the device when placed in a special programmer. This pin is always tied to the +5V standby supply, to ensure that the device can never be re-programmed inside the television chassis.
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Supply/Ground Connections Pins 14 and 7 are the +5V and 0V supply connections respectively. This device always has +5V supplied to it, even when the TV is in the standby state. Capacitor C042 is connected across the supply terminal for de-coupling. Chip Enable Connection Pin 1 is connected to the MMU3 output from the microcontroller and is used to select either the MTP or the SRAM.
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Address Connections Pins 1 to 3 are the address lines used to select the I C slave address of the device. On the M24C32 device, these lines must be connected to ground in order to access the device properly. Write Disable Connection Pin 7 is the I C write enable/disable input.
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Pin 14 is the shift data input necessary for transferring the 8 data bits into the device. When this line is HIGH, a logical ‘1’ is latched into the device on the rising edge of SCK. When this line is low during the rising edge of SCK, a logical ‘0’ is stored instead.
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Under normal operating conditions (and when the TV is NOT in service or diagnose modes), pin 10 is disconnected from pin 12 (and pin 12 of scart2). When the TV is in service mode, a PC can be connected to scart 2 to perform diagnostic functions on the chassis (see separate section on diagnostic protocols for more information).
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Expanded A/D&D/A AV3 SW SAV1 TUNER D size in •E SIDE PANEL •E PCF8591 (I008) WOOFER OFF (U101) UVE25-EW54D Main u-con(80pin) E2P ROM E2RD E2P DIS IF/Video Chroma/Analogue SW Head Phone IN •E M.SCL M.SCL •E •E IR IN M.SDA M.SDA AV1 IN •E...
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UP91 Signal circuit description Tuner. The tuner U101, is a frequency synthesis type with an unbalanced input, powered from the +5V rail while the tuning voltage is supplied by the +33V rail, supplied from the power supply circuit. Direct frequency access, channel selection, AGC and AFC functions are controlled via the I2C bus. AGC, AFC and Offset controls may be selected by entering the service menu and selecting the ‘tuner’...
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Synchronisation The sync separator is operated by the Feature Box circuit. Chroma & Luma Processing The IC contains a chrominance bandpass filter , the SECAM cloche and chrominance trap. The filters are calibrated using the tuning frequency and the crystal frequency of the colour decoder. The luminance output signal which is derived from the incoming CVBS or Y/C signal can be varied in amplitude by means of a separate gain control.
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enhancement and digital comb filtering takes place. Separated luminance and chrominance output components are available via a digital to analogue 8 bit converter at pins 1 & 4 of PN01 respectively. Digital Double Scan Conversion Unit (Feature Box) The main feature of this unit is frequency double scan conversion 100Hz interlaced and 50/60Hz progressive scan. Other features of this unit are noise reduction, line flicker reduction, CTI (Colour Transient Improvement), sharpness, vertical zoom and horizontal compression.
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FIG.1 Scan rate conversion mode for display Fig.1 shows the differences between 100Hz interlaced scan and 50/60Hz progressive scan. The biggest advantage of progressive scan is "non-interlacing", but field frequency is kept at 50/60Hz. This means the line construction (density) is twice, compared with 100Hz interlaced scan. Therefore, if progressive scan mode is selected, large area flicker will be still appeared on display, but will eliminate lines flicker.
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Two RGB sources are intended for use by the Digital Convergence Adjustment Signal, while the second is used for the OSD and Teletext. The required input signal has an amplitude of 0.5V Peak-to-Peak. The switching between the internal signal and the OSD signal can be realized via a OSD BLK. The circuit contains switchable matrix circuits for the colour difference signal so that the colour reproduction can be adapted for PAL/SCAM and NTSC.
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circuit produces a compensation signal by differentiated luminance signal. The compensation signal is given some current gain,applied to the auxiliary coil (connectors PVMR, PVMG, PVMB) on the neck of the cathode ray tube (CRT) tocontrol the speed of the electron beam. The VM circuit is located beside CRT base PCB, on the backside of lower part of front cabinet.