Bose AV28 Manual page 10

3.1.1 Processor Clock
U1 is clocked by a crystal inverter-oscillator whose nominal frequency is 27 MHz.
A 10KW resistor (R713) biases one gate of U701, a 74VHCU04 [high-speed, unbuffered] inverter.
The crystal in the inverter's feedback path is designed for a 22pF load, achieved by the series
combination of the two 30pF load capacitors C704 and C707 and other stray capacitance in the
input gates of U1. R714 sets the pole in the oscillator's loop response, and R715 buffers the output
between the oscillator and U1. See sheet 8 of SD254135.
After the signal is buffered by U1, the 27 MHz clock drives the video circuitry. Frequency accuracy
within ±50ppm of this oscillator circuit is necessary for color video operation.
3.1.2 Processor Reset
U703 generates a 140ms reset pulse at power-on and any time the +3.3V supply dips below 2.93
volts (corresponding to an AC line voltage of about 40VACRMS. The pulse is buffered by two of
the gates of U701, a 74VHCU04 inverter, and distributed as active-low /RESET1. The reset signal
ensures reliable startup of U1 at power-up and after a brownout.
See the comments in section 2.4 regarding power-fail detection.
3.2 Memory
See sheet 1 of SD254135.
The U1 memory interface supports both SDRAM and flash memory of various sizes. Both memory
ICs are connected to the same bus, and a chip select chooses between the two devices. The type
of memory cycle that is run depends on which address space is needed.
3.2.1 FLASH
U2 is a 1-megaword by 16-bit Flash memory IC. FLASH memory is nonvolatile, meaning that its
stored data is not lost when the chip loses power. The FLASH is used to store all application
software for the product (including software to run on both of U1's RISC processors and its DSP).
This software is programmed into the FLASH by Manufacturing during In-Circuit Test. The FLASH
also stores nonvolatile user parameters, such as AM/FM presets and OSD setup preferences.
U2 shares the memory address and data bus with U3, but its cycle is different from the SDRAM:
flash access is asynchronous and does not use a memory clock. Address (pins 1-9, 18-24, and
48) and chip select (pin 26) is presented to the chip, and data appears 1 access time later on the
data bus. The flash chip only supplies 16-bit data to U1; the other data bus lines are not driven
during flash access.
U2 can be programmed in-circuit by U1; this allows media center software updates in the field via
CD-ROM. During reprogramming, the new program is held in SDRAM (along with the operating
program) until checksum-verified, then written permanently to FLASH.
Theory of Operation
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