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3-4-4 Processor and Memory Module Matrix Table
Memory Q'ty
for each CPU
1 DIMM
2 DIMM
4 DIMM
6 DIMM
8 DIMM
12 DIMM
NOTE!
l There should be at least one DDR4 DIMM per socket.
l If only one DIMM is populated in a channel, then populate it in the slot furthest away from CPU of that channel.
l Channel 0's on each memory controller (A/E/C/G, I/M/K/O) must be populated with same total capacity per channel (if populated).
l Channel 1's on each memory controller (B/F/D/H, J/N/L/P) must be populated with same total capacity per channel (if populated).
CPU0
B0 A0 A1 D0 C0 C1 G1 G0 H0 E1 E0 F0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
System Hardware Installation
J0 I0 I1 L0 K0 K1 O1 O0 P0 M1M0 N0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
- 26 -
CPU1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
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